Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit fd6ae97b authored by Deepak Kumar's avatar Deepak Kumar Committed by Gerrit - the friendly Code Review server
Browse files

msm: kgsl: Add a quirk to limit UCHE to GBIF read/write transactions 



Add quirk gpu-quirk-limit-uche-gbif-rw to limit the number of read
and write transactions from UCHE block to GBIF. This is needed to
avoid possible deadlock between GBIF, SMMU and MEMNOC and also
helps in enabling/disabling this quirk for different hardware
revisions using dtsi file.

Change-Id: Ic5b95ea0360c2fba4c28b26db26dc7650e3261c4
Signed-off-by: default avatarDeepak Kumar <dkumar@codeaurora.org>
Signed-off-by: default avatarUrvashi Agrawal <urvaagra@codeaurora.org>
parent 53fac10d

Documentation/devicetree/bindings/gpu/adreno.txt

+3 −0
Original line number Diff line number Diff line
@@ -191,6 +191,9 @@ GPU Quirks: 
- qcom,gpu-quirk-hfi-use-reg:

				Use registers to replace DCVS HFI message to avoid GMU failure

				to access system memory during IFPC

- qcom,gpu-quirk-limit-uche-gbif-rw:

				Limit number of read and write transactions from UCHE block to

				GBIF to avoid possible deadlock between GBIF, SMMU and MEMNOC.



KGSL Memory Pools:

- qcom,gpu-mempools:		Container for sets of GPU mempools.Multiple sets

drivers/gpu/msm/adreno.c

+2 −0
Original line number Diff line number Diff line
@@ -946,6 +946,8 @@ static struct { 
			"qcom,gpu-quirk-lmloadkill-disable" },

	{ ADRENO_QUIRK_HFI_USE_REG, "qcom,gpu-quirk-hfi-use-reg" },

	{ ADRENO_QUIRK_SECVID_SET_ONCE, "qcom,gpu-quirk-secvid-set-once" },

	{ ADRENO_QUIRK_LIMIT_UCHE_GBIF_RW,

			"qcom,gpu-quirk-limit-uche-gbif-rw" },

};



static int adreno_of_get_power(struct adreno_device *adreno_dev,

drivers/gpu/msm/adreno.h

+6 −0
Original line number Diff line number Diff line
@@ -144,6 +144,12 @@ 
#define ADRENO_QUIRK_HFI_USE_REG BIT(6)

/* Only set protected SECVID registers once */

#define ADRENO_QUIRK_SECVID_SET_ONCE BIT(7)

/*

 * Limit number of read and write transactions from

 * UCHE block to GBIF to avoid possible deadlock

 * between GBIF, SMMU and MEMNOC.

 */

#define ADRENO_QUIRK_LIMIT_UCHE_GBIF_RW BIT(8)



/* Flags to control command packet settings */

#define KGSL_CMD_FLAGS_NONE             0

drivers/gpu/msm/adreno_a6xx.c

+3 −1
Original line number Diff line number Diff line
@@ -55,7 +55,6 @@ static const struct adreno_vbif_data a630_vbif[] = { 


static const struct adreno_vbif_data a615_gbif[] = {

	{A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3},

	{A6XX_UCHE_GBIF_GX_CONFIG, 0x10200F9},

	{0, 0},

};
@@ -669,6 +668,9 @@ static void a6xx_start(struct adreno_device *adreno_dev) 
	adreno_vbif_start(adreno_dev, a6xx_vbif_platforms,

			ARRAY_SIZE(a6xx_vbif_platforms));



	if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_LIMIT_UCHE_GBIF_RW))

		kgsl_regwrite(device, A6XX_UCHE_GBIF_GX_CONFIG, 0x10200F9);



	/* Make all blocks contribute to the GPU BUSY perf counter */

	kgsl_regwrite(device, A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xFFFFFFFF);