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Commit fd023f20 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: update clock entries to support cphy"

parents da491ada febae330

arch/arm64/boot/dts/qcom/sm8150-sde-display.dtsi

+16 −4
Original line number Diff line number Diff line
@@ -458,10 +458,16 @@ 


		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			 <&mdss_dsi0_pll PCLK_MUX_0_CLK>,

			 <&mdss_dsi0_pll CPHY_BYTECLK_SRC_0_CLK>,

			 <&mdss_dsi0_pll CPHY_PCLK_SRC_0_CLK>,

			 <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,

			 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;

			 <&mdss_dsi1_pll PCLK_MUX_1_CLK>,

			 <&mdss_dsi1_pll CPHY_BYTECLK_SRC_1_CLK>,

			 <&mdss_dsi1_pll CPHY_PCLK_SRC_1_CLK>;

		clock-names = "mux_byte_clk0", "mux_pixel_clk0",

			      "mux_byte_clk1", "mux_pixel_clk1";

			      "cphy_byte_clk0", "cphy_pixel_clk0",

			      "mux_byte_clk1", "mux_pixel_clk1",

			      "cphy_byte_clk1", "cphy_pixel_clk1";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -508,10 +514,16 @@ 


		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			 <&mdss_dsi0_pll PCLK_MUX_0_CLK>,

			 <&mdss_dsi0_pll CPHY_BYTECLK_SRC_0_CLK>,

			 <&mdss_dsi0_pll CPHY_PCLK_SRC_0_CLK>,

			 <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,

			 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;

			 <&mdss_dsi1_pll PCLK_MUX_1_CLK>,

			 <&mdss_dsi1_pll CPHY_BYTECLK_SRC_1_CLK>,

			 <&mdss_dsi1_pll CPHY_PCLK_SRC_1_CLK>;

		clock-names = "mux_byte_clk0", "mux_pixel_clk0",

			      "mux_byte_clk1", "mux_pixel_clk1";

			      "cphy_byte_clk0", "cphy_pixel_clk0",

			      "mux_byte_clk1", "mux_pixel_clk1",

			      "cphy_byte_clk1", "cphy_pixel_clk1";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi1_active &sde_te1_active>;