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Commit fca179aa authored by Yunyun Cao's avatar Yunyun Cao Committed by Gerrit - the friendly Code Review server
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msm: ais: use CDM to update wm image address 



Use CDM to update wm image address instead of direct write.
and remove the buffer fifo which doesn't needed for CDM.
Use separated reg_val_pair for each RDI path to update wm,
otherwise, it will be overwritten to cause fps drop.

Change-Id: If86cc21ade3322572df4a3162f6fd33a91535611
Signed-off-by: default avatarYunyun Cao <yunyunc@codeaurora.org>
parent 6b835cdb

drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c

+14 −123
Original line number Diff line number Diff line
@@ -28,11 +28,6 @@ 
#include "cam_debug_util.h"

#include "cam_cpas_api.h"



static void __iomem *mem_base[CAM_VFE_HW_NUM_MAX];

static struct kfifo *g_addr_fifo[CAM_VFE_HW_NUM_MAX];

static struct kfifo *g_buffer_fifo[CAM_VFE_HW_NUM_MAX];

static spinlock_t *g_lock[CAM_VFE_HW_NUM_MAX];



static const char drv_name[] = "vfe_bus";



#define CAM_VFE_BUS_IRQ_REG0                     0
@@ -115,9 +110,6 @@ struct cam_vfe_bus_ver2_common_data { 
	void                                       *vfe_irq_controller;

	struct cam_vfe_bus_ver2_reg_offset_common  *common_reg;

	struct cam_vfe_bus_ver2_reg_data           *reg_data;

	uint32_t                                    io_buf_update[

		MAX_REG_VAL_PAIR_SIZE];



	struct cam_vfe_bus_irq_evt_payload          evt_payload[

		CAM_VFE_BUS_VER2_PAYLOAD_MAX];

	struct list_head                            free_payload_list;
@@ -134,6 +126,8 @@ struct cam_vfe_bus_ver2_wm_resource_data { 
	struct cam_vfe_bus_ver2_common_data            *common_data;

	struct cam_vfe_bus_ver2_reg_offset_bus_client  *hw_regs;

	void                                *ctx;

	uint32_t                                    io_buf_update[

		MAX_REG_VAL_PAIR_SIZE];



	uint32_t             irq_enabled;
@@ -165,7 +159,6 @@ struct cam_vfe_bus_ver2_wm_resource_data { 
	uint32_t             en_cfg;

	uint32_t             is_dual;

	uint32_t             is_lite;

	uint32_t             is_streaming;

};



struct cam_vfe_bus_ver2_comp_grp_data {
@@ -217,9 +210,6 @@ struct cam_vfe_bus_ver2_priv { 
	struct cam_isp_resource_node  bus_client[CAM_VFE_BUS_VER2_MAX_CLIENTS];

	struct cam_isp_resource_node  comp_grp[CAM_VFE_BUS_VER2_COMP_GRP_MAX];

	struct cam_isp_resource_node  vfe_out[CAM_VFE_BUS_VER2_VFE_OUT_MAX];

	struct kfifo addr_fifo[CAM_VFE_BUS_VER2_MAX_CLIENTS];

	struct kfifo buffer_fifo[CAM_VFE_BUS_VER2_MAX_CLIENTS];

	spinlock_t fifo_lock[CAM_VFE_BUS_VER2_MAX_CLIENTS];



	struct list_head                    free_comp_grp;

	struct list_head                    free_dual_comp_grp;
@@ -1248,7 +1238,6 @@ static int cam_vfe_bus_start_wm(struct cam_isp_resource_node *wm_res) 
	CAM_DBG(CAM_ISP, "enable WM res %d offset 0x%x val 0x%x",

		rsrc_data->index, (uint32_t) rsrc_data->hw_regs->cfg,

		rsrc_data->en_cfg);

	rsrc_data->is_streaming = CAM_ISP_RESOURCE_STATE_STREAMING;



	wm_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING;
@@ -1277,12 +1266,6 @@ static int cam_vfe_bus_stop_wm(struct cam_isp_resource_node *wm_res) 
			wm_res->irq_handle);



	wm_res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED;

	rsrc_data->is_streaming = CAM_ISP_RESOURCE_STATE_RESERVED;



	kfifo_reset(

	&g_addr_fifo[rsrc_data->common_data->core_index][rsrc_data->index]);

	kfifo_reset(

	&g_buffer_fifo[rsrc_data->common_data->core_index][rsrc_data->index]);



	return rc;

}
@@ -1343,8 +1326,6 @@ static int cam_vfe_bus_handle_wm_done_bottom_half(void *wm_node, 
		(wm_res == NULL) ? NULL : wm_res->res_priv;

	uint32_t  *cam_ife_irq_regs;

	uint32_t   status_reg;

	uint32_t device_addr;

	struct kfifo *address_fifo;



	if (!evt_payload || !rsrc_data)

		return rc;
@@ -1364,20 +1345,6 @@ static int cam_vfe_bus_handle_wm_done_bottom_half(void *wm_node, 
		cam_vfe_bus_put_evt_payload(rsrc_data->common_data,

			&evt_payload);



	spin_lock_bh(

		&g_lock[rsrc_data->common_data->core_index][rsrc_data->index]);



	address_fifo =

		&g_addr_fifo

		[rsrc_data->common_data->core_index][rsrc_data->index];



	if (!kfifo_is_empty(address_fifo))

		kfifo_out(address_fifo,

		&device_addr, sizeof(uint32_t));



	spin_unlock_bh(

		&g_lock[rsrc_data->common_data->core_index][rsrc_data->index]);



	return rc;

}
@@ -2870,7 +2837,6 @@ static int cam_vfe_bus_update_ubwc_regs( 
static int cam_vfe_bus_update_wm(void *priv, void *cmd_args,

	uint32_t arg_size)

{

	struct cam_vfe_bus_ver2_priv             *bus_priv;

	struct cam_isp_hw_get_cmd_update         *update_buf;

	struct cam_buf_io_cfg                    *io_cfg;

	struct cam_vfe_bus_ver2_vfe_out_data     *vfe_out_data = NULL;
@@ -2880,10 +2846,7 @@ static int cam_vfe_bus_update_wm(void *priv, void *cmd_args, 
	uint32_t  i, j, k, size = 0;

	uint32_t  frame_inc = 0, val;

	uint32_t loop_size = 0;

	uint32_t image_buf;

	uint32_t output_image_buf;



	bus_priv = (struct cam_vfe_bus_ver2_priv  *) priv;

	update_buf =  (struct cam_isp_hw_get_cmd_update *) cmd_args;



	vfe_out_data = (struct cam_vfe_bus_ver2_vfe_out_data *)
@@ -2901,7 +2864,6 @@ static int cam_vfe_bus_update_wm(void *priv, void *cmd_args, 
		return -EINVAL;

	}



	reg_val_pair = &vfe_out_data->common_data->io_buf_update[0];

	io_cfg = update_buf->wm_update->io_cfg;



	for (i = 0, j = 0; i < vfe_out_data->num_wm; i++) {
@@ -2913,7 +2875,9 @@ static int cam_vfe_bus_update_wm(void *priv, void *cmd_args, 
		}



		wm_data = vfe_out_data->wm_res[i]->res_priv;

		reg_val_pair = &wm_data->io_buf_update[0];

		ubwc_client = wm_data->hw_regs->ubwc_regs;



		/* update width register */

		CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j,

			wm_data->hw_regs->buffer_width_cfg,
@@ -2992,57 +2956,13 @@ static int cam_vfe_bus_update_wm(void *priv, void *cmd_args, 
					update_buf->wm_update->image_buf[i] +

					io_cfg->planes[i].meta_size +

					k * frame_inc);

			else {



				spin_lock_bh(

					&bus_priv->fifo_lock[wm_data->index]);



				image_buf =

					update_buf->wm_update->image_buf[i] +

					wm_data->offset + k * frame_inc;





				if (!kfifo_is_full(

					&bus_priv->buffer_fifo

					[wm_data->index])) {

					kfifo_in(

					&bus_priv->buffer_fifo[wm_data->index],

					&image_buf, sizeof(uint32_t));

				} else

					CAM_ERR(CAM_ISP, "buffer_fifo full!");



				while ((!kfifo_is_full(

					&bus_priv->addr_fifo[wm_data->index]))

					&& (!kfifo_is_empty

					(&bus_priv->buffer_fifo

					[wm_data->index]))) {

					kfifo_out(

					&bus_priv->buffer_fifo[wm_data->index],

					&output_image_buf,

					sizeof(uint32_t));



					if (wm_data->is_streaming ==

					CAM_ISP_RESOURCE_STATE_STREAMING)

						cam_io_w_mb(output_image_buf,

						bus_priv->common_data.mem_base +

						wm_data->hw_regs->image_addr);

			else

				CAM_VFE_ADD_REG_VAL_PAIR(

				reg_val_pair,

				j,

				wm_data->hw_regs->image_addr,

						output_image_buf);



					kfifo_in(

					&bus_priv->addr_fifo[wm_data->index],

					&output_image_buf,

					sizeof(uint32_t));

				}

				spin_unlock_bh(

					&bus_priv->fifo_lock[wm_data->index]);

			}





				update_buf->wm_update->image_buf[i] +

				wm_data->offset + k * frame_inc);

		}



		CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j,
@@ -3099,7 +3019,7 @@ static int cam_vfe_bus_update_hfr(void *priv, void *cmd_args, 
		return -EINVAL;

	}



	reg_val_pair = &vfe_out_data->common_data->io_buf_update[0];



	hfr_cfg = update_hfr->hfr_update;



	for (i = 0, j = 0; i < vfe_out_data->num_wm; i++) {
@@ -3112,6 +3032,8 @@ static int cam_vfe_bus_update_hfr(void *priv, void *cmd_args, 


		wm_data = vfe_out_data->wm_res[i]->res_priv;



		reg_val_pair = &wm_data->io_buf_update[0];



		if (wm_data->index <= 2 && hfr_cfg->subsample_period > 3) {

			CAM_ERR(CAM_ISP,

				"RDI doesn't support irq subsample period %d",
@@ -3521,16 +3443,6 @@ int cam_vfe_bus_ver2_init( 
		CAM_VFE_BUS_ADDR_NO_SYNC_DEFAULT_VAL;

	bus_priv->common_data.camera_hw_version = camera_hw_version;



	mem_base[bus_priv->common_data.hw_intf->hw_idx] =

		bus_priv->common_data.mem_base;

	g_addr_fifo[bus_priv->common_data.hw_intf->hw_idx] =

		&bus_priv->addr_fifo[0];

	g_buffer_fifo[bus_priv->common_data.hw_intf->hw_idx] =

		&bus_priv->buffer_fifo[0];

	g_lock[bus_priv->common_data.hw_intf->hw_idx] =

		&bus_priv->fifo_lock[0];





	mutex_init(&bus_priv->common_data.bus_mutex);



	rc = cam_irq_controller_init(drv_name, bus_priv->common_data.mem_base,
@@ -3552,23 +3464,6 @@ int cam_vfe_bus_ver2_init( 
			CAM_ERR(CAM_ISP, "Init WM failed rc=%d", rc);

			goto deinit_wm;

		}

		rc = kfifo_alloc(&bus_priv->addr_fifo[i],

			sizeof(uint32_t) * MAX_FIFO_DEPTH,

			GFP_KERNEL);

		if (rc < 0) {

			CAM_ERR(CAM_ISP, "addr_fifo kfifo_alloc rc=%d", rc);

			goto deinit_wm;

		}

		rc = kfifo_alloc(&bus_priv->buffer_fifo[i],

			sizeof(uint32_t) * MAX_NUM_OF_OUTPUT_BUFFERS,

			GFP_KERNEL);

		if (rc < 0) {

			CAM_ERR(CAM_ISP,

			"buffer_fifo kfifo_alloc rc=%d",

			rc);

			goto deinit_wm;

		}

		spin_lock_init(&bus_priv->fifo_lock[i]);

	}



	for (i = 0; i < CAM_VFE_BUS_VER2_COMP_GRP_MAX; i++) {
@@ -3669,10 +3564,6 @@ int cam_vfe_bus_ver2_deinit( 
		if (rc < 0)

			CAM_ERR(CAM_ISP,

				"Deinit WM failed rc=%d", rc);



		kfifo_free(&bus_priv->addr_fifo[i]);



		kfifo_free(&bus_priv->buffer_fifo[i]);

	}



	for (i = 0; i < CAM_VFE_BUS_VER2_COMP_GRP_MAX; i++) {