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Commit fb4a3d35 authored by Gabor Juhos's avatar Gabor Juhos Committed by John W. Linville
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ath9k: uninline ath9k_io{read,write}32 routines 



The spin_lock handling uses lots of instructions on some archs.
With this patch the size of the ath9k module will be significantly
smaller.

Signed-off-by: default avatarGabor Juhos <juhosg@openwrt.org>
Acked-by: default avatarLuis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 5cff20e6

drivers/net/wireless/ath/ath9k/ath9k.h

+2 −31
Original line number Diff line number Diff line
@@ -697,36 +697,7 @@ void ath9k_wiphy_pause_all_forced(struct ath_softc *sc, 
bool ath9k_wiphy_scanning(struct ath_softc *sc);

void ath9k_wiphy_work(struct work_struct *work);



/*

 * Read and write, they both share the same lock. We do this to serialize

 * reads and writes on Atheros 802.11n PCI devices only. This is required

 * as the FIFO on these devices can only accept sanely 2 requests. After

 * that the device goes bananas. Serializing the reads/writes prevents this

 * from happening.

 */



static inline void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)

{

	if (ah->config.serialize_regmode == SER_REG_MODE_ON) {

		unsigned long flags;

		spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);

		iowrite32(val, ah->ah_sc->mem + reg_offset);

		spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);

	} else

		iowrite32(val, ah->ah_sc->mem + reg_offset);

}



static inline unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)

{

	u32 val;

	if (ah->config.serialize_regmode == SER_REG_MODE_ON) {

		unsigned long flags;

		spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);

		val = ioread32(ah->ah_sc->mem + reg_offset);

		spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);

	} else

		val = ioread32(ah->ah_sc->mem + reg_offset);

	return val;

}

void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val);

unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset);



#endif /* ATH9K_H */

drivers/net/wireless/ath/ath9k/hw.c

+32 −0
Original line number Diff line number Diff line
@@ -84,6 +84,38 @@ static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 
		return ath9k_hw_mac_clks(ah, usecs);

}



/*

 * Read and write, they both share the same lock. We do this to serialize

 * reads and writes on Atheros 802.11n PCI devices only. This is required

 * as the FIFO on these devices can only accept sanely 2 requests. After

 * that the device goes bananas. Serializing the reads/writes prevents this

 * from happening.

 */



void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)

{

	if (ah->config.serialize_regmode == SER_REG_MODE_ON) {

		unsigned long flags;

		spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);

		iowrite32(val, ah->ah_sc->mem + reg_offset);

		spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);

	} else

		iowrite32(val, ah->ah_sc->mem + reg_offset);

}



unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)

{

	u32 val;

	if (ah->config.serialize_regmode == SER_REG_MODE_ON) {

		unsigned long flags;

		spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);

		val = ioread32(ah->ah_sc->mem + reg_offset);

		spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);

	} else

		val = ioread32(ah->ah_sc->mem + reg_offset);

	return val;

}



bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)

{

	int i;