mmc: dw_mmc: Add Synopsys DesignWare mmc host driver.

	help

	  If you say yes here SD-Cards may work on the EZkit.

config MMC_DW

	tristate "Synopsys DesignWare Memory Card Interface"

	depends on ARM

	help

	  This selects support for the Synopsys DesignWare Mobile Storage IP

	  block, this provides host support for SD and MMC interfaces, in both

	  PIO and external DMA modes.

config MMC_DW_IDMAC

	bool "Internal DMAC interface"

	depends on MMC_DW

	help

	  This selects support for the internal DMAC block within the Synopsys

	  Designware Mobile Storage IP block. This disables the external DMA

	  interface.

config MMC_SH_MMCIF

	tristate "SuperH Internal MMCIF support"

	depends on MMC_BLOCK && (SUPERH || ARCH_SHMOBILE)

obj-$(CONFIG_MMC_CB710)	+= cb710-mmc.o

obj-$(CONFIG_MMC_VIA_SDMMC)	+= via-sdmmc.o

obj-$(CONFIG_SDH_BFIN)		+= bfin_sdh.o

obj-$(CONFIG_MMC_DW)		+= dw_mmc.o

obj-$(CONFIG_MMC_SH_MMCIF)	+= sh_mmcif.o

obj-$(CONFIG_MMC_JZ4740)	+= jz4740_mmc.o

obj-$(CONFIG_MMC_USHC)		+= ushc.o

/*

 * Synopsys DesignWare Multimedia Card Interface driver

 *  (Based on NXP driver for lpc 31xx)

 *

 * Copyright (C) 2009 NXP Semiconductors

 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 */

#ifndef _DW_MMC_H_

#define _DW_MMC_H_

#define SDMMC_CTRL		0x000

#define SDMMC_PWREN		0x004

#define SDMMC_CLKDIV		0x008

#define SDMMC_CLKSRC		0x00c

#define SDMMC_CLKENA		0x010

#define SDMMC_TMOUT		0x014

#define SDMMC_CTYPE		0x018

#define SDMMC_BLKSIZ		0x01c

#define SDMMC_BYTCNT		0x020

#define SDMMC_INTMASK		0x024

#define SDMMC_CMDARG		0x028

#define SDMMC_CMD		0x02c

#define SDMMC_RESP0		0x030

#define SDMMC_RESP1		0x034

#define SDMMC_RESP2		0x038

#define SDMMC_RESP3		0x03c

#define SDMMC_MINTSTS		0x040

#define SDMMC_RINTSTS		0x044

#define SDMMC_STATUS		0x048

#define SDMMC_FIFOTH		0x04c

#define SDMMC_CDETECT		0x050

#define SDMMC_WRTPRT		0x054

#define SDMMC_GPIO		0x058

#define SDMMC_TCBCNT		0x05c

#define SDMMC_TBBCNT		0x060

#define SDMMC_DEBNCE		0x064

#define SDMMC_USRID		0x068

#define SDMMC_VERID		0x06c

#define SDMMC_HCON		0x070

#define SDMMC_BMOD		0x080

#define SDMMC_PLDMND		0x084

#define SDMMC_DBADDR		0x088

#define SDMMC_IDSTS		0x08c

#define SDMMC_IDINTEN		0x090

#define SDMMC_DSCADDR		0x094

#define SDMMC_BUFADDR		0x098

#define SDMMC_DATA		0x100

#define SDMMC_DATA_ADR		0x100

/* shift bit field */

#define _SBF(f, v)		((v) << (f))

/* Control register defines */

#define SDMMC_CTRL_USE_IDMAC		BIT(25)

#define SDMMC_CTRL_CEATA_INT_EN		BIT(11)

#define SDMMC_CTRL_SEND_AS_CCSD		BIT(10)

#define SDMMC_CTRL_SEND_CCSD		BIT(9)

#define SDMMC_CTRL_ABRT_READ_DATA	BIT(8)

#define SDMMC_CTRL_SEND_IRQ_RESP	BIT(7)

#define SDMMC_CTRL_READ_WAIT		BIT(6)

#define SDMMC_CTRL_DMA_ENABLE		BIT(5)

#define SDMMC_CTRL_INT_ENABLE		BIT(4)

#define SDMMC_CTRL_DMA_RESET		BIT(2)

#define SDMMC_CTRL_FIFO_RESET		BIT(1)

#define SDMMC_CTRL_RESET		BIT(0)

/* Clock Enable register defines */

#define SDMMC_CLKEN_LOW_PWR		BIT(16)

#define SDMMC_CLKEN_ENABLE		BIT(0)

/* time-out register defines */

#define SDMMC_TMOUT_DATA(n)		_SBF(8, (n))

#define SDMMC_TMOUT_DATA_MSK		0xFFFFFF00

#define SDMMC_TMOUT_RESP(n)		((n) & 0xFF)

#define SDMMC_TMOUT_RESP_MSK		0xFF

/* card-type register defines */

#define SDMMC_CTYPE_8BIT		BIT(16)

#define SDMMC_CTYPE_4BIT		BIT(0)

#define SDMMC_CTYPE_1BIT		0

/* Interrupt status & mask register defines */

#define SDMMC_INT_SDIO			BIT(16)

#define SDMMC_INT_EBE			BIT(15)

#define SDMMC_INT_ACD			BIT(14)

#define SDMMC_INT_SBE			BIT(13)

#define SDMMC_INT_HLE			BIT(12)

#define SDMMC_INT_FRUN			BIT(11)

#define SDMMC_INT_HTO			BIT(10)

#define SDMMC_INT_DTO			BIT(9)

#define SDMMC_INT_RTO			BIT(8)

#define SDMMC_INT_DCRC			BIT(7)

#define SDMMC_INT_RCRC			BIT(6)

#define SDMMC_INT_RXDR			BIT(5)

#define SDMMC_INT_TXDR			BIT(4)

#define SDMMC_INT_DATA_OVER		BIT(3)

#define SDMMC_INT_CMD_DONE		BIT(2)

#define SDMMC_INT_RESP_ERR		BIT(1)

#define SDMMC_INT_CD			BIT(0)

#define SDMMC_INT_ERROR			0xbfc2

/* Command register defines */

#define SDMMC_CMD_START			BIT(31)

#define SDMMC_CMD_CCS_EXP		BIT(23)

#define SDMMC_CMD_CEATA_RD		BIT(22)

#define SDMMC_CMD_UPD_CLK		BIT(21)

#define SDMMC_CMD_INIT			BIT(15)

#define SDMMC_CMD_STOP			BIT(14)

#define SDMMC_CMD_PRV_DAT_WAIT		BIT(13)

#define SDMMC_CMD_SEND_STOP		BIT(12)

#define SDMMC_CMD_STRM_MODE		BIT(11)

#define SDMMC_CMD_DAT_WR		BIT(10)

#define SDMMC_CMD_DAT_EXP		BIT(9)

#define SDMMC_CMD_RESP_CRC		BIT(8)

#define SDMMC_CMD_RESP_LONG		BIT(7)

#define SDMMC_CMD_RESP_EXP		BIT(6)

#define SDMMC_CMD_INDX(n)		((n) & 0x1F)

/* Status register defines */

#define SDMMC_GET_FCNT(x)		(((x)>>17) & 0x1FF)

#define SDMMC_FIFO_SZ			32

/* Internal DMAC interrupt defines */

#define SDMMC_IDMAC_INT_AI		BIT(9)

#define SDMMC_IDMAC_INT_NI		BIT(8)

#define SDMMC_IDMAC_INT_CES		BIT(5)

#define SDMMC_IDMAC_INT_DU		BIT(4)

#define SDMMC_IDMAC_INT_FBE		BIT(2)

#define SDMMC_IDMAC_INT_RI		BIT(1)

#define SDMMC_IDMAC_INT_TI		BIT(0)

/* Internal DMAC bus mode bits */

#define SDMMC_IDMAC_ENABLE		BIT(7)

#define SDMMC_IDMAC_FB			BIT(1)

#define SDMMC_IDMAC_SWRESET		BIT(0)

/* Register access macros */

#define mci_readl(dev, reg)			\

	__raw_readl(dev->regs + SDMMC_##reg)

#define mci_writel(dev, reg, value)			\

	__raw_writel((value), dev->regs + SDMMC_##reg)

/* 16-bit FIFO access macros */

#define mci_readw(dev, reg)			\

	__raw_readw(dev->regs + SDMMC_##reg)

#define mci_writew(dev, reg, value)			\

	__raw_writew((value), dev->regs + SDMMC_##reg)

/* 64-bit FIFO access macros */

#ifdef readq

#define mci_readq(dev, reg)			\

	__raw_readq(dev->regs + SDMMC_##reg)

#define mci_writeq(dev, reg, value)			\

	__raw_writeq((value), dev->regs + SDMMC_##reg)

#else

/*

 * Dummy readq implementation for architectures that don't define it.

 *

 * We would assume that none of these architectures would configure

 * the IP block with a 64bit FIFO width, so this code will never be

 * executed on those machines. Defining these macros here keeps the

 * rest of the code free from ifdefs.

 */

#define mci_readq(dev, reg)			\

	(*(volatile u64 __force *)(dev->regs + SDMMC_##reg))

#define mci_writeq(dev, reg, value)			\

	(*(volatile u64 __force *)(dev->regs + SDMMC_##reg) = value)

#endif

#endif /* _DW_MMC_H_ */

/*

 * Synopsys DesignWare Multimedia Card Interface driver

 *  (Based on NXP driver for lpc 31xx)

 *

 * Copyright (C) 2009 NXP Semiconductors

 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 */

#ifndef _LINUX_MMC_DW_MMC_H_

#define _LINUX_MMC_DW_MMC_H_

#define MAX_MCI_SLOTS	2

enum dw_mci_state {

	STATE_IDLE = 0,

	STATE_SENDING_CMD,

	STATE_SENDING_DATA,

	STATE_DATA_BUSY,

	STATE_SENDING_STOP,

	STATE_DATA_ERROR,

};

enum {

	EVENT_CMD_COMPLETE = 0,

	EVENT_XFER_COMPLETE,

	EVENT_DATA_COMPLETE,

	EVENT_DATA_ERROR,

	EVENT_XFER_ERROR

};

struct mmc_data;

/**

 * struct dw_mci - MMC controller state shared between all slots

 * @lock: Spinlock protecting the queue and associated data.

 * @regs: Pointer to MMIO registers.

 * @sg: Scatterlist entry currently being processed by PIO code, if any.

 * @pio_offset: Offset into the current scatterlist entry.

 * @cur_slot: The slot which is currently using the controller.

 * @mrq: The request currently being processed on @cur_slot,

 *	or NULL if the controller is idle.

 * @cmd: The command currently being sent to the card, or NULL.

 * @data: The data currently being transferred, or NULL if no data

 *	transfer is in progress.

 * @use_dma: Whether DMA channel is initialized or not.

 * @sg_dma: Bus address of DMA buffer.

 * @sg_cpu: Virtual address of DMA buffer.

 * @dma_ops: Pointer to platform-specific DMA callbacks.

 * @cmd_status: Snapshot of SR taken upon completion of the current

 *	command. Only valid when EVENT_CMD_COMPLETE is pending.

 * @data_status: Snapshot of SR taken upon completion of the current

 *	data transfer. Only valid when EVENT_DATA_COMPLETE or

 *	EVENT_DATA_ERROR is pending.

 * @stop_cmdr: Value to be loaded into CMDR when the stop command is

 *	to be sent.

 * @dir_status: Direction of current transfer.

 * @tasklet: Tasklet running the request state machine.

 * @card_tasklet: Tasklet handling card detect.

 * @pending_events: Bitmask of events flagged by the interrupt handler

 *	to be processed by the tasklet.

 * @completed_events: Bitmask of events which the state machine has

 *	processed.

 * @state: Tasklet state.

 * @queue: List of slots waiting for access to the controller.

 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus

 *	rate and timeout calculations.

 * @current_speed: Configured rate of the controller.

 * @num_slots: Number of slots available.

 * @pdev: Platform device associated with the MMC controller.

 * @pdata: Platform data associated with the MMC controller.

 * @slot: Slots sharing this MMC controller.

 * @data_shift: log2 of FIFO item size.

 * @push_data: Pointer to FIFO push function.

 * @pull_data: Pointer to FIFO pull function.

 * @quirks: Set of quirks that apply to specific versions of the IP.

 *

 * Locking

 * =======

 *

 * @lock is a softirq-safe spinlock protecting @queue as well as

 * @cur_slot, @mrq and @state. These must always be updated

 * at the same time while holding @lock.

 *

 * The @mrq field of struct dw_mci_slot is also protected by @lock,

 * and must always be written at the same time as the slot is added to

 * @queue.

 *

 * @pending_events and @completed_events are accessed using atomic bit

 * operations, so they don't need any locking.

 *

 * None of the fields touched by the interrupt handler need any

 * locking. However, ordering is important: Before EVENT_DATA_ERROR or

 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related

 * interrupts must be disabled and @data_status updated with a

 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the

 * CMDRDY interupt must be disabled and @cmd_status updated with a

 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the

 * bytes_xfered field of @data must be written. This is ensured by

 * using barriers.

 */

struct dw_mci {

	spinlock_t		lock;

	void __iomem		*regs;

	struct scatterlist	*sg;

	unsigned int		pio_offset;

	struct dw_mci_slot	*cur_slot;

	struct mmc_request	*mrq;

	struct mmc_command	*cmd;

	struct mmc_data		*data;

	/* DMA interface members*/

	int			use_dma;

	dma_addr_t		sg_dma;

	void			*sg_cpu;

	struct dw_mci_dma_ops	*dma_ops;

#ifdef CONFIG_MMC_DW_IDMAC

	unsigned int		ring_size;

#else

	struct dw_mci_dma_data	*dma_data;

#endif

	u32			cmd_status;

	u32			data_status;

	u32			stop_cmdr;

	u32			dir_status;

	struct tasklet_struct	tasklet;

	struct tasklet_struct	card_tasklet;

	unsigned long		pending_events;

	unsigned long		completed_events;

	enum dw_mci_state	state;

	struct list_head	queue;

	u32			bus_hz;

	u32			current_speed;

	u32			num_slots;

	struct platform_device	*pdev;

	struct dw_mci_board	*pdata;

	struct dw_mci_slot	*slot[MAX_MCI_SLOTS];

	/* FIFO push and pull */

	int			data_shift;

	void (*push_data)(struct dw_mci *host, void *buf, int cnt);

	void (*pull_data)(struct dw_mci *host, void *buf, int cnt);

	/* Workaround flags */

	u32			quirks;

};

/* DMA ops for Internal/External DMAC interface */

struct dw_mci_dma_ops {

	/* DMA Ops */

	int (*init)(struct dw_mci *host);

	void (*start)(struct dw_mci *host, unsigned int sg_len);

	void (*complete)(struct dw_mci *host);

	void (*stop)(struct dw_mci *host);

	void (*cleanup)(struct dw_mci *host);

	void (*exit)(struct dw_mci *host);

};

/* IP Quirks/flags. */

/* No special quirks or flags to cater for */

#define DW_MCI_QUIRK_NONE		0

/* DTO fix for command transmission with IDMAC configured */

#define DW_MCI_QUIRK_IDMAC_DTO		1

/* delay needed between retries on some 2.11a implementations */

#define DW_MCI_QUIRK_RETRY_DELAY	2

/* High Speed Capable - Supports HS cards (upto 50MHz) */

#define DW_MCI_QUIRK_HIGHSPEED		4

struct dma_pdata;

struct block_settings {

	unsigned short	max_segs;	/* see blk_queue_max_segments */

	unsigned int	max_blk_size;	/* maximum size of one mmc block */

	unsigned int	max_blk_count;	/* maximum number of blocks in one req*/

	unsigned int	max_req_size;	/* maximum number of bytes in one req*/

	unsigned int	max_seg_size;	/* see blk_queue_max_segment_size */

};

/* Board platform data */

struct dw_mci_board {

	u32 num_slots;

	u32 quirks; /* Workaround / Quirk flags */

	unsigned int bus_hz; /* Bus speed */

	/* delay in mS before detecting cards after interrupt */

	u32 detect_delay_ms;

	int (*init)(u32 slot_id, irq_handler_t , void *);

	int (*get_ro)(u32 slot_id);

	int (*get_cd)(u32 slot_id);

	int (*get_ocr)(u32 slot_id);

	int (*get_bus_wd)(u32 slot_id);

	/*

	 * Enable power to selected slot and set voltage to desired level.

	 * Voltage levels are specified using MMC_VDD_xxx defines defined

	 * in linux/mmc/host.h file.

	 */

	void (*setpower)(u32 slot_id, u32 volt);

	void (*exit)(u32 slot_id);

	void (*select_slot)(u32 slot_id);

	struct dw_mci_dma_ops *dma_ops;

	struct dma_pdata *data;

	struct block_settings *blk_settings;

};

#endif /* _LINUX_MMC_DW_MMC_H_ */