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Commit f8facf22 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Correct default pinctrl state for sm8150 HSUART"

parents d1a279bf 980ad249

arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi

+21 −8
Original line number Diff line number Diff line
@@ -253,20 +253,33 @@ 
		};



		qupv3_se13_4uart_pins: qupv3_se13_4uart_pins {

			qupv3_se13_pins_default: qupv3_se13_pins_default {

			qupv3_se13_default_ctsrtsrx:

				qupv3_se13_default_ctsrtsrx {

				mux {

					pins = "gpio43", "gpio44", "gpio45",

								"gpio46";

					pins = "gpio43", "gpio44", "gpio46";

					function = "gpio";

				};



				config {

					pins = "gpio43", "gpio44", "gpio45",

								"gpio46";

					pins = "gpio43", "gpio44", "gpio46";

					drive-strength = <2>;

					bias-disable;

					bias-pull-down;

				};

			};



			qupv3_se13_default_tx: qupv3_se13_default_tx {

				mux {

					pins = "gpio45";

					function = "gpio";

				};



				config {

					pins = "gpio45";

					drive-strength = <2>;

					bias-pull-up;

				};

			};



			qupv3_se13_ctsrx: qupv3_se13_ctsrx {

				mux {

					pins = "gpio43", "gpio46";

arch/arm64/boot/dts/qcom/sm8150-qupv3.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -421,7 +421,8 @@ 
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;

		pinctrl-names = "default", "active", "sleep";

		pinctrl-0 = <&qupv3_se13_pins_default>;

		pinctrl-0 = <&qupv3_se13_default_ctsrtsrx>,

				<&qupv3_se13_default_tx>;

		pinctrl-1 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>,

						<&qupv3_se13_tx>;

		pinctrl-2 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>,