From ec350f9e80b8fb3a2ee2d5deab00de74c0bad172 Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 10 Jan 2022 18:00:50 -0800 Subject: [PATCH 01/42] fw-api: CL 16893507 - update fw common interface files add mlo_glb_chip_crash_info defs Change-Id: Ie09fb05019abd15ae3353de01177f5dc1ce1a4db CRs-Fixed: 2262693 --- fw/wlan_defs.h | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/fw/wlan_defs.h b/fw/wlan_defs.h index 351cd54cb0e4..f39cc7cc66df 100755 --- a/fw/wlan_defs.h +++ b/fw/wlan_defs.h @@ -1366,6 +1366,8 @@ typedef enum { MLO_SHMEM_TLV_STRUCT_MLO_GLB_LINK, MLO_SHMEM_TLV_STRUCT_MLO_GLB_LINK_INFO, MLO_SHMEM_TLV_STRUCT_MLO_GLB_H_SHMEM, + MLO_SHMEM_TLV_STRUCT_MLO_GLB_CHIP_CRASH_INFO, + MLO_SHMEM_TLV_STRUCT_MLO_GLB_PER_CHIP_CRASH_INFO, } MLO_SHMEM_TLV_TAG_ID; /** Helper macro for params GET/SET of mgmt_rx_reo_snapshot */ @@ -1542,6 +1544,52 @@ typedef struct { A_COMPILE_TIME_ASSERT(check_mlo_glb_link_info_8byte_size_quantum, (((sizeof(mlo_glb_link_info) % sizeof(A_UINT64) == 0x0)))); +typedef enum { + MLO_SHMEM_CRASH_PARTNER_CHIPS = 1, +} MLO_SHMEM_CHIP_CRASH_REASON; + +/* glb link info structures used for scratchpad memory (crash and recovery) */ +typedef struct { + /* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_PER_CHIP_CRASH_INFO */ + A_UINT32 tlv_header; + /** + * crash reason, takes value in enum MLO_SHMEM_CHIP_CRASH_REASON + */ + A_UINT32 crash_reason; +} mlo_glb_per_chip_crash_info; + +A_COMPILE_TIME_ASSERT(check_mlo_glb_per_chip_crash_info, + (((sizeof(mlo_glb_per_chip_crash_info) % sizeof(A_UINT64) == 0x0)))); + +/** Helper macro for params GET/SET of mlo_glb_chip_crash_info */ +#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_NO_OF_CHIPS_GET(chip_info) MLO_SHMEM_GET_BITS(chip_info, 0, 2) +#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_NO_OF_CHIPS_SET(chip_info, value) MLO_SHMEM_SET_BITS(chip_info, 0, 2, value) + +#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_VALID_CHIP_BMAP_GET(chip_info) MLO_SHMEM_GET_BITS(chip_info, 2, 3) +#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_VALID_CHIP_BMAP_SET(chip_info, value) MLO_SHMEM_SET_BITS(chip_info, 2, 3, value) + +typedef struct { + /* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_CHIP_CRASH_INFO */ + A_UINT32 tlv_header; + + /** + * chip_info + * + * [1:0]: no_of_chips + * [4:2]: valid_chip_bmap + * [31:6]: reserved + */ + A_UINT32 chip_info; + /* This TLV is followed by array of mlo_glb_per_chip_crash_info: + * mlo_glb_per_chip_crash_info will have mutiple instances equal to num of partner chips + * received by no_of_chips + * mlo_glb_per_chip_crash_info per_chip_crash_info[]; + */ +} mlo_glb_chip_crash_info; + +A_COMPILE_TIME_ASSERT(check_mlo_glb_chip_crash_info, + (((sizeof(mlo_glb_chip_crash_info) % sizeof(A_UINT64) == 0x0)))); + /** Helper macro for params GET/SET of mlo_glb_h_shmem */ #define MLO_SHMEM_GLB_H_SHMEM_PARAM_MINOR_VERSION_GET(major_minor_version) MLO_SHMEM_GET_BITS(major_minor_version, 0, 16) #define MLO_SHMEM_GLB_H_SHMEM_PARAM_MINOR_VERSION_SET(major_minor_version, value) MLO_SHMEM_SET_BITS(major_minor_version, 0, 16, value) @@ -1563,6 +1611,7 @@ typedef struct { /* This TLV is followed by TLVs * mlo_glb_rx_reo_snapshot_info reo_snapshot; * mlo_glb_link_info glb_info; + * mlo_glb_chip_crash_info crash_info; */ } mlo_glb_h_shmem; -- GitLab From 34ebfb43811faf591237dbcd4ac0ee85ec09793c Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 11 Jan 2022 18:00:48 -0800 Subject: [PATCH 02/42] fw-api: CL 16908979 - update fw common interface files Change-Id: Ifb5cd4914cbe05e10dc86ab025c045955063e86e WMI: add AFC SERVICE RESET_SUPPORT, SERV_RESP_FORMAT_IGNORE, CMD_RESET defs CRs-Fixed: 2262693 --- fw/wmi_services.h | 3 ++- fw/wmi_unified.h | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 33983e18ff93..720d58598a48 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -567,11 +567,12 @@ typedef enum { WMI_SERVICE_RTT_11AZ_MAC_PHY_SEC_SUPPORT = 315, /* FW support for 11AZ secure LTF + FTM */ WMI_SERVICE_SPECTRAL_SESSION_INFO_SUPPORT = 316, /* Information corresponding to each Spectral scan session will be sent by the FW before the reports corresponding to that session are sent */ WMI_SERVICE_PDEV_RATE_CONFIG_SUPPORT = 317, /* Support rate configurations per PDEV */ - MI_SERVICE_MLO_STA_NAN_NDI_SUPPORT = 318, /* FW support for NAN and NDP support with MLO STA */ + WMI_SERVICE_MLO_STA_NAN_NDI_SUPPORT = 318, /* FW support for NAN and NDP support with MLO STA */ WMI_SERVICE_PROBE_ALL_BW_SUPPORT = 319, /* FW support to probe on higher BW even if the probe fails on lower BW - IOT issue */ WMI_SERVICE_PKTLOG_DECODE_INFO_SUPPORT = 320, /* FW supports embedding Pktlog decode info in the Pktlog trace file level header */ WMI_SERVICE_PNO_SCAN_CONFIG_PER_CHANNEL = 321, /* Indicates that FW supports per channel configuration support in the PNO scan start command */ WMI_SERVICE_MULTIPLE_PEER_GROUP_CMD_SUPPORT = 322, /* FW support for multiple peer group command */ + WMI_SERVICE_AFC_RESET_SUPPORT = 323, /* Indicates FW supports AFC reset */ WMI_MAX_EXT2_SERVICE diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index c1fa01562018..8bb733eb85c8 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -30535,6 +30535,7 @@ typedef enum { */ AFC_SERV_RESP_FORMAT_JSON = 0, AFC_SERV_RESP_FORMAT_BINARY = 1, + AFC_SERV_RESP_FORMAT_IGNORE = 2, /* When cmd type is reset,server response is set to FORMAT_IGNORE */ } WMI_AFC_SERV_RESP_FORMAT_TYPE; typedef enum { @@ -30545,6 +30546,7 @@ typedef enum { * This type can be expanded in future as per requirements. */ WMI_AFC_CMD_SERV_RESP_READY = 1, + WMI_AFC_CMD_RESET = 2, /* Added cmd type to handle AFC reset */ } WMI_AFC_CMD_TYPE; /** Host indicating AFC info availability to FW */ -- GitLab From fe3898f3349df471abb0c5cfad892c4f6e612308 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 13 Jan 2022 12:01:11 -0800 Subject: [PATCH 03/42] fw-api: CL 16924619 - update fw common interface files Change-Id: I0bde23a994c9381ea2bf840e067ee8c781720fdc WMI: add EHT_SUPP_MCS_ enum constant defs CRs-Fixed: 2262693 --- fw/wmi_unified.h | 6 ++++++ fw/wmi_version.h | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 8bb733eb85c8..d67d8c5e2cc8 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -2573,6 +2573,12 @@ typedef struct _wmi_ppe_threshold { * 2 – index for == 160Mhz bw (only 3 bytes are valid and other is reserved) * 3 – index for == 320Mhz bw (only 3 bytes are valid and other is reserved) */ +enum { + WMI_EHT_SUPP_MCS_20MHZ_ONLY, + WMI_EHT_SUPP_MCS_LE_80MHZ, + WMI_EHT_SUPP_MCS_160MHZ, + WMI_EHT_SUPP_MCS_320MHZ, +}; #define WMI_MAX_EHT_SUPP_MCS_2G_SIZE 2 #define WMI_MAX_EHT_SUPP_MCS_5G_SIZE 4 diff --git a/fw/wmi_version.h b/fw/wmi_version.h index caab39cb752e..79cb81a4527c 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -36,7 +36,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1105 +#define __WMI_REVISION_ 1106 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From cda460e96e0537b5fdcaaaf443378baef28eed78 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 14 Jan 2022 06:00:54 -0800 Subject: [PATCH 04/42] fw-api: CL 16936729 - update fw common interface files Change-Id: Ieac70f22a69a414c08c096464e3b3775ad558486 WMI: add RTT_PASN pre-auth message defs CRs-Fixed: 2262693 --- fw/wmi.h | 1 - fw/wmi_tlv_defs.h | 44 +++++++++++++++++ fw/wmi_unified.h | 118 ++++++++++++++++++++++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 4 files changed, 163 insertions(+), 2 deletions(-) diff --git a/fw/wmi.h b/fw/wmi.h index d022f8573a23..30b01c6857ea 100644 --- a/fw/wmi.h +++ b/fw/wmi.h @@ -146,7 +146,6 @@ typedef enum { TX_USAGE = 0x02, /* default Tx Key - Static WEP only */ PMK_USAGE = 0x04, /* PMK cache */ PASN_USAGE = 0x08, /* is PASN based key */ - LTF_USAGE = 0x10, /* is LTF key seed */ } KEY_USAGE; /* * List of Events (target to host) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index adc7ef1e7a25..6f3ab3fcba78 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1231,6 +1231,14 @@ typedef enum { WMITLV_TAG_STRUC_wmi_pdev_sscan_per_detector_info, WMITLV_TAG_STRUC_wmi_ctrl_path_odd_addr_read_struct, WMITLV_TAG_STRUC_wmi_vdev_multiple_peer_group_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_set_ltf_key_seed_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_rtt_pasn_peer_create_req_event_fixed_param, + WMITLV_TAG_STRUC_wmi_rtt_pasn_peer_create_req_param, + WMITLV_TAG_STRUC_wmi_rtt_pasn_auth_status_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_rtt_pasn_auth_status_param, + WMITLV_TAG_STRUC_wmi_rtt_pasn_peer_delete_event_fixed_param, + WMITLV_TAG_STRUC_wmi_rtt_pasn_peer_delete_param, + WMITLV_TAG_STRUC_wmi_rtt_pasn_deauth_cmd_fixed_param, } WMITLV_TAG_ID; /* @@ -1716,6 +1724,9 @@ typedef enum { OP(WMI_SAWF_SVC_CLASS_DISABLE_CMDID) \ OP(WMI_SOC_TQM_RESET_ENABLE_DISABLE_CMDID) \ OP(WMI_VDEV_MULTIPLE_PEER_GROUP_CMDID) \ + OP(WMI_VDEV_SET_LTF_KEY_SEED_CMDID) \ + OP(WMI_RTT_PASN_AUTH_STATUS_CMD) \ + OP(WMI_RTT_PASN_DEAUTH_CMD) \ /* add new CMD_LIST elements above this line */ @@ -1995,6 +2006,8 @@ typedef enum { OP(WMI_RESMGR_CHAN_TIME_QUOTA_CHANGED_EVENTID) \ OP(WMI_PDEV_PKTLOG_DECODE_INFO_EVENTID) \ OP(WMI_SPECTRAL_CAPABILITIES_EVENTID) \ + OP(WMI_RTT_PASN_PEER_CREATE_REQ_EVENTID) \ + OP(WMI_RTT_PASN_PEER_DELETE_EVENTID) \ /* add new EVT_LIST elements above this line */ @@ -2454,6 +2467,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_FD_TMPL_CMDID); WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_INSTALL_KEY_CMDID); +/* VDEV set LTF key seed Cmd */ +#define WMITLV_TABLE_WMI_VDEV_SET_LTF_KEY_SEED_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_set_ltf_key_seed_cmd_fixed_param, wmi_vdev_set_ltf_key_seed_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)\ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, key_seed, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_LTF_KEY_SEED_CMDID); + /* VDEV WNM SLEEP MODE Cmd */ #define WMITLV_TABLE_WMI_VDEV_WNM_SLEEPMODE_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_VDEV_WNM_SLEEPMODE_CMD_fixed_param, WMI_VDEV_WNM_SLEEPMODE_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -4907,6 +4926,17 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SOC_TQM_RESET_ENABLE_DISABLE_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, wds_macaddr, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_MULTIPLE_PEER_GROUP_CMDID); +/* RTT 11az PASN authentication status cmd */ +#define WMITLV_TABLE_WMI_RTT_PASN_AUTH_STATUS_CMD(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rtt_pasn_auth_status_cmd_fixed_param, wmi_rtt_pasn_auth_status_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rtt_pasn_auth_status_param, pasn_auth_status_param, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_RTT_PASN_AUTH_STATUS_CMD); + +/* RTT 11az PASN deauthentication cmd */ +#define WMITLV_TABLE_WMI_RTT_PASN_DEAUTH_CMD(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rtt_pasn_deauth_cmd_fixed_param, wmi_rtt_pasn_deauth_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_RTT_PASN_DEAUTH_CMD); + /************************** TLV definitions of WMI events *******************************/ @@ -6633,6 +6663,20 @@ WMITLV_CREATE_PARAM_STRUC(WMI_RESMGR_CHAN_TIME_QUOTA_CHANGED_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_pktlog_decode_info_evt_fixed_param, wmi_pdev_pktlog_decode_info_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_PKTLOG_DECODE_INFO_EVENTID); +/* RTT 11az PASN peer create request event */ +#define WMITLV_TABLE_WMI_RTT_PASN_PEER_CREATE_REQ_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rtt_pasn_peer_create_req_event_fixed_param, \ + wmi_rtt_pasn_peer_create_req_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rtt_pasn_peer_create_req_param, rtt_pasn_peer_param, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_RTT_PASN_PEER_CREATE_REQ_EVENTID); + +/* RTT 11az PASN peer delete event */ +#define WMITLV_TABLE_WMI_RTT_PASN_PEER_DELETE_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rtt_pasn_peer_delete_event_fixed_param, \ + wmi_rtt_pasn_peer_delete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rtt_pasn_peer_delete_param, rtt_pasn_peer_param, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_RTT_PASN_PEER_DELETE_EVENTID); + #ifdef __cplusplus } diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index d67d8c5e2cc8..ecdd09f1ce49 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -581,6 +581,8 @@ typedef enum { WMI_VDEV_UPDATE_MAC_ADDR_CMDID, /* WMI cmd to perform operation on multiple peer based on subcmd type */ WMI_VDEV_MULTIPLE_PEER_GROUP_CMDID, + /** Set LTF key seed which will be further used to derive LTF keys */ + WMI_VDEV_SET_LTF_KEY_SEED_CMDID, /* peer specific commands */ @@ -944,6 +946,10 @@ typedef enum { WMI_RTT_MEASREQ_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_RTT), /** request to report a tsf measurement */ WMI_RTT_TSF_CMDID, + /** RTT 11az PASN authentication status */ + WMI_RTT_PASN_AUTH_STATUS_CMD, + /** RTT 11az PASN deauthentication cmd */ + WMI_RTT_PASN_DEAUTH_CMD, /** spectral scan command */ /** configure spectral scan */ @@ -1844,6 +1850,10 @@ typedef enum { WMI_TSF_MEASUREMENT_REPORT_EVENTID, /** RTT error report */ WMI_RTT_ERROR_REPORT_EVENTID, + /** RTT 11az PASN peer create request */ + WMI_RTT_PASN_PEER_CREATE_REQ_EVENTID, + /** RTT 11az PASN peer delete event */ + WMI_RTT_PASN_PEER_DELETE_EVENTID, /*STATS specific events*/ /** txrx stats event requested by host */ @@ -12494,6 +12504,22 @@ typedef struct { */ } wmi_vdev_install_key_cmd_fixed_param; +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_set_ltf_key_seed_cmd_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** MAC address used for deriving */ + wmi_mac_addr peer_macaddr; + /** authentication mode */ + A_UINT32 rsn_authmode; + /** LTF key seed length */ + A_UINT32 key_seed_len; +/* + * Following this struct are this TLV. + * A_UINT8 key_seed[key_seed_len]; <-- actual LTF key seed; + */ +} wmi_vdev_set_ltf_key_seed_cmd_fixed_param; + /** Preamble types to be used with VDEV fixed rate configuration */ typedef enum { WMI_RATE_PREAMBLE_OFDM, @@ -14951,6 +14977,7 @@ enum wmi_peer_type { WMI_PEER_TYPE_OCB = 3, /* Peer is a OCB Peer */ WMI_PEER_TYPE_NAN_DATA = 4, /* Peer is NAN DATA */ WMI_PEER_TYPE_TRANS_BSS = 5, /* For creating BSS peer when connecting with non-transmit AP */ + WMI_PEER_TYPE_PASN = 6, /* Peer is used for Pre-Association Security Negotiation */ WMI_PEER_TYPE_HOST_MAX = 127, /* Host <-> Target Peer type is assigned up to 127 */ /* Reserved from 128 - 255 for target internal use.*/ WMI_PEER_TYPE_ROAMOFFLOAD_TEMP = 128, /* Temporarily created during offload roam */ @@ -18044,6 +18071,7 @@ typedef enum event_type_e { WOW_TWT_EVENT, /* 32 + 10 */ WOW_DCS_INTERFERENCE_DET, /* 32 + 11 */ WOW_ROAM_STATS_EVENT, /* 32 + 12 */ + WOW_RTT_11AZ_EVENT, /* 32 + 13 */ } WOW_WAKE_EVENT_TYPE; typedef enum wake_reason_e { @@ -18121,6 +18149,7 @@ typedef enum wake_reason_e { WOW_REASON_DCS_INT_DET, WOW_REASON_ROAM_STATS, WOW_REASON_MDNS_WAKEUP, + WOW_REASON_RTT_11AZ, /* add new WOW_REASON_ defs before this line */ WOW_REASON_MAX, @@ -30496,6 +30525,9 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) WMI_RETURN_STRING(WMI_VDEV_UPDATE_MAC_ADDR_CMDID); WMI_RETURN_STRING(WMI_SOC_TQM_RESET_ENABLE_DISABLE_CMDID); WMI_RETURN_STRING(WMI_VDEV_MULTIPLE_PEER_GROUP_CMDID); + WMI_RETURN_STRING(WMI_VDEV_SET_LTF_KEY_SEED_CMDID); + WMI_RETURN_STRING(WMI_RTT_PASN_AUTH_STATUS_CMD); + WMI_RETURN_STRING(WMI_RTT_PASN_DEAUTH_CMD); } return (A_UINT8 *) "Invalid WMI cmd"; @@ -37283,6 +37315,92 @@ typedef struct { */ } wmi_vdev_multiple_peer_group_cmd_fixed_param; +#define WMI_RTT_PASN_PEER_CREATE_SECURITY_MODE_GET(flag) WMI_GET_BITS(flag, 0, 2) +#define WMI_RTT_PASN_PEER_CREATE_SECURITY_MODE_SET(flag,val) WMI_SET_BITS(flag, 0, 2, val) +#define WMI_RTT_PASN_PEER_CREATE_FORCE_SELF_MAC_USE_GET(flag) WMI_GET_BITS(flag, 2, 1) +#define WMI_RTT_PASN_PEER_CREATE_FORCE_SELF_MAC_USE_SET(flag,val) WMI_SET_BITS(flag, 2, 1, val) + +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rtt_pasn_peer_create_req_event_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; +/** + * The following TLV will follow this fixed_param TLV: + * + * wmi_rtt_pasn_peer_create_req_param rtt_pasn_peer_param[] + */ +} wmi_rtt_pasn_peer_create_req_event_fixed_param; + +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rtt_pasn_peer_create_req_param */ + + wmi_mac_addr self_mac_addr; /* self MAC address (can be vdev address or random mac address) */ + wmi_mac_addr dest_mac_addr; /* MAC address of the peer */ + + A_UINT32 control_flag; /* some control information here */ + /********************************************************************************* + * Bits 1:0: Security mode, check wmi_rtt_security_mode for detail. + * Host driver to request supplicant to derive and install PASN keys if security mode is set. + * Bit 2: Force_self_mac_addr_use, To indicate supplicant/hostapd to use this self mac addr to (re)generate PASN keys, + * and flush old cache( if it exists) for dest_mac_addr with old self_mac_addr. + * Bits 31:3: Reserved + */ +} wmi_rtt_pasn_peer_create_req_param; + + +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rtt_pasn_auth_status_cmd_fixed_param */ +/** + * The following TLV will follow this fixed_param TLV: + * + * wmi_rtt_pasn_auth_status_param pasn_auth_status_param[] + */ +} wmi_rtt_pasn_auth_status_cmd_fixed_param; + +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rtt_pasn_auth_status_param */ + /* MAC address of the peer */ + wmi_mac_addr peer_mac_addr; + /* Return status. 0 for success, non-zero otherwise */ + A_UINT32 status; +} wmi_rtt_pasn_auth_status_param; + + +#define WMI_RTT_PASN_PEER_DELETE_DELETED_BIT_GET(flag) WMI_GET_BITS(flag, 0, 1) +#define WMI_RTT_PASN_PEER_DELETE_DELETED_BIT_SET(flag,val) WMI_SET_BITS(flag, 0, 1, val) +#define WMI_RTT_PASN_PEER_DELETE_FLUSH_KEYS_GET(flag) WMI_GET_BITS(flag, 1, 1) +#define WMI_RTT_PASN_PEER_DELETE_FLUSH_KEYS_SET(flag,val) WMI_SET_BITS(flag, 1, 1, val) + +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rtt_pasn_peer_delete_event_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; +/** + * The following TLV will follow this fixed_param TLV: + * + * wmi_rtt_pasn_peer_delete_param rtt_pasn_peer_param[] + */ +} wmi_rtt_pasn_peer_delete_event_fixed_param; + +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rtt_pasn_peer_delete_param */ + /* MAC address of the peer */ + wmi_mac_addr peer_mac_addr; + /* some control information here */ + A_UINT32 control_flag; +/********************************************************************************** + * Bit 0: peer_deleted (This is set to 1 if peer has already been deleted by the target) + * Bit 1: flush keys (This is set to 1 if target wants the cached PASN keys to be flushed) + * Bits 31:2: reserved + */ +} wmi_rtt_pasn_peer_delete_param; + +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rtt_pasn_deauth_cmd_fixed_param */ + /* MAC address of the peer */ + wmi_mac_addr peer_mac_addr; +} wmi_rtt_pasn_deauth_cmd_fixed_param; + /* ADD NEW DEFS HERE */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 79cb81a4527c..916f8e0092f2 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -36,7 +36,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1106 +#define __WMI_REVISION_ 1107 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 0cd367650dbbb34cc5c7cf88fe8f8f3467b636ce Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 17 Jan 2022 18:01:08 -0800 Subject: [PATCH 05/42] fw-api: CL 16957374 - update fw common interface files add WMI_ROAM_INVOKE_FLAG_SELECT_CANDIDATE_CONSIDER_SCORE def Change-Id: Ieacf42ff59624e02048e345a9768697c94a95087 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 6 +++++- fw/wmi_version.h | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index ecdd09f1ce49..687f7a71747e 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -17407,7 +17407,11 @@ typedef struct{ #define WMI_ROAM_INVOKE_FLAG_NO_NULL_FRAME_TO_AP 2 /* start extra full scan if no candidate found in previous scan */ #define WMI_ROAM_INVOKE_FLAG_FULL_SCAN_IF_NO_CANDIDATE 3 -/* from bit 4 to bit 31 are reserved */ +/* when bit is set: candidate selection algo will based on fw score algo. + * when bit is not set: candidate selection algo will ignore score. + */ +#define WMI_ROAM_INVOKE_FLAG_SELECT_CANDIDATE_CONSIDER_SCORE 4 +/* from bit 5 to bit 31 are reserved */ #define WMI_SET_ROAM_INVOKE_ADD_CH_TO_CACHE(flag) do { \ (flag) |= (1 << WMI_SET_ROAM_INVOKE_ADD_CH_TO_CACHE); \ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 916f8e0092f2..971527e7ee70 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -36,7 +36,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1107 +#define __WMI_REVISION_ 1108 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 74b5a5dd0d1babe82b3114655638cd1eeff3b478 Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 19 Jan 2022 12:00:53 -0800 Subject: [PATCH 06/42] fw-api: CL 16974263 - update fw common interface files Change-Id: Ib26193e7fe564bb84617c9a033a5b31c7993dfb0 WMI: add PDEV_PARAM_EN_UPDATE_SCRAM_SEED def CRs-Fixed: 2262693 --- fw/wmi_unified.h | 15 +++++++++++++-- fw/wmi_version.h | 2 +- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 687f7a71747e..575c93fff50d 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -8047,6 +8047,10 @@ typedef enum { /* Param to enable/disable probing on all BW */ WMI_PDEV_PARAM_EN_PROBE_ALL_BW, + + /* Param to enable/disable updating scrambler seed feature */ + WMI_PDEV_PARAM_EN_UPDATE_SCRAM_SEED, + } WMI_PDEV_PARAM; #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1) @@ -17407,8 +17411,15 @@ typedef struct{ #define WMI_ROAM_INVOKE_FLAG_NO_NULL_FRAME_TO_AP 2 /* start extra full scan if no candidate found in previous scan */ #define WMI_ROAM_INVOKE_FLAG_FULL_SCAN_IF_NO_CANDIDATE 3 -/* when bit is set: candidate selection algo will based on fw score algo. - * when bit is not set: candidate selection algo will ignore score. +/* when bit is set: + * Candidate selection algo will based on fw score algo. + * Which means configurations like wmi_roam_score_delta_param, + * wmi_configure_roam_trigger_parameters is also configurable for + * host_invoke roam, as well as consider current BSS score as + * score algo input. + * when bit is not set: + * Candidate selection algo will ignore score and above configurations + * and ignore current BSS score. */ #define WMI_ROAM_INVOKE_FLAG_SELECT_CANDIDATE_CONSIDER_SCORE 4 /* from bit 5 to bit 31 are reserved */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 971527e7ee70..9180ed5034ac 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -36,7 +36,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1108 +#define __WMI_REVISION_ 1109 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 3345991c8d38e23ff5a699a3591007f7b9ac146f Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 20 Jan 2022 18:00:55 -0800 Subject: [PATCH 07/42] fw-api: CL 16991780 - update fw common interface files add WMI_SERVICE_FP_PHY_ERR_FILTER_SUPPORT def Change-Id: I5d9255455b24a0bfb6ea1fee10400170dbc64304 CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + fw/wmi_version.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 720d58598a48..92d4f2fe9f60 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -573,6 +573,7 @@ typedef enum { WMI_SERVICE_PNO_SCAN_CONFIG_PER_CHANNEL = 321, /* Indicates that FW supports per channel configuration support in the PNO scan start command */ WMI_SERVICE_MULTIPLE_PEER_GROUP_CMD_SUPPORT = 322, /* FW support for multiple peer group command */ WMI_SERVICE_AFC_RESET_SUPPORT = 323, /* Indicates FW supports AFC reset */ + WMI_SERVICE_FP_PHY_ERR_FILTER_SUPPORT = 324, /* FW supports monitor ring configurations for filtering in PHY error packets */ WMI_MAX_EXT2_SERVICE diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 9180ed5034ac..c2589fd43247 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -36,7 +36,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1109 +#define __WMI_REVISION_ 1110 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From c3efac9930a12533c3e47235f28beffd1b260918 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 20 Jan 2022 18:01:26 -0800 Subject: [PATCH 08/42] fw-api: CL 17004158 - update fw common interface files Update copyright header in htt_stats.h file. Update copyright header in htt_stats.h file based on new guideance from LOST team that current ownership should be for Qualcomm Innovation Center , not Linux Foundation.Similar changes will be applied in other wlanfw_cmn .h files in a follow-up change. Change-Id: I4441b5225bedfab969a97974c7f2f8296b0c13f6 CRs-Fixed: 2262693 --- fw/htt_stats.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/fw/htt_stats.h b/fw/htt_stats.h index b05e5a380532..cd31a0e4468a 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2017-2022 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the -- GitLab From f9a852dd022149ada1f36a92ed2bb8ebf96ad791 Mon Sep 17 00:00:00 2001 From: spuligil Date: Sat, 22 Jan 2022 18:02:12 -0800 Subject: [PATCH 09/42] fw-api: CL 17023988 - update fw common interface files HTT stats: auto-generate documentation Convert certain comments in htt.h and htt_stats.h from /* to doxygen-style /**.Add scripts and doxygen configuration files for using doxygen to generate documentation of HTT stats definitions. Change-Id: If11ba7104918568726d6cf10f66745622cbcc6ae CRs-Fixed: 2262693 --- fw/htt.h | 7 +- fw/htt_stats.h | 2501 ++++++++++++++++++++++++++++-------------------- 2 files changed, 1477 insertions(+), 1031 deletions(-) diff --git a/fw/htt.h b/fw/htt.h index f86fac9c5ff0..2eff2c74616d 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -273,7 +273,7 @@ */ #define HTT_T2H_MSG_TYPE_RC_UPDATE_IND DEPRECATED_HTT_T2H_MSG_TYPE_RC_UPDATE_IND -/* +/** * htt_dbg_stats_type - * bit positions for each stats type within a stats type bitmask * The bitmask contains 24 bits. @@ -579,6 +579,7 @@ typedef struct { }; } htt_tlv_hdr_t; +/** HTT stats TLV tag values */ typedef enum { HTT_STATS_TX_PDEV_CMN_TAG = 0, /* htt_tx_pdev_stats_cmn_tlv */ HTT_STATS_TX_PDEV_UNDERRUN_TAG = 1, /* htt_tx_pdev_stats_urrn_tlv_v */ @@ -727,7 +728,9 @@ typedef enum { HTT_STATS_MAX_TAG, -} htt_tlv_tag_t; +} htt_stats_tlv_tag_t; +/* retain deprecated enum name as an alias for the current enum name */ +typedef htt_stats_tlv_tag_t htt_tlv_tag_t; #define HTT_STATS_TLV_TAG_M 0x00000fff #define HTT_STATS_TLV_TAG_S 0 diff --git a/fw/htt_stats.h b/fw/htt_stats.h index cd31a0e4468a..cc069582153c 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -29,7 +29,7 @@ #include #include /* HTT stats TLV struct def and tag defs */ -/* +/** * htt_dbg_ext_stats_type - * The base structure for each of the stats_type is only for reference * Host should use this information to know the type of TLVs to expect @@ -38,7 +38,7 @@ * Max supported stats :- 256. */ enum htt_dbg_ext_stats_type { - /* HTT_DBG_EXT_STATS_RESET + /** HTT_DBG_EXT_STATS_RESET * PARAM: * - config_param0 : start_offset (stats type) * - config_param1 : stats bmask from start offset @@ -49,7 +49,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_RESET = 0, - /* HTT_DBG_EXT_STATS_PDEV_TX + /** HTT_DBG_EXT_STATS_PDEV_TX * PARAMS: * - No Params * RESP MSG: @@ -57,7 +57,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_PDEV_TX = 1, - /* HTT_DBG_EXT_STATS_PDEV_RX + /** HTT_DBG_EXT_STATS_PDEV_RX * PARAMS: * - No Params * RESP MSG: @@ -65,7 +65,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_PDEV_RX = 2, - /* HTT_DBG_EXT_STATS_PDEV_TX_HWQ + /** HTT_DBG_EXT_STATS_PDEV_TX_HWQ * PARAMS: * - config_param0: [Bit31: Bit0] HWQ mask * RESP MSG: @@ -73,7 +73,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_PDEV_TX_HWQ = 3, - /* HTT_DBG_EXT_STATS_PDEV_TX_SCHED + /** HTT_DBG_EXT_STATS_PDEV_TX_SCHED * PARAMS: * - config_param0: [Bit31: Bit0] TXQ mask * RESP MSG: @@ -81,7 +81,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_PDEV_TX_SCHED = 4, - /* HTT_DBG_EXT_STATS_PDEV_ERROR + /** HTT_DBG_EXT_STATS_PDEV_ERROR * PARAMS: * - No Params * RESP MSG: @@ -89,7 +89,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_PDEV_ERROR = 5, - /* HTT_DBG_EXT_STATS_PDEV_TQM + /** HTT_DBG_EXT_STATS_PDEV_TQM * PARAMS: * - No Params * RESP MSG: @@ -97,7 +97,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_PDEV_TQM = 6, - /* HTT_DBG_EXT_STATS_TQM_CMDQ + /** HTT_DBG_EXT_STATS_TQM_CMDQ * PARAMS: * - config_param0: * [Bit15: Bit0 ] cmdq id :if 0xFFFF print all cmdq's @@ -107,7 +107,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_TQM_CMDQ = 7, - /* HTT_DBG_EXT_STATS_TX_DE_INFO + /** HTT_DBG_EXT_STATS_TX_DE_INFO * PARAMS: * - No Params * RESP MSG: @@ -115,7 +115,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_TX_DE_INFO = 8, - /* HTT_DBG_EXT_STATS_PDEV_TX_RATE + /** HTT_DBG_EXT_STATS_PDEV_TX_RATE * PARAMS: * - No Params * RESP MSG: @@ -123,7 +123,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_PDEV_TX_RATE = 9, - /* HTT_DBG_EXT_STATS_PDEV_RX_RATE + /** HTT_DBG_EXT_STATS_PDEV_RX_RATE * PARAMS: * - No Params * RESP MSG: @@ -131,7 +131,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_PDEV_RX_RATE = 10, - /* HTT_DBG_EXT_STATS_PEER_INFO + /** HTT_DBG_EXT_STATS_PEER_INFO * PARAMS: * - config_param0: * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request @@ -163,7 +163,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_PEER_INFO = 11, - /* HTT_DBG_EXT_STATS_TX_SELFGEN_INFO + /** HTT_DBG_EXT_STATS_TX_SELFGEN_INFO * PARAMS: * - No Params * RESP MSG: @@ -171,7 +171,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_TX_SELFGEN_INFO = 12, - /* HTT_DBG_EXT_STATS_TX_MU_HWQ + /** HTT_DBG_EXT_STATS_TX_MU_HWQ * PARAMS: * - config_param0: [Bit31: Bit0] HWQ mask * RESP MSG: @@ -179,7 +179,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_TX_MU_HWQ = 13, - /* HTT_DBG_EXT_STATS_RING_IF_INFO + /** HTT_DBG_EXT_STATS_RING_IF_INFO * PARAMS: * - config_param0: * [Bit15: Bit0 ] ring id :if 0xFFFF print all rings @@ -189,7 +189,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_RING_IF_INFO = 14, - /* HTT_DBG_EXT_STATS_SRNG_INFO + /** HTT_DBG_EXT_STATS_SRNG_INFO * PARAMS: * - config_param0: * [Bit15: Bit0 ] ring id :if 0xFFFF print all rings @@ -200,7 +200,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_SRNG_INFO = 15, - /* HTT_DBG_EXT_STATS_SFM_INFO + /** HTT_DBG_EXT_STATS_SFM_INFO * PARAMS: * - No Params * RESP MSG: @@ -208,7 +208,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_SFM_INFO = 16, - /* HTT_DBG_EXT_STATS_PDEV_TX_MU + /** HTT_DBG_EXT_STATS_PDEV_TX_MU * PARAMS: * - No Params * RESP MSG: @@ -216,7 +216,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_PDEV_TX_MU = 17, - /* HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST + /** HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST * PARAMS: * - config_param0: * [Bit7 : Bit0] vdev_id:8 @@ -227,7 +227,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST = 18, - /* HTT_DBG_EXT_STATS_PDEV_CCA_STATS + /** HTT_DBG_EXT_STATS_PDEV_CCA_STATS * PARAMS: * - config_param0: * [Bit0] - Clear bit0 to read 1sec,100ms & cumulative CCA stats. @@ -239,7 +239,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_PDEV_CCA_STATS = 19, - /* HTT_DBG_EXT_STATS_TWT_SESSIONS + /** HTT_DBG_EXT_STATS_TWT_SESSIONS * PARAMS: * - config_param0: * No params @@ -248,7 +248,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_TWT_SESSIONS = 20, - /* HTT_DBG_EXT_STATS_REO_CNTS + /** HTT_DBG_EXT_STATS_REO_CNTS * PARAMS: * - config_param0: * No params @@ -257,7 +257,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_REO_RESOURCE_STATS = 21, - /* HTT_DBG_EXT_STATS_TX_SOUNDING_INFO + /** HTT_DBG_EXT_STATS_TX_SOUNDING_INFO * PARAMS: * - config_param0: * [Bit0] vdev_id_set:1 @@ -272,7 +272,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_TX_SOUNDING_INFO = 22, - /* HTT_DBG_EXT_STATS_PDEV_OBSS_PD_STATS + /** HTT_DBG_EXT_STATS_PDEV_OBSS_PD_STATS * PARAMS: * - config_param0: * No params @@ -281,7 +281,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_PDEV_OBSS_PD_STATS = 23, - /* HTT_DBG_EXT_STATS_RING_BACKPRESSURE_STATS + /** HTT_DBG_EXT_STATS_RING_BACKPRESSURE_STATS * PARAMS: * - config_param0: * No params @@ -290,7 +290,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_RING_BACKPRESSURE_STATS = 24, - /* HTT_DBG_EXT_STATS_LATENCY_PROF_STATS + /** HTT_DBG_EXT_STATS_LATENCY_PROF_STATS * PARAMS: * * RESP MSG: @@ -298,7 +298,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_LATENCY_PROF_STATS = 25, - /* HTT_DBG_EXT_STATS_PDEV_UL_TRIGGER + /** HTT_DBG_EXT_STATS_PDEV_UL_TRIGGER * PARAMS: * - No Params * RESP MSG: @@ -306,7 +306,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_PDEV_UL_TRIG_STATS = 26, - /* HTT_DBG_EXT_STATS_PDEV_UL_MUMIMO_TRIG_STATS = 27 + /** HTT_DBG_EXT_STATS_PDEV_UL_MUMIMO_TRIG_STATS = 27 * PARAMS: * - No Params * RESP MSG: @@ -314,7 +314,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_PDEV_UL_MUMIMO_TRIG_STATS = 27, - /* HTT_DBG_EXT_STATS_FSE_RX + /** HTT_DBG_EXT_STATS_FSE_RX * PARAMS: * - No Params * RESP MSG: @@ -322,7 +322,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_FSE_RX = 28, - /* HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS + /** HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS * PARAMS: * - config_param0: [Bit0] : [1] for mac_addr based request * - config_param1: [Bit31 : Bit0] mac_addr31to0 @@ -332,7 +332,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS = 29, - /* HTT_DBG_EXT_STATS_PDEV_RX_RATE_EXT + /** HTT_DBG_EXT_STATS_PDEV_RX_RATE_EXT * PARAMS: * - No Params * RESP MSG: @@ -340,7 +340,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_PDEV_RX_RATE_EXT = 30, - /* HTT_DBG_EXT_STATS_PDEV_TX_RATE_TXBF + /** HTT_DBG_EXT_STATS_PDEV_TX_RATE_TXBF * PARAMS: * - No Params * RESP MSG: @@ -352,7 +352,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_TXBF_OFDMA = 32, - /* HTT_DBG_EXT_STA_11AX_UL_STATS + /** HTT_DBG_EXT_STA_11AX_UL_STATS * PARAMS: * - No Params * RESP MSG: @@ -360,7 +360,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STA_11AX_UL_STATS = 33, - /* HTT_DBG_EXT_VDEV_RTT_RESP_STATS + /** HTT_DBG_EXT_VDEV_RTT_RESP_STATS * PARAMS: * - config_param0: * [Bit7 : Bit0] vdev_id:8 @@ -370,7 +370,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_VDEV_RTT_RESP_STATS = 34, - /* HTT_DBG_EXT_PKTLOG_AND_HTT_RING_STATS + /** HTT_DBG_EXT_PKTLOG_AND_HTT_RING_STATS * PARAMS: * - No Params * RESP MSG: @@ -378,7 +378,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_PKTLOG_AND_HTT_RING_STATS = 35, - /* HTT_DBG_EXT_STATS_DLPAGER_STATS + /** HTT_DBG_EXT_STATS_DLPAGER_STATS * PARAMS: * * RESP MSG: @@ -386,7 +386,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_DLPAGER_STATS = 36, - /* HTT_DBG_EXT_PHY_COUNTERS_AND_PHY_STATS + /** HTT_DBG_EXT_PHY_COUNTERS_AND_PHY_STATS * PARAMS: * - No Params * RESP MSG: @@ -394,7 +394,7 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_PHY_COUNTERS_AND_PHY_STATS = 37, - /* HTT_DBG_EXT_VDEVS_TXRX_STATS + /** HTT_DBG_EXT_VDEVS_TXRX_STATS * PARAMS: * - No Params * RESP MSG: @@ -404,7 +404,7 @@ enum htt_dbg_ext_stats_type { HTT_DBG_EXT_VDEV_RTT_INITIATOR_STATS = 39, - /* HTT_DBG_EXT_PDEV_PER_STATS + /** HTT_DBG_EXT_PDEV_PER_STATS * PARAMS: * - No Params * RESP MSG: @@ -414,7 +414,7 @@ enum htt_dbg_ext_stats_type { HTT_DBG_EXT_AST_ENTRIES = 41, - /* HTT_DBG_EXT_RX_RING_STATS + /** HTT_DBG_EXT_RX_RING_STATS * PARAMS: * - No Params * RESP MSG: @@ -586,167 +586,175 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* BIT [ 7 : 0] :- mac_id + /** + * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ A_UINT32 mac_id__word; - /* Num queued to HW */ + /** Num PPDUs queued to HW */ A_UINT32 hw_queued; - /* Num PPDU reaped from HW */ + /** Num PPDUs reaped from HW */ A_UINT32 hw_reaped; - /* Num underruns */ + /** Num underruns */ A_UINT32 underrun; - /* Num HW Paused counter. */ + /** Num HW Paused counter */ A_UINT32 hw_paused; - /* Num HW flush counter. */ + /** Num HW flush counter */ A_UINT32 hw_flush; - /* Num HW filtered counter. */ + /** Num HW filtered counter */ A_UINT32 hw_filt; - /* Num PPDUs cleaned up in TX abort */ + /** Num PPDUs cleaned up in TX abort */ A_UINT32 tx_abort; - /* Num MPDUs requed by SW */ + /** Num MPDUs requeued by SW */ A_UINT32 mpdu_requed; - /* excessive retries */ + /** excessive retries */ A_UINT32 tx_xretry; - /* Last used data hw rate code */ + /** Last used data hw rate code */ A_UINT32 data_rc; - /* frames dropped due to excessive sw retries */ + /** frames dropped due to excessive SW retries */ A_UINT32 mpdu_dropped_xretry; - /* illegal rate phy errors */ + /** illegal rate phy errors */ A_UINT32 illgl_rate_phy_err; - /* wal pdev continous xretry */ + /** wal pdev continuous xretry */ A_UINT32 cont_xretry; - /* wal pdev tx timeout */ + /** wal pdev tx timeout */ A_UINT32 tx_timeout; - /* wal pdev resets */ + /** wal pdev resets */ A_UINT32 pdev_resets; - /* PhY/BB underrun */ + /** PHY/BB underrun */ A_UINT32 phy_underrun; - /* MPDU is more than txop limit */ + /** MPDU is more than txop limit */ A_UINT32 txop_ovf; - /* Number of Sequences posted */ + /** Number of Sequences posted */ A_UINT32 seq_posted; - /* Number of Sequences failed queueing */ + /** Number of Sequences failed queueing */ A_UINT32 seq_failed_queueing; - /* Number of Sequences completed */ + /** Number of Sequences completed */ A_UINT32 seq_completed; - /* Number of Sequences restarted */ + /** Number of Sequences restarted */ A_UINT32 seq_restarted; - /* Number of MU Sequences posted */ + /** Number of MU Sequences posted */ A_UINT32 mu_seq_posted; - /* Number of time HW ring is paused between seq switch within ISR */ + /** Number of time HW ring is paused between seq switch within ISR */ A_UINT32 seq_switch_hw_paused; - /* Number of times seq continuation in DSR */ + /** Number of times seq continuation in DSR */ A_UINT32 next_seq_posted_dsr; - /* Number of times seq continuation in ISR */ + /** Number of times seq continuation in ISR */ A_UINT32 seq_posted_isr; - /* Number of seq_ctrl cached. */ + /** Number of seq_ctrl cached. */ A_UINT32 seq_ctrl_cached; - /* Number of MPDUs successfully transmitted */ + /** Number of MPDUs successfully transmitted */ A_UINT32 mpdu_count_tqm; - /* Number of MSDUs successfully transmitted */ + /** Number of MSDUs successfully transmitted */ A_UINT32 msdu_count_tqm; - /* Number of MPDUs dropped */ + /** Number of MPDUs dropped */ A_UINT32 mpdu_removed_tqm; - /* Number of MSDUs dropped */ + /** Number of MSDUs dropped */ A_UINT32 msdu_removed_tqm; - /* Num MPDUs flushed by SW, HWPAUSED, SW TXABORT (Reset,channel change) */ + /** Num MPDUs flushed by SW, HWPAUSED, SW TXABORT (Reset,channel change) */ A_UINT32 mpdus_sw_flush; - /* Num MPDUs filtered by HW, all filter condition (TTL expired) */ + /** Num MPDUs filtered by HW, all filter condition (TTL expired) */ A_UINT32 mpdus_hw_filter; - /* Num MPDUs truncated by PDG (TXOP, TBTT, PPDU_duration based on rate, dyn_bw) */ + /** + * Num MPDUs truncated by PDG + * (TXOP, TBTT, PPDU_duration based on rate, dyn_bw) + */ A_UINT32 mpdus_truncated; - /* Num MPDUs that was tried but didn't receive ACK or BA */ + /** Num MPDUs that was tried but didn't receive ACK or BA */ A_UINT32 mpdus_ack_failed; - /* Num MPDUs that was dropped due to expiry (MSDU TTL). */ + /** Num MPDUs that was dropped due to expiry (MSDU TTL) */ A_UINT32 mpdus_expired; - /* Num MPDUs that was retried within seq_ctrl (MGMT/LEGACY) */ + /** Num MPDUs that was retried within seq_ctrl (MGMT/LEGACY) */ A_UINT32 mpdus_seq_hw_retry; - /* Num of TQM acked cmds processed */ + /** Num of TQM acked cmds processed */ A_UINT32 ack_tlv_proc; - /* coex_abort_mpdu_cnt valid. */ + /** coex_abort_mpdu_cnt valid */ A_UINT32 coex_abort_mpdu_cnt_valid; - /* coex_abort_mpdu_cnt from TX FES stats. */ + /** coex_abort_mpdu_cnt from TX FES stats */ A_UINT32 coex_abort_mpdu_cnt; - /* Number of total PPDUs(DATA, MGMT, excludes selfgen) tried over the air (OTA) */ + /** + * Number of total PPDUs + * (DATA, MGMT, excludes selfgen) tried over the air (OTA) + */ A_UINT32 num_total_ppdus_tried_ota; - /* Number of data PPDUs tried over the air (OTA) */ + /** Number of data PPDUs tried over the air (OTA) */ A_UINT32 num_data_ppdus_tried_ota; - /* Num Local control/mgmt frames (MSDUs) queued */ + /** Num Local control/mgmt frames (MSDUs) queued */ A_UINT32 local_ctrl_mgmt_enqued; - /* local_ctrl_mgmt_freed: + /** * Num Local control/mgmt frames (MSDUs) done * It includes all local ctrl/mgmt completions * (acked, no ack, flush, TTL, etc) */ A_UINT32 local_ctrl_mgmt_freed; - /* Num Local data frames (MSDUs) queued */ + /** Num Local data frames (MSDUs) queued */ A_UINT32 local_data_enqued; - /* local_data_freed: + /** * Num Local data frames (MSDUs) done * It includes all local data completions * (acked, no ack, flush, TTL, etc) */ A_UINT32 local_data_freed; - /* Num MPDUs tried by SW */ + /** Num MPDUs tried by SW */ A_UINT32 mpdu_tried; - /* Num of waiting seq posted in isr completion handler */ + /** Num of waiting seq posted in ISR completion handler */ A_UINT32 isr_wait_seq_posted; A_UINT32 tx_active_dur_us_low; A_UINT32 tx_active_dur_us_high; - /* Number of MPDUs dropped after max retries */ + /** Number of MPDUs dropped after max retries */ A_UINT32 remove_mpdus_max_retries; - /* Num HTT cookies dispatched */ + /** Num HTT cookies dispatched */ A_UINT32 comp_delivered; - /* successful ppdu transmissions */ + /** successful ppdu transmissions */ A_UINT32 ppdu_ok; - /* Scheduler self triggers */ + /** Scheduler self triggers */ A_UINT32 self_triggers; - /* FES duration of last tx data PPDU in us (sch_eval_end - ppdu_start) */ + /** FES duration of last tx data PPDU in us (sch_eval_end - ppdu_start) */ A_UINT32 tx_time_dur_data; - /* Num of times sequence terminated due to ppdu duration < burst limit */ + /** Num of times sequence terminated due to ppdu duration < burst limit */ A_UINT32 seq_qdepth_repost_stop; - /* Num of times MU sequence terminated due to MSDUs reaching threshold */ + /** Num of times MU sequence terminated due to MSDUs reaching threshold */ A_UINT32 mu_seq_min_msdu_repost_stop; - /* Num of times SU sequence terminated due to MSDUs reaching threshold */ + /** Num of times SU sequence terminated due to MSDUs reaching threshold */ A_UINT32 seq_min_msdu_repost_stop; - /* Num of times sequence terminated due to no TXOP available */ + /** Num of times sequence terminated due to no TXOP available */ A_UINT32 seq_txop_repost_stop; - /* Num of times the next sequence got cancelled */ + /** Num of times the next sequence got cancelled */ A_UINT32 next_seq_cancel; - /* Num of times fes offset was misaligned */ + /** Num of times fes offset was misaligned */ A_UINT32 fes_offsets_err_cnt; - /* Num of times peer denylisted for MU-MIMO transmission */ + /** Num of times peer denylisted for MU-MIMO transmission */ A_UINT32 num_mu_peer_blacklisted; - /* Num of times mu_ofdma seq posted */ + /** Num of times mu_ofdma seq posted */ A_UINT32 mu_ofdma_seq_posted; - /* Num of times UL MU MIMO seq posted */ + /** Num of times UL MU MIMO seq posted */ A_UINT32 ul_mumimo_seq_posted; - /* Num of times UL OFDMA seq posted */ + /** Num of times UL OFDMA seq posted */ A_UINT32 ul_ofdma_seq_posted; - /* Num of times Thermal module suspended scheduler */ + /** Num of times Thermal module suspended scheduler */ A_UINT32 thermal_suspend_cnt; - /* Num of times DFS module suspended scheduler */ + /** Num of times DFS module suspended scheduler */ A_UINT32 dfs_suspend_cnt; - /* Num of times TX abort module suspended scheduler */ + /** Num of times TX abort module suspended scheduler */ A_UINT32 tx_abort_suspend_cnt; - /* tgt_specific_opaque_txq_suspend_info: - * This field is a target-specifc bit mask of suspended PPDU tx queues. + /** + * This field is a target-specific bit mask of suspended PPDU tx queues. * Since the bit mask definition is different for different targets, * this field is not meant for general use, but rather for debugging use. */ A_UINT32 tgt_specific_opaque_txq_suspend_info; - /* Last SCHEDULER suspend reason + /** + * Last SCHEDULER suspend reason * 1 -> Thermal Module * 2 -> DFS Module * 3 -> Tx Abort Module */ A_UINT32 last_suspend_reason; - /* Num of dynamic mimo ps dlmumimo sequences posted */ + /** Num of dynamic mimo ps dlmumimo sequences posted */ A_UINT32 num_dyn_mimo_ps_dlmumimo_sequences; - /* Num of times su bf sequences are denylisted */ + /** Num of times su bf sequences are denylisted */ A_UINT32 num_su_txbf_denylisted; } htt_tx_pdev_stats_cmn_tlv; @@ -995,7 +1003,8 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* BIT [ 7 : 0] :- mac_id + /** + * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ union { @@ -1006,7 +1015,7 @@ typedef struct { A_UINT32 mac_id__word; }; - /* + /** * hw_wars is a variable-length array, with each element counting * the number of occurrences of the corresponding type of HW WAR. * That is, hw_wars[0] indicates how many times HW WAR 0 occurred, @@ -1084,8 +1093,10 @@ typedef struct _htt_msdu_flow_stats_tlv { A_UINT32 last_remove_timestamp; A_UINT32 total_processed_msdu_count; A_UINT32 cur_msdu_count_in_flowq; - A_UINT32 sw_peer_id; /* This will help to find which peer_id is stuck state */ - /* BIT [15 : 0] :- tx_flow_number + /** This will help to find which peer_id is stuck state */ + A_UINT32 sw_peer_id; + /** + * BIT [15 : 0] :- tx_flow_number * BIT [19 : 16] :- tid_num * BIT [20 : 20] :- drop_rule * BIT [31 : 21] :- reserved @@ -1094,7 +1105,8 @@ typedef struct _htt_msdu_flow_stats_tlv { A_UINT32 last_cycle_enqueue_count; A_UINT32 last_cycle_dequeue_count; A_UINT32 last_cycle_drop_count; - /* BIT [15 : 0] :- current_drop_th + /** + * BIT [15 : 0] :- current_drop_th * BIT [31 : 16] :- reserved */ A_UINT32 current_drop_th; @@ -1158,23 +1170,25 @@ typedef struct _htt_msdu_flow_stats_tlv { typedef struct _htt_tx_tid_stats_tlv { htt_tlv_hdr_t tlv_hdr; - /* Stored as little endian */ + /** Stored as little endian */ A_UINT8 tid_name[MAX_HTT_TID_NAME]; - /* BIT [15 : 0] :- sw_peer_id + /** + * BIT [15 : 0] :- sw_peer_id * BIT [31 : 16] :- tid_num */ A_UINT32 sw_peer_id__tid_num; - /* BIT [ 7 : 0] :- num_sched_pending + /** + * BIT [ 7 : 0] :- num_sched_pending * BIT [15 : 8] :- num_ppdu_in_hwq * BIT [31 : 16] :- reserved */ A_UINT32 num_sched_pending__num_ppdu_in_hwq; A_UINT32 tid_flags; - /* per tid # of hw_queued ppdu.*/ + /** per tid # of hw_queued ppdu */ A_UINT32 hw_queued; - /* number of per tid successful PPDU. */ + /** number of per tid successful PPDU */ A_UINT32 hw_reaped; - /* per tid Num MPDUs filtered by HW */ + /** per tid Num MPDUs filtered by HW */ A_UINT32 mpdus_hw_filter; A_UINT32 qdepth_bytes; @@ -1183,30 +1197,31 @@ typedef struct _htt_tx_tid_stats_tlv { A_UINT32 last_scheduled_tsmp; A_UINT32 pause_module_id; A_UINT32 block_module_id; - /* tid tx airtime in sec */ + /** tid tx airtime in sec */ A_UINT32 tid_tx_airtime; } htt_tx_tid_stats_tlv; /* Tidq stats */ typedef struct _htt_tx_tid_stats_v1_tlv { htt_tlv_hdr_t tlv_hdr; - /* Stored as little endian */ + /** Stored as little endian */ A_UINT8 tid_name[MAX_HTT_TID_NAME]; - /* BIT [15 : 0] :- sw_peer_id + /** + * BIT [15 : 0] :- sw_peer_id * BIT [31 : 16] :- tid_num */ A_UINT32 sw_peer_id__tid_num; - /* BIT [ 7 : 0] :- num_sched_pending + /** + * BIT [ 7 : 0] :- num_sched_pending * BIT [15 : 8] :- num_ppdu_in_hwq * BIT [31 : 16] :- reserved */ A_UINT32 num_sched_pending__num_ppdu_in_hwq; A_UINT32 tid_flags; - /* Max qdepth in bytes reached by this tid*/ + /** Max qdepth in bytes reached by this tid */ A_UINT32 max_qdepth_bytes; - /* number of msdus qdepth reached max */ + /** number of msdus qdepth reached max */ A_UINT32 max_qdepth_n_msdus; - /* Made reserved this field */ A_UINT32 rsvd; A_UINT32 qdepth_bytes; @@ -1215,10 +1230,11 @@ typedef struct _htt_tx_tid_stats_v1_tlv { A_UINT32 last_scheduled_tsmp; A_UINT32 pause_module_id; A_UINT32 block_module_id; - /* tid tx airtime in sec */ + /** tid tx airtime in sec */ A_UINT32 tid_tx_airtime; A_UINT32 allow_n_flags; - /* BIT [15 : 0] :- sendn_frms_allowed + /** + * BIT [15 : 0] :- sendn_frms_allowed * BIT [31 : 16] :- reserved */ A_UINT32 sendn_frms_allowed; @@ -1252,78 +1268,83 @@ typedef struct _htt_tx_tid_stats_v1_tlv { typedef struct _htt_rx_tid_stats_tlv { htt_tlv_hdr_t tlv_hdr; - /* BIT [15 : 0] : sw_peer_id + /** + * BIT [15 : 0] : sw_peer_id * BIT [31 : 16] : tid_num */ A_UINT32 sw_peer_id__tid_num; - /* Stored as little endian */ + /** Stored as little endian */ A_UINT8 tid_name[MAX_HTT_TID_NAME]; - /* dup_in_reorder not collected per tid for now, - as there is no wal_peer back ptr in data rx peer. */ + /** + * dup_in_reorder not collected per tid for now, + * as there is no wal_peer back ptr in data rx peer. + */ A_UINT32 dup_in_reorder; A_UINT32 dup_past_outside_window; A_UINT32 dup_past_within_window; - /* Number of per tid MSDUs with flag of decrypt_err */ + /** Number of per tid MSDUs with flag of decrypt_err */ A_UINT32 rxdesc_err_decrypt; - /* tid rx airtime in sec */ + /** tid rx airtime in sec */ A_UINT32 tid_rx_airtime; } htt_rx_tid_stats_tlv; #define HTT_MAX_COUNTER_NAME 8 typedef struct { htt_tlv_hdr_t tlv_hdr; - /* Stored as little endian */ + /** Stored as little endian */ A_UINT8 counter_name[HTT_MAX_COUNTER_NAME]; A_UINT32 count; } htt_counter_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - /* Number of rx ppdu. */ + /** Number of rx PPDU */ A_UINT32 ppdu_cnt; - /* Number of rx mpdu. */ + /** Number of rx MPDU */ A_UINT32 mpdu_cnt; - /* Number of rx msdu */ + /** Number of rx MSDU */ A_UINT32 msdu_cnt; - /* Pause bitmap */ + /** pause bitmap */ A_UINT32 pause_bitmap; - /* Block bitmap */ + /** block bitmap */ A_UINT32 block_bitmap; - /* Current timestamp */ + /** current timestamp */ A_UINT32 current_timestamp; - /* Peer cumulative tx airtime in sec */ + /** Peer cumulative tx airtime in sec */ A_UINT32 peer_tx_airtime; - /* Peer cumulative rx airtime in sec */ + /** Peer cumulative rx airtime in sec */ A_UINT32 peer_rx_airtime; - /* Peer current rssi in dBm */ + /** Peer current rssi in dBm */ A_INT32 rssi; - /* Total enqueued, dequeued and dropped msdu's for peer */ + /** Total enqueued, dequeued and dropped MSDU's for peer */ A_UINT32 peer_enqueued_count_low; A_UINT32 peer_enqueued_count_high; A_UINT32 peer_dequeued_count_low; A_UINT32 peer_dequeued_count_high; A_UINT32 peer_dropped_count_low; A_UINT32 peer_dropped_count_high; - /* Total ppdu transmitted bytes for peer: includes MAC header overhead */ + /** Total ppdu transmitted bytes for peer: includes MAC header overhead */ A_UINT32 ppdu_transmitted_bytes_low; A_UINT32 ppdu_transmitted_bytes_high; A_UINT32 peer_ttl_removed_count; - /* inactive_time + /** + * inactive_time * Running duration of the time since last tx/rx activity by this peer, * units = seconds. * If the peer is currently active, this inactive_time will be 0x0. */ A_UINT32 inactive_time; - /* Number of MPDUs dropped after max retries */ + /** Number of MPDUs dropped after max retries */ A_UINT32 remove_mpdus_max_retries; } htt_peer_stats_cmn_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - /* This enum type of HTT_PEER_TYPE */ + /** This enum type of HTT_PEER_TYPE */ A_UINT32 peer_type; A_UINT32 sw_peer_id; - /* BIT [7 : 0] :- vdev_id + /** + * BIT [7 : 0] :- vdev_id * BIT [15 : 8] :- pdev_id * BIT [31 : 16] :- ast_indx */ @@ -1394,28 +1415,37 @@ typedef enum { typedef struct _htt_tx_peer_rate_stats_tlv { htt_tlv_hdr_t tlv_hdr; - /* Number of tx ldpc packets */ + /** Number of tx LDPC packets */ A_UINT32 tx_ldpc; - /* Number of tx rts packets */ + /** Number of tx RTS packets */ A_UINT32 rts_cnt; - /* RSSI value of last ack packet (units = dB above noise floor) */ + /** RSSI value of last ack packet (units = dB above noise floor) */ A_UINT32 ack_rssi; A_UINT32 tx_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; A_UINT32 tx_su_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; A_UINT32 tx_mu_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; - A_UINT32 tx_nss[HTT_TX_PEER_STATS_NUM_SPATIAL_STREAMS]; /* element 0,1, ...7 -> NSS 1,2, ...8 */ - A_UINT32 tx_bw[HTT_TX_PEER_STATS_NUM_BW_COUNTERS]; /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ + /** + * element 0,1, ...7 -> NSS 1,2, ...8 + */ + A_UINT32 tx_nss[HTT_TX_PEER_STATS_NUM_SPATIAL_STREAMS]; + /** + * element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz + */ + A_UINT32 tx_bw[HTT_TX_PEER_STATS_NUM_BW_COUNTERS]; A_UINT32 tx_stbc[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; A_UINT32 tx_pream[HTT_TX_PEER_STATS_NUM_PREAMBLE_TYPES]; - /* Counters to track number of tx packets in each GI (400us, 800us, 1600us & 3200us) in each mcs (0-11) */ + /** + * Counters to track number of tx packets in each GI + * (400us, 800us, 1600us & 3200us) in each mcs (0-11) + */ A_UINT32 tx_gi[HTT_TX_PEER_STATS_NUM_GI_COUNTERS][HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; - /* Counters to track packets in dcm mcs (MCS 0, 1, 3, 4) */ + /** Counters to track packets in dcm mcs (MCS 0, 1, 3, 4) */ A_UINT32 tx_dcm[HTT_TX_PEER_STATS_NUM_DCM_COUNTERS]; - /* Stats for MCS 12/13 */ + /** Stats for MCS 12/13 */ A_UINT32 tx_mcs_ext[HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; A_UINT32 tx_su_mcs_ext[HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; A_UINT32 tx_mu_mcs_ext[HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; @@ -1437,29 +1467,39 @@ typedef struct _htt_rx_peer_rate_stats_tlv { htt_tlv_hdr_t tlv_hdr; A_UINT32 nsts; - /* Number of rx ldpc packets */ + /** Number of rx LDPC packets */ A_UINT32 rx_ldpc; - /* Number of rx rts packets */ + /** Number of rx RTS packets */ A_UINT32 rts_cnt; - A_UINT32 rssi_mgmt; /* units = dB above noise floor */ - A_UINT32 rssi_data; /* units = dB above noise floor */ - A_UINT32 rssi_comb; /* units = dB above noise floor */ + /** units = dB above noise floor */ + A_UINT32 rssi_mgmt; + /** units = dB above noise floor */ + A_UINT32 rssi_data; + /** units = dB above noise floor */ + A_UINT32 rssi_comb; A_UINT32 rx_mcs[HTT_RX_PEER_STATS_NUM_MCS_COUNTERS]; - A_UINT32 rx_nss[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS]; /* element 0,1, ...7 -> NSS 1,2, ...8 */ + /** + * element 0,1, ...7 -> NSS 1,2, ...8 + */ + A_UINT32 rx_nss[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS]; A_UINT32 rx_dcm[HTT_RX_PEER_STATS_NUM_DCM_COUNTERS]; A_UINT32 rx_stbc[HTT_RX_PEER_STATS_NUM_MCS_COUNTERS]; - A_UINT32 rx_bw[HTT_RX_PEER_STATS_NUM_BW_COUNTERS]; /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ + /** + * element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz + */ + A_UINT32 rx_bw[HTT_RX_PEER_STATS_NUM_BW_COUNTERS]; A_UINT32 rx_pream[HTT_RX_PEER_STATS_NUM_PREAMBLE_TYPES]; - A_UINT8 rssi_chain[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PEER_STATS_NUM_BW_COUNTERS]; /* units = dB above noise floor */ + /** units = dB above noise floor */ + A_UINT8 rssi_chain[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PEER_STATS_NUM_BW_COUNTERS]; - /* Counters to track number of rx packets in each GI in each mcs (0-11) */ + /** Counters to track number of rx packets in each GI in each mcs (0-11) */ A_UINT32 rx_gi[HTT_RX_PEER_STATS_NUM_GI_COUNTERS][HTT_RX_PEER_STATS_NUM_MCS_COUNTERS]; - A_UINT32 rx_ulofdma_non_data_ppdu; /* ppdu level */ - A_UINT32 rx_ulofdma_data_ppdu; /* ppdu level */ - A_UINT32 rx_ulofdma_mpdu_ok; /* mpdu level */ - A_UINT32 rx_ulofdma_mpdu_fail; /* mpdu level */ + A_UINT32 rx_ulofdma_non_data_ppdu; /** PPDU level */ + A_UINT32 rx_ulofdma_data_ppdu; /** PPDU level */ + A_UINT32 rx_ulofdma_mpdu_ok; /** MPDU level */ + A_UINT32 rx_ulofdma_mpdu_fail; /** MPDU level */ A_INT8 rx_ul_fd_rssi[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS]; /* dBm unit */ /* per_chain_rssi_pkt_type: * This field shows what type of rx frame the per-chain RSSI was computed @@ -1472,14 +1512,19 @@ typedef struct _htt_rx_peer_rate_stats_tlv { A_UINT32 per_chain_rssi_pkt_type; A_INT8 rx_per_chain_rssi_in_dbm[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PEER_STATS_NUM_BW_COUNTERS]; - A_UINT32 rx_ulmumimo_non_data_ppdu; /* ppdu level */ - A_UINT32 rx_ulmumimo_data_ppdu; /* ppdu level */ - A_UINT32 rx_ulmumimo_mpdu_ok; /* mpdu level */ - A_UINT32 rx_ulmumimo_mpdu_fail; /* mpdu level */ + /** PPDU level */ + A_UINT32 rx_ulmumimo_non_data_ppdu; + /** PPDU level */ + A_UINT32 rx_ulmumimo_data_ppdu; + /** MPDU level */ + A_UINT32 rx_ulmumimo_mpdu_ok; + /** mpdu level */ + A_UINT32 rx_ulmumimo_mpdu_fail; - A_UINT8 rssi_chain_ext[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PEER_STATS_NUM_BW_EXT_COUNTERS]; /* units = dB above noise floor */ + /** units = dB above noise floor */ + A_UINT8 rssi_chain_ext[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PEER_STATS_NUM_BW_EXT_COUNTERS]; - /* Stats for MCS 12/13 */ + /** Stats for MCS 12/13 */ A_UINT32 rx_mcs_ext[HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; A_UINT32 rx_stbc_ext[HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; A_UINT32 rx_gi_ext[HTT_RX_PEER_STATS_NUM_GI_COUNTERS][HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; @@ -1509,14 +1554,14 @@ typedef enum { typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 peer_id; - /* Num of DL schedules for peer */ + /** Num of DL schedules for peer */ A_UINT32 num_sched_dl; - /* Num od UL schedules for peer */ + /** Num od UL schedules for peer */ A_UINT32 num_sched_ul; - /* Peer TX time */ + /** Peer TX time */ A_UINT32 peer_tx_active_dur_us_low; A_UINT32 peer_tx_active_dur_us_high; - /* Peer RX time */ + /** Peer RX time */ A_UINT32 peer_rx_active_dur_us_low; A_UINT32 peer_rx_active_dur_us_high; A_UINT32 peer_curr_rate_kbps; @@ -1630,20 +1675,30 @@ typedef struct { /* MU MIMO stats per hwQ */ typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 mu_mimo_sch_posted; /* number of MU MIMO schedules posted to HW */ - A_UINT32 mu_mimo_sch_failed; /* number of MU MIMO schedules failed to post */ - A_UINT32 mu_mimo_ppdu_posted; /* number of MU MIMO PPDUs posted to HW */ + /** number of MU MIMO schedules posted to HW */ + A_UINT32 mu_mimo_sch_posted; + /** number of MU MIMO schedules failed to post */ + A_UINT32 mu_mimo_sch_failed; + /** number of MU MIMO PPDUs posted to HW */ + A_UINT32 mu_mimo_ppdu_posted; } htt_tx_hwq_mu_mimo_sch_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 mu_mimo_mpdus_queued_usr; /* 11AC DL MU MIMO number of mpdus queued to HW, per user */ - A_UINT32 mu_mimo_mpdus_tried_usr; /* 11AC DL MU MIMO number of mpdus tried over the air, per user */ - A_UINT32 mu_mimo_mpdus_failed_usr; /* 11AC DL MU MIMO number of mpdus failed acknowledgement, per user */ - A_UINT32 mu_mimo_mpdus_requeued_usr; /* 11AC DL MU MIMO number of mpdus re-queued to HW, per user */ - A_UINT32 mu_mimo_err_no_ba_usr; /* 11AC DL MU MIMO BA not receieved, per user */ - A_UINT32 mu_mimo_mpdu_underrun_usr; /* 11AC DL MU MIMO mpdu underrun encountered, per user */ - A_UINT32 mu_mimo_ampdu_underrun_usr; /* 11AC DL MU MIMO ampdu underrun encountered, per user */ + /** 11AC DL MU MIMO number of mpdus queued to HW, per user */ + A_UINT32 mu_mimo_mpdus_queued_usr; + /** 11AC DL MU MIMO number of mpdus tried over the air, per user */ + A_UINT32 mu_mimo_mpdus_tried_usr; + /** 11AC DL MU MIMO number of mpdus failed acknowledgement, per user */ + A_UINT32 mu_mimo_mpdus_failed_usr; + /** 11AC DL MU MIMO number of mpdus re-queued to HW, per user */ + A_UINT32 mu_mimo_mpdus_requeued_usr; + /** 11AC DL MU MIMO BA not receieved, per user */ + A_UINT32 mu_mimo_err_no_ba_usr; + /** 11AC DL MU MIMO mpdu underrun encountered, per user */ + A_UINT32 mu_mimo_mpdu_underrun_usr; + /** 11AC DL MU MIMO ampdu underrun encountered, per user */ + A_UINT32 mu_mimo_ampdu_underrun_usr; } htt_tx_hwq_mu_mimo_mpdu_stats_tlv; #define HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID_M 0x000000ff @@ -1675,7 +1730,8 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* BIT [ 7 : 0] :- mac_id + /** + * BIT [ 7 : 0] :- mac_id * BIT [15 : 8] :- hwq_id * BIT [31 : 16] :- reserved */ @@ -1689,8 +1745,10 @@ typedef struct { typedef struct { struct _hwq_mu_mimo_stats { htt_tx_hwq_mu_mimo_cmn_stats_tlv cmn_tlv; - htt_tx_hwq_mu_mimo_sch_stats_tlv mu_mimo_sch_stats_tlv[1]; /* WAL_TX_STATS_MAX_GROUP_SIZE */ - htt_tx_hwq_mu_mimo_mpdu_stats_tlv mu_mimo_mpdu_stats_tlv[1]; /* WAL_TX_STATS_TX_MAX_NUM_USERS */ + /** WAL_TX_STATS_MAX_GROUP_SIZE */ + htt_tx_hwq_mu_mimo_sch_stats_tlv mu_mimo_sch_stats_tlv[1]; + /** WAL_TX_STATS_TX_MAX_NUM_USERS */ + htt_tx_hwq_mu_mimo_mpdu_stats_tlv mu_mimo_mpdu_stats_tlv[1]; } hwq[1]; } htt_tx_hwq_mu_mimo_stats_t; @@ -1724,38 +1782,65 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* BIT [ 7 : 0] :- mac_id + /** + * BIT [ 7 : 0] :- mac_id * BIT [15 : 8] :- hwq_id * BIT [31 : 16] :- reserved */ A_UINT32 mac_id__hwq_id__word; - /* PPDU level stats */ - A_UINT32 xretry; /* Number of times ack is failed for the PPDU scheduled on this txQ */ - A_UINT32 underrun_cnt; /* Number of times sched cmd status reported mpdu underrun */ - A_UINT32 flush_cnt; /* Number of times sched cmd is flushed */ - A_UINT32 filt_cnt; /* Number of times sched cmd is filtered */ - A_UINT32 null_mpdu_bmap; /* Number of times HWSCH uploaded null mpdu bitmap */ - A_UINT32 user_ack_failure; /* Number of time user ack or ba tlv is not seen on FES ring where it is expected to be */ - A_UINT32 ack_tlv_proc; /* Number of times TQM processed ack tlv received from HWSCH */ - A_UINT32 sched_id_proc; /* Cache latest processed scheduler ID received from ack ba tlv */ - A_UINT32 null_mpdu_tx_count; /* Number of times TxPCU reported mpdus transmitted for a user is zero */ - A_UINT32 mpdu_bmap_not_recvd; /* Number of times SW did not see any mpdu info bitmap tlv on FES status ring */ - - /* Selfgen stats per hwQ */ - A_UINT32 num_bar; /* Number of SU/MU BAR frames posted to hwQ */ - A_UINT32 rts; /* Number of RTS frames posted to hwQ */ - A_UINT32 cts2self; /* Number of cts2self frames posted to hwQ */ - A_UINT32 qos_null; /* Number of qos null frames posted to hwQ */ - - /* MPDU level stats */ - A_UINT32 mpdu_tried_cnt; /* mpdus tried Tx by HWSCH/TQM */ - A_UINT32 mpdu_queued_cnt; /* mpdus queued to HWSCH */ - A_UINT32 mpdu_ack_fail_cnt; /* mpdus tried but ack was not received */ - A_UINT32 mpdu_filt_cnt; /* This will include sched cmd flush and time based discard */ - A_UINT32 false_mpdu_ack_count; /* Number of MPDUs for which ACK was sucessful but no Tx happened */ - - A_UINT32 txq_timeout; /* Number of times txq timeout happened */ + /*--- PPDU level stats */ + /** Number of times ack is failed for the PPDU scheduled on this txQ */ + A_UINT32 xretry; + /** Number of times sched cmd status reported mpdu underrun */ + A_UINT32 underrun_cnt; + /** Number of times sched cmd is flushed */ + A_UINT32 flush_cnt; + /** Number of times sched cmd is filtered */ + A_UINT32 filt_cnt; + /** Number of times HWSCH uploaded null mpdu bitmap */ + A_UINT32 null_mpdu_bmap; + /** + * Number of times user ack or BA TLV is not seen on FES ring + * where it is expected to be + */ + A_UINT32 user_ack_failure; + /** Number of times TQM processed ack TLV received from HWSCH */ + A_UINT32 ack_tlv_proc; + /** Cache latest processed scheduler ID received from ack BA TLV */ + A_UINT32 sched_id_proc; + /** Number of times TxPCU reported MPDUs transmitted for a user is zero */ + A_UINT32 null_mpdu_tx_count; + /** + * Number of times SW did not see any MPDU info bitmap TLV + * on FES status ring + */ + A_UINT32 mpdu_bmap_not_recvd; + + /*--- Selfgen stats per hwQ */ + /** Number of SU/MU BAR frames posted to hwQ */ + A_UINT32 num_bar; + /** Number of RTS frames posted to hwQ */ + A_UINT32 rts; + /** Number of cts2self frames posted to hwQ */ + A_UINT32 cts2self; + /** Number of qos null frames posted to hwQ */ + A_UINT32 qos_null; + + /*--- MPDU level stats */ + /** mpdus tried Tx by HWSCH/TQM */ + A_UINT32 mpdu_tried_cnt; + /** mpdus queued to HWSCH */ + A_UINT32 mpdu_queued_cnt; + /** mpdus tried but ack was not received */ + A_UINT32 mpdu_ack_fail_cnt; + /** This will include sched cmd flush and time based discard */ + A_UINT32 mpdu_filt_cnt; + /** Number of MPDUs for which ACK was sucessful but no Tx happened */ + A_UINT32 false_mpdu_ack_count; + + /** Number of times txq timeout happened */ + A_UINT32 txq_timeout; } htt_tx_hwq_stats_cmn_tlv; #define HTT_TX_HWQ_DIFS_LATENCY_STATS_TLV_SZ(_num_elems) (sizeof(A_UINT32) + /* hist_intvl */ \ @@ -1764,7 +1849,7 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 hist_intvl; - /* histogram of ppdu post to hwsch - > cmd status received */ + /** histogram of ppdu post to hwsch - > cmd status received */ A_UINT32 difs_latency_hist[1]; /* HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS */ } htt_tx_hwq_difs_latency_stats_tlv_v; @@ -1773,7 +1858,7 @@ typedef struct { /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - /* Histogram of sched cmd result */ + /** Histogram of sched cmd result */ A_UINT32 cmd_result[1]; /* HTT_TX_HWQ_MAX_CMD_RESULT_STATS */ } htt_tx_hwq_cmd_result_stats_tlv_v; @@ -1782,7 +1867,7 @@ typedef struct { /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - /* Histogram of various pause conitions */ + /** Histogram of various pause conitions */ A_UINT32 cmd_stall_status[1]; /* HTT_TX_HWQ_MAX_CMD_STALL_STATS */ } htt_tx_hwq_cmd_stall_stats_tlv_v; @@ -1791,7 +1876,7 @@ typedef struct { /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - /* Histogram of number of user fes result */ + /** Histogram of number of user fes result */ A_UINT32 fes_result[1]; /* HTT_TX_HWQ_MAX_FES_RESULT_STATS */ } htt_tx_hwq_fes_result_stats_tlv_v; @@ -1812,7 +1897,7 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 hist_bin_size; - /* Histogram of number of mpdus on tried mpdu */ + /** Histogram of number of mpdus on tried mpdu */ A_UINT32 tried_mpdu_cnt_hist[1]; /* HTT_TX_HWQ_TRIED_MPDU_CNT_HIST */ } htt_tx_hwq_tried_mpdu_cnt_hist_tlv_v; @@ -1830,7 +1915,7 @@ typedef struct { * */ typedef struct { htt_tlv_hdr_t tlv_hdr; - /* Histogram of txop used cnt */ + /** Histogram of txop used cnt */ A_UINT32 txop_used_cnt_hist[1]; /* HTT_TX_HWQ_TXOP_USED_CNT_HIST */ } htt_tx_hwq_txop_used_cnt_hist_tlv_v; @@ -1947,54 +2032,89 @@ typedef enum { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* BIT [ 7 : 0] :- mac_id + /* + * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ A_UINT32 mac_id__word; - A_UINT32 su_bar; /* BAR sent out for SU transmission */ - A_UINT32 rts; /* SW generated RTS frame sent */ - A_UINT32 cts2self; /* SW generated CTS-to-self frame sent */ - A_UINT32 qos_null; /* SW generated QOS NULL frame sent */ - A_UINT32 delayed_bar_1; /* BAR sent for MU user 1 */ - A_UINT32 delayed_bar_2; /* BAR sent for MU user 2 */ - A_UINT32 delayed_bar_3; /* BAR sent for MU user 3 */ - A_UINT32 delayed_bar_4; /* BAR sent for MU user 4 */ - A_UINT32 delayed_bar_5; /* BAR sent for MU user 5 */ - A_UINT32 delayed_bar_6; /* BAR sent for MU user 6 */ - A_UINT32 delayed_bar_7; /* BAR sent for MU user 7 */ + /** BAR sent out for SU transmission */ + A_UINT32 su_bar; + /** SW generated RTS frame sent */ + A_UINT32 rts; + /** SW generated CTS-to-self frame sent */ + A_UINT32 cts2self; + /** SW generated QOS NULL frame sent */ + A_UINT32 qos_null; + /** BAR sent for MU user 1 */ + A_UINT32 delayed_bar_1; + /** BAR sent for MU user 2 */ + A_UINT32 delayed_bar_2; + /** BAR sent for MU user 3 */ + A_UINT32 delayed_bar_3; + /** BAR sent for MU user 4 */ + A_UINT32 delayed_bar_4; + /** BAR sent for MU user 5 */ + A_UINT32 delayed_bar_5; + /** BAR sent for MU user 6 */ + A_UINT32 delayed_bar_6; + /** BAR sent for MU user 7 */ + A_UINT32 delayed_bar_7; A_UINT32 bar_with_tqm_head_seq_num; A_UINT32 bar_with_tid_seq_num; - A_UINT32 su_sw_rts_queued; /* SW generated RTS frame queued to the HW */ - A_UINT32 su_sw_rts_tried; /* SW generated RTS frame sent over the air */ - A_UINT32 su_sw_rts_err; /* SW generated RTS frame completed with error */ - A_UINT32 su_sw_rts_flushed; /* SW generated RTS frame flushed */ - A_UINT32 su_sw_rts_rcvd_cts_diff_bw; /* CTS (RTS response) received in different BW */ + /** SW generated RTS frame queued to the HW */ + A_UINT32 su_sw_rts_queued; + /** SW generated RTS frame sent over the air */ + A_UINT32 su_sw_rts_tried; + /** SW generated RTS frame completed with error */ + A_UINT32 su_sw_rts_err; + /** SW generated RTS frame flushed */ + A_UINT32 su_sw_rts_flushed; + /** CTS (RTS response) received in different BW */ + A_UINT32 su_sw_rts_rcvd_cts_diff_bw; } htt_tx_selfgen_cmn_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 ac_su_ndpa; /* 11AC VHT SU NDPA frame sent over the air */ - A_UINT32 ac_su_ndp; /* 11AC VHT SU NDP frame sent over the air */ - A_UINT32 ac_mu_mimo_ndpa; /* 11AC VHT MU MIMO NDPA frame sent over the air */ - A_UINT32 ac_mu_mimo_ndp; /* 11AC VHT MU MIMO NDP frame sent over the air */ - A_UINT32 ac_mu_mimo_brpoll_1; /* 11AC VHT MU MIMO BR-POLL for user 1 sent over the air */ - A_UINT32 ac_mu_mimo_brpoll_2; /* 11AC VHT MU MIMO BR-POLL for user 2 sent over the air */ - A_UINT32 ac_mu_mimo_brpoll_3; /* 11AC VHT MU MIMO BR-POLL for user 3 sent over the air */ - A_UINT32 ac_su_ndpa_queued; /* 11AC VHT SU NDPA frame queued to the HW */ - A_UINT32 ac_su_ndp_queued; /* 11AC VHT SU NDP frame queued to the HW */ - A_UINT32 ac_mu_mimo_ndpa_queued; /* 11AC VHT MU MIMO NDPA frame queued to the HW */ - A_UINT32 ac_mu_mimo_ndp_queued; /* 11AC VHT MU MIMO NDP frame queued to the HW */ - A_UINT32 ac_mu_mimo_brpoll_1_queued; /* 11AC VHT MU MIMO BR-POLL for user 1 frame queued to the HW */ - A_UINT32 ac_mu_mimo_brpoll_2_queued; /* 11AC VHT MU MIMO BR-POLL for user 2 frame queued to the HW */ - A_UINT32 ac_mu_mimo_brpoll_3_queued; /* 11AC VHT MU MIMO BR-POLL for user 3 frame queued to the HW */ + /** 11AC VHT SU NDPA frame sent over the air */ + A_UINT32 ac_su_ndpa; + /** 11AC VHT SU NDP frame sent over the air */ + A_UINT32 ac_su_ndp; + /** 11AC VHT MU MIMO NDPA frame sent over the air */ + A_UINT32 ac_mu_mimo_ndpa; + /** 11AC VHT MU MIMO NDP frame sent over the air */ + A_UINT32 ac_mu_mimo_ndp; + /** 11AC VHT MU MIMO BR-POLL for user 1 sent over the air */ + A_UINT32 ac_mu_mimo_brpoll_1; + /** 11AC VHT MU MIMO BR-POLL for user 2 sent over the air */ + A_UINT32 ac_mu_mimo_brpoll_2; + /** 11AC VHT MU MIMO BR-POLL for user 3 sent over the air */ + A_UINT32 ac_mu_mimo_brpoll_3; + /** 11AC VHT SU NDPA frame queued to the HW */ + A_UINT32 ac_su_ndpa_queued; + /** 11AC VHT SU NDP frame queued to the HW */ + A_UINT32 ac_su_ndp_queued; + /** 11AC VHT MU MIMO NDPA frame queued to the HW */ + A_UINT32 ac_mu_mimo_ndpa_queued; + /** 11AC VHT MU MIMO NDP frame queued to the HW */ + A_UINT32 ac_mu_mimo_ndp_queued; + /** 11AC VHT MU MIMO BR-POLL for user 1 frame queued to the HW */ + A_UINT32 ac_mu_mimo_brpoll_1_queued; + /** 11AC VHT MU MIMO BR-POLL for user 2 frame queued to the HW */ + A_UINT32 ac_mu_mimo_brpoll_2_queued; + /** 11AC VHT MU MIMO BR-POLL for user 3 frame queued to the HW */ + A_UINT32 ac_mu_mimo_brpoll_3_queued; } htt_tx_selfgen_ac_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 ax_su_ndpa; /* 11AX HE SU NDPA frame sent over the air */ - A_UINT32 ax_su_ndp; /* 11AX HE NDP frame sent over the air */ - A_UINT32 ax_mu_mimo_ndpa; /* 11AX HE MU MIMO NDPA frame sent over the air */ - A_UINT32 ax_mu_mimo_ndp; /* 11AX HE MU MIMO NDP frame sent over the air */ + /** 11AX HE SU NDPA frame sent over the air */ + A_UINT32 ax_su_ndpa; + /** 11AX HE NDP frame sent over the air */ + A_UINT32 ax_su_ndp; + /** 11AX HE MU MIMO NDPA frame sent over the air */ + A_UINT32 ax_mu_mimo_ndpa; + /** 11AX HE MU MIMO NDP frame sent over the air */ + A_UINT32 ax_mu_mimo_ndp; union { struct { /* deprecated old names */ @@ -2006,96 +2126,136 @@ typedef struct { A_UINT32 ax_mu_mimo_brpoll_6; A_UINT32 ax_mu_mimo_brpoll_7; }; - /* 11AX HE MU BR-POLL frame for users 1 - 7 sent over the air */ + /** 11AX HE MU BR-POLL frame for users 1 - 7 sent over the air */ A_UINT32 ax_mu_mimo_brpoll[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS - 1]; }; - A_UINT32 ax_basic_trigger; /* 11AX HE MU Basic Trigger frame sent over the air */ - A_UINT32 ax_bsr_trigger; /* 11AX HE MU BSRP Trigger frame sent over the air */ - A_UINT32 ax_mu_bar_trigger; /* 11AX HE MU BAR Trigger frame sent over the air */ - A_UINT32 ax_mu_rts_trigger; /* 11AX HE MU RTS Trigger frame sent over the air */ - A_UINT32 ax_ulmumimo_trigger; /* 11AX HE MU UL-MUMIMO Trigger frame sent over the air */ - A_UINT32 ax_su_ndpa_queued; /* 11AX HE SU NDPA frame queued to the HW */ - A_UINT32 ax_su_ndp_queued; /* 11AX HE SU NDP frame queued to the HW */ - A_UINT32 ax_mu_mimo_ndpa_queued; /* 11AX HE MU MIMO NDPA frame queued to the HW */ - A_UINT32 ax_mu_mimo_ndp_queued; /* 11AX HE MU MIMO NDP frame queued to the HW */ - /* 11AX HE MU BR-POLL frame for users 1 - 7 queued to the HW */ + /** 11AX HE MU Basic Trigger frame sent over the air */ + A_UINT32 ax_basic_trigger; + /** 11AX HE MU BSRP Trigger frame sent over the air */ + A_UINT32 ax_bsr_trigger; + /** 11AX HE MU BAR Trigger frame sent over the air */ + A_UINT32 ax_mu_bar_trigger; + /** 11AX HE MU RTS Trigger frame sent over the air */ + A_UINT32 ax_mu_rts_trigger; + /** 11AX HE MU UL-MUMIMO Trigger frame sent over the air */ + A_UINT32 ax_ulmumimo_trigger; + /** 11AX HE SU NDPA frame queued to the HW */ + A_UINT32 ax_su_ndpa_queued; + /** 11AX HE SU NDP frame queued to the HW */ + A_UINT32 ax_su_ndp_queued; + /** 11AX HE MU MIMO NDPA frame queued to the HW */ + A_UINT32 ax_mu_mimo_ndpa_queued; + /** 11AX HE MU MIMO NDP frame queued to the HW */ + A_UINT32 ax_mu_mimo_ndp_queued; + /** 11AX HE MU BR-POLL frame for users 1 - 7 queued to the HW */ A_UINT32 ax_mu_mimo_brpoll_queued[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS - 1]; - /* 11AX HE UL-MUMIMO Trigger frame for users 0 - 7 successfully sent over the air */ + /** + * 11AX HE UL-MUMIMO Trigger frame for users 0 - 7 + * successfully sent over the air + */ A_UINT32 ax_ul_mumimo_trigger[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; } htt_tx_selfgen_ax_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 be_su_ndpa; /* 11be EHT SU NDPA frame sent over the air */ - A_UINT32 be_su_ndp; /* 11be EHT NDP frame sent over the air */ - A_UINT32 be_mu_mimo_ndpa; /* 11be EHT MU MIMO NDPA frame sent over the air */ - A_UINT32 be_mu_mimo_ndp; /* 11be EHT MU MIMO NDP frame sent over theT air */ - /* 11be EHT MU BR-POLL frame for users 1 - 7 sent over the air */ + /** 11be EHT SU NDPA frame sent over the air */ + A_UINT32 be_su_ndpa; + /** 11be EHT NDP frame sent over the air */ + A_UINT32 be_su_ndp; + /** 11be EHT MU MIMO NDPA frame sent over the air */ + A_UINT32 be_mu_mimo_ndpa; + /** 11be EHT MU MIMO NDP frame sent over theT air */ + A_UINT32 be_mu_mimo_ndp; + /** 11be EHT MU BR-POLL frame for users 1 - 7 sent over the air */ A_UINT32 be_mu_mimo_brpoll[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS - 1]; - A_UINT32 be_basic_trigger; /* 11be EHT MU Basic Trigger frame sent over the air */ - A_UINT32 be_bsr_trigger; /* 11be EHT MU BSRP Trigger frame sent over the air */ - A_UINT32 be_mu_bar_trigger; /* 11be EHT MU BAR Trigger frame sent over the air */ - A_UINT32 be_mu_rts_trigger; /* 11be EHT MU RTS Trigger frame sent over the air */ - A_UINT32 be_ulmumimo_trigger; /* 11be EHT MU UL-MUMIMO Trigger frame sent over the air */ - A_UINT32 be_su_ndpa_queued; /* 11be EHT SU NDPA frame queued to the HW */ - A_UINT32 be_su_ndp_queued; /* 11be EHT SU NDP frame queued to the HW */ - A_UINT32 be_mu_mimo_ndpa_queued; /* 11be EHT MU MIMO NDPA frame queued to the HW */ - A_UINT32 be_mu_mimo_ndp_queued; /* 11be EHT MU MIMO NDP frame queued to the HW */ - /* 11be EHT MU BR-POLL frame for users 1 - 7 queued to the HW */ + /** 11be EHT MU Basic Trigger frame sent over the air */ + A_UINT32 be_basic_trigger; + /** 11be EHT MU BSRP Trigger frame sent over the air */ + A_UINT32 be_bsr_trigger; + /** 11be EHT MU BAR Trigger frame sent over the air */ + A_UINT32 be_mu_bar_trigger; + /** 11be EHT MU RTS Trigger frame sent over the air */ + A_UINT32 be_mu_rts_trigger; + /** 11be EHT MU UL-MUMIMO Trigger frame sent over the air */ + A_UINT32 be_ulmumimo_trigger; + /** 11be EHT SU NDPA frame queued to the HW */ + A_UINT32 be_su_ndpa_queued; + /** 11be EHT SU NDP frame queued to the HW */ + A_UINT32 be_su_ndp_queued; + /** 11be EHT MU MIMO NDPA frame queued to the HW */ + A_UINT32 be_mu_mimo_ndpa_queued; + /** 11be EHT MU MIMO NDP frame queued to the HW */ + A_UINT32 be_mu_mimo_ndp_queued; + /** 11be EHT MU BR-POLL frame for users 1 - 7 queued to the HW */ A_UINT32 be_mu_mimo_brpoll_queued[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS - 1]; - /* 11be EHT UL-MUMIMO Trigger frame for users 0 - 7 successfully sent over the air */ + /** + * 11be EHT UL-MUMIMO Trigger frame for users 0 - 7 + * successfully sent over the air + */ A_UINT32 be_ul_mumimo_trigger[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; } htt_tx_selfgen_be_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - /* 11AX HE OFDMA NDPA frame queued to the HW */ + /** 11AX HE OFDMA NDPA frame queued to the HW */ A_UINT32 ax_ofdma_ndpa_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; - /* 11AX HE OFDMA NDPA frame sent over the air */ + /** 11AX HE OFDMA NDPA frame sent over the air */ A_UINT32 ax_ofdma_ndpa_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; - /* 11AX HE OFDMA NDPA frame flushed by HW */ + /** 11AX HE OFDMA NDPA frame flushed by HW */ A_UINT32 ax_ofdma_ndpa_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; - /* 11AX HE OFDMA NDPA frame completed with error(s) */ + /** 11AX HE OFDMA NDPA frame completed with error(s) */ A_UINT32 ax_ofdma_ndpa_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; } htt_txbf_ofdma_ndpa_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - /* 11AX HE OFDMA NDP frame queued to the HW */ + /** 11AX HE OFDMA NDP frame queued to the HW */ A_UINT32 ax_ofdma_ndp_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; - /* 11AX HE OFDMA NDPA frame sent over the air */ + /** 11AX HE OFDMA NDPA frame sent over the air */ A_UINT32 ax_ofdma_ndp_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; - /* 11AX HE OFDMA NDPA frame flushed by HW */ + /** 11AX HE OFDMA NDPA frame flushed by HW */ A_UINT32 ax_ofdma_ndp_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; - /* 11AX HE OFDMA NDPA frame completed with error(s) */ + /** 11AX HE OFDMA NDPA frame completed with error(s) */ A_UINT32 ax_ofdma_ndp_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; } htt_txbf_ofdma_ndp_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - /* 11AX HE OFDMA MU BRPOLL frame queued to the HW */ + /** 11AX HE OFDMA MU BRPOLL frame queued to the HW */ A_UINT32 ax_ofdma_brpoll_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; - /* 11AX HE OFDMA MU BRPOLL frame sent over the air */ + /** 11AX HE OFDMA MU BRPOLL frame sent over the air */ A_UINT32 ax_ofdma_brpoll_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; - /* 11AX HE OFDMA MU BRPOLL frame flushed by HW */ + /** 11AX HE OFDMA MU BRPOLL frame flushed by HW */ A_UINT32 ax_ofdma_brpoll_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; - /* 11AX HE OFDMA MU BRPOLL frame completed with error(s) */ + /** 11AX HE OFDMA MU BRPOLL frame completed with error(s) */ A_UINT32 ax_ofdma_brp_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; - /* Number of CBF(s) received when 11AX HE OFDMA MU BRPOLL frame completed with error(s) */ + /** + * Number of CBF(s) received when 11AX HE OFDMA MU BRPOLL frame + * completed with error(s) + */ A_UINT32 ax_ofdma_brp_err_num_cbf_rcvd[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS+1]; } htt_txbf_ofdma_brp_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - /* 11AX HE OFDMA PPDUs that were sent over the air with steering (TXBF + OFDMA) */ + /** + * 11AX HE OFDMA PPDUs that were sent over the air with steering + * (TXBF + OFDMA) + */ A_UINT32 ax_ofdma_num_ppdu_steer[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; - /* 11AX HE OFDMA PPDUs that were sent over the air in open loop */ + /** 11AX HE OFDMA PPDUs that were sent over the air in open loop */ A_UINT32 ax_ofdma_num_ppdu_ol[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; - /* 11AX HE OFDMA number of users for which CBF prefetch was initiated to PHY HW during TX */ + /** + * 11AX HE OFDMA number of users for which CBF prefetch was initiated + * to PHY HW during TX + */ A_UINT32 ax_ofdma_num_usrs_prefetch[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; - /* 11AX HE OFDMA number of users for which sounding was initiated during TX */ + /** + * 11AX HE OFDMA number of users for which sounding was initiated + * during TX + */ A_UINT32 ax_ofdma_num_usrs_sound[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; - /* 11AX HE OFDMA number of users for which sounding was forced during TX */ + /** 11AX HE OFDMA number of users for which sounding was forced during TX */ A_UINT32 ax_ofdma_num_usrs_force_sound[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; } htt_txbf_ofdma_steer_stats_tlv; @@ -2119,28 +2279,46 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 ac_su_ndp_err; /* 11AC VHT SU NDP frame completed with error(s) */ - A_UINT32 ac_su_ndpa_err; /* 11AC VHT SU NDPA frame completed with error(s) */ - A_UINT32 ac_mu_mimo_ndpa_err; /* 11AC VHT MU MIMO NDPA frame completed with error(s) */ - A_UINT32 ac_mu_mimo_ndp_err; /* 11AC VHT MU MIMO NDP frame completed with error(s) */ - A_UINT32 ac_mu_mimo_brp1_err; /* 11AC VHT MU MIMO BRPOLL for user 1 frame completed with error(s) */ - A_UINT32 ac_mu_mimo_brp2_err; /* 11AC VHT MU MIMO BRPOLL for user 2 frame completed with error(s) */ - A_UINT32 ac_mu_mimo_brp3_err; /* 11AC VHT MU MIMO BRPOLL for user 3 frame completed with error(s) */ - A_UINT32 ac_su_ndpa_flushed; /* 11AC VHT SU NDPA frame flushed by HW */ - A_UINT32 ac_su_ndp_flushed; /* 11AC VHT SU NDP frame flushed by HW */ - A_UINT32 ac_mu_mimo_ndpa_flushed; /* 11AC VHT MU MIMO NDPA frame flushed by HW */ - A_UINT32 ac_mu_mimo_ndp_flushed; /* 11AC VHT MU MIMO NDP frame flushed by HW */ - A_UINT32 ac_mu_mimo_brpoll1_flushed; /* 11AC VHT MU MIMO BRPOLL for user 1 frame flushed by HW */ - A_UINT32 ac_mu_mimo_brpoll2_flushed; /* 11AC VHT MU MIMO BRPOLL for user 2 frame flushed by HW */ - A_UINT32 ac_mu_mimo_brpoll3_flushed; /* 11AC VHT MU MIMO BRPOLL for user 3 frame flushed by HW */ + /** 11AC VHT SU NDP frame completed with error(s) */ + A_UINT32 ac_su_ndp_err; + /** 11AC VHT SU NDPA frame completed with error(s) */ + A_UINT32 ac_su_ndpa_err; + /** 11AC VHT MU MIMO NDPA frame completed with error(s) */ + A_UINT32 ac_mu_mimo_ndpa_err; + /** 11AC VHT MU MIMO NDP frame completed with error(s) */ + A_UINT32 ac_mu_mimo_ndp_err; + /** 11AC VHT MU MIMO BRPOLL for user 1 frame completed with error(s) */ + A_UINT32 ac_mu_mimo_brp1_err; + /** 11AC VHT MU MIMO BRPOLL for user 2 frame completed with error(s) */ + A_UINT32 ac_mu_mimo_brp2_err; + /** 11AC VHT MU MIMO BRPOLL for user 3 frame completed with error(s) */ + A_UINT32 ac_mu_mimo_brp3_err; + /** 11AC VHT SU NDPA frame flushed by HW */ + A_UINT32 ac_su_ndpa_flushed; + /** 11AC VHT SU NDP frame flushed by HW */ + A_UINT32 ac_su_ndp_flushed; + /** 11AC VHT MU MIMO NDPA frame flushed by HW */ + A_UINT32 ac_mu_mimo_ndpa_flushed; + /** 11AC VHT MU MIMO NDP frame flushed by HW */ + A_UINT32 ac_mu_mimo_ndp_flushed; + /** 11AC VHT MU MIMO BRPOLL for user 1 frame flushed by HW */ + A_UINT32 ac_mu_mimo_brpoll1_flushed; + /** 11AC VHT MU MIMO BRPOLL for user 2 frame flushed by HW */ + A_UINT32 ac_mu_mimo_brpoll2_flushed; + /** 11AC VHT MU MIMO BRPOLL for user 3 frame flushed by HW */ + A_UINT32 ac_mu_mimo_brpoll3_flushed; } htt_tx_selfgen_ac_err_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 ax_su_ndp_err; /* 11AX HE SU NDP frame completed with error(s) */ - A_UINT32 ax_su_ndpa_err; /* 11AX HE SU NDPA frame completed with error(s) */ - A_UINT32 ax_mu_mimo_ndpa_err; /* 11AX HE MU MIMO NDPA frame completed with error(s) */ - A_UINT32 ax_mu_mimo_ndp_err; /* 11AX HE MU MIMO NDP frame completed with error(s) */ + /** 11AX HE SU NDP frame completed with error(s) */ + A_UINT32 ax_su_ndp_err; + /** 11AX HE SU NDPA frame completed with error(s) */ + A_UINT32 ax_su_ndpa_err; + /** 11AX HE MU MIMO NDPA frame completed with error(s) */ + A_UINT32 ax_mu_mimo_ndpa_err; + /** 11AX HE MU MIMO NDP frame completed with error(s) */ + A_UINT32 ax_mu_mimo_ndp_err; union { struct { /* deprecated old names */ @@ -2152,48 +2330,80 @@ typedef struct { A_UINT32 ax_mu_mimo_brp6_err; A_UINT32 ax_mu_mimo_brp7_err; }; - /* 11AX HE MU BR-POLL frame for 1 - 7 users completed with error(s) */ + /** 11AX HE MU BR-POLL frame for 1 - 7 users completed with error(s) */ A_UINT32 ax_mu_mimo_brp_err[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS - 1]; }; - A_UINT32 ax_basic_trigger_err; /* 11AX HE MU Basic Trigger frame completed with error(s) */ - A_UINT32 ax_bsr_trigger_err; /* 11AX HE MU BSRP Trigger frame completed with error(s) */ - A_UINT32 ax_mu_bar_trigger_err; /* 11AX HE MU BAR Trigger frame completed with error(s) */ - A_UINT32 ax_mu_rts_trigger_err; /* 11AX HE MU RTS Trigger frame completed with error(s) */ - A_UINT32 ax_ulmumimo_trigger_err; /* 11AX HE MU ULMUMIMO Trigger frame completed with error(s) */ - /* Number of CBF(s) received when 11AX HE MU MIMO BRPOLL frame completed with error(s) */ + /** 11AX HE MU Basic Trigger frame completed with error(s) */ + A_UINT32 ax_basic_trigger_err; + /** 11AX HE MU BSRP Trigger frame completed with error(s) */ + A_UINT32 ax_bsr_trigger_err; + /** 11AX HE MU BAR Trigger frame completed with error(s) */ + A_UINT32 ax_mu_bar_trigger_err; + /** 11AX HE MU RTS Trigger frame completed with error(s) */ + A_UINT32 ax_mu_rts_trigger_err; + /** 11AX HE MU ULMUMIMO Trigger frame completed with error(s) */ + A_UINT32 ax_ulmumimo_trigger_err; + /** + * Number of CBF(s) received when 11AX HE MU MIMO BRPOLL + * frame completed with error(s) + */ A_UINT32 ax_mu_mimo_brp_err_num_cbf_received[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; - A_UINT32 ax_su_ndpa_flushed; /* 11AX HE SU NDPA frame flushed by HW */ - A_UINT32 ax_su_ndp_flushed; /* 11AX HE SU NDP frame flushed by HW */ - A_UINT32 ax_mu_mimo_ndpa_flushed; /* 11AX HE MU MIMO NDPA frame flushed by HW */ - A_UINT32 ax_mu_mimo_ndp_flushed; /* 11AX HE MU MIMO NDP frame flushed by HW */ - /* 11AX HE MU BR-POLL frame for users 1 - 7 flushed by HW */ + /** 11AX HE SU NDPA frame flushed by HW */ + A_UINT32 ax_su_ndpa_flushed; + /** 11AX HE SU NDP frame flushed by HW */ + A_UINT32 ax_su_ndp_flushed; + /** 11AX HE MU MIMO NDPA frame flushed by HW */ + A_UINT32 ax_mu_mimo_ndpa_flushed; + /** 11AX HE MU MIMO NDP frame flushed by HW */ + A_UINT32 ax_mu_mimo_ndp_flushed; + /** 11AX HE MU BR-POLL frame for users 1 - 7 flushed by HW */ A_UINT32 ax_mu_mimo_brpoll_flushed[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS - 1]; - /* 11AX HE UL-MUMIMO Trigger frame for users 0 - 7 completed with error(s) */ + /** + * 11AX HE UL-MUMIMO Trigger frame for users 0 - 7 completed with error(s) + */ A_UINT32 ax_ul_mumimo_trigger_err[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; } htt_tx_selfgen_ax_err_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 be_su_ndp_err; /* 11BE EHT SU NDP frame completed with error(s) */ - A_UINT32 be_su_ndpa_err; /* 11BE EHT SU NDPA frame completed with error(s) */ - A_UINT32 be_mu_mimo_ndpa_err; /* 11BE EHT MU MIMO NDPA frame completed with error(s) */ - A_UINT32 be_mu_mimo_ndp_err; /* 11BE EHT MU MIMO NDP frame completed with error(s) */ - /* 11BE EHT MU BR-POLL frame for 1 - 7 users completed with error(s) */ + /** 11BE EHT SU NDP frame completed with error(s) */ + A_UINT32 be_su_ndp_err; + /** 11BE EHT SU NDPA frame completed with error(s) */ + A_UINT32 be_su_ndpa_err; + /** 11BE EHT MU MIMO NDPA frame completed with error(s) */ + A_UINT32 be_mu_mimo_ndpa_err; + /** 11BE EHT MU MIMO NDP frame completed with error(s) */ + A_UINT32 be_mu_mimo_ndp_err; + /** 11BE EHT MU BR-POLL frame for 1 - 7 users completed with error(s) */ A_UINT32 be_mu_mimo_brp_err[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS - 1]; - A_UINT32 be_basic_trigger_err; /* 11BE EHT MU Basic Trigger frame completed with error(s) */ - A_UINT32 be_bsr_trigger_err; /* 11BE EHT MU BSRP Trigger frame completed with error(s) */ - A_UINT32 be_mu_bar_trigger_err; /* 11BE EHT MU BAR Trigger frame completed with error(s) */ - A_UINT32 be_mu_rts_trigger_err; /* 11BE EHT MU RTS Trigger frame completed with error(s) */ - A_UINT32 be_ulmumimo_trigger_err; /* 11BE EHT MU ULMUMIMO Trigger frame completed with error(s) */ - /* Number of CBF(s) received when 11BE EHT MU MIMO BRPOLL frame completed with error(s) */ + /** 11BE EHT MU Basic Trigger frame completed with error(s) */ + A_UINT32 be_basic_trigger_err; + /** 11BE EHT MU BSRP Trigger frame completed with error(s) */ + A_UINT32 be_bsr_trigger_err; + /** 11BE EHT MU BAR Trigger frame completed with error(s) */ + A_UINT32 be_mu_bar_trigger_err; + /** 11BE EHT MU RTS Trigger frame completed with error(s) */ + A_UINT32 be_mu_rts_trigger_err; + /** 11BE EHT MU ULMUMIMO Trigger frame completed with error(s) */ + A_UINT32 be_ulmumimo_trigger_err; + /** + * Number of CBF(s) received when 11BE EHT MU MIMO BRPOLL frame + * completed with error(s) + */ A_UINT32 be_mu_mimo_brp_err_num_cbf_received[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; - A_UINT32 be_su_ndpa_flushed; /* 11BE EHT SU NDPA frame flushed by HW */ - A_UINT32 be_su_ndp_flushed; /* 11BE EHT SU NDP frame flushed by HW */ - A_UINT32 be_mu_mimo_ndpa_flushed; /* 11BE EHT MU MIMO NDPA frame flushed by HW */ - A_UINT32 be_mu_mimo_ndp_flushed; /* 11BE HT MU MIMO NDP frame flushed by HW */ - /* 11BE EHT MU BR-POLL frame for users 1 - 7 flushed by HW */ + /** 11BE EHT SU NDPA frame flushed by HW */ + A_UINT32 be_su_ndpa_flushed; + /** 11BE EHT SU NDP frame flushed by HW */ + A_UINT32 be_su_ndp_flushed; + /** 11BE EHT MU MIMO NDPA frame flushed by HW */ + A_UINT32 be_mu_mimo_ndpa_flushed; + /** 11BE HT MU MIMO NDP frame flushed by HW */ + A_UINT32 be_mu_mimo_ndp_flushed; + /** 11BE EHT MU BR-POLL frame for users 1 - 7 flushed by HW */ A_UINT32 be_mu_mimo_brpoll_flushed[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS - 1]; - /* 11BE EHT UL-MUMIMO Trigger frame for users 0 - 7 completed with error(s) */ + /** + * 11BE EHT UL-MUMIMO Trigger frame for users 0 - 7 completed with error(s) + */ A_UINT32 be_ul_mumimo_trigger_err[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; } htt_tx_selfgen_be_err_stats_tlv; @@ -2227,88 +2437,95 @@ typedef struct { * received by HW for queuing within SIFS interval. */ - typedef struct { htt_tlv_hdr_t tlv_hdr; - /* 11AC VHT SU NDPA scheduler completion status reason code */ + /** 11AC VHT SU NDPA scheduler completion status reason code */ A_UINT32 ac_su_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; - /* 11AC VHT SU NDP scheduler completion status reason code */ + /** 11AC VHT SU NDP scheduler completion status reason code */ A_UINT32 ac_su_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; - /* 11AC VHT SU NDP scheduler error code */ + /** 11AC VHT SU NDP scheduler error code */ A_UINT32 ac_su_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; - /* 11AC VHT MU MIMO NDPA scheduler completion status reason code */ + /** 11AC VHT MU MIMO NDPA scheduler completion status reason code */ A_UINT32 ac_mu_mimo_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; - /* 11AC VHT MU MIMO NDP scheduler completion status reason code */ + /** 11AC VHT MU MIMO NDP scheduler completion status reason code */ A_UINT32 ac_mu_mimo_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; - /* 11AC VHT MU MIMO NDP scheduler error code */ + /** 11AC VHT MU MIMO NDP scheduler error code */ A_UINT32 ac_mu_mimo_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; - /* 11AC VHT MU MIMO BRPOLL scheduler completion status reason code */ + /** 11AC VHT MU MIMO BRPOLL scheduler completion status reason code */ A_UINT32 ac_mu_mimo_brp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; - /* 11AC VHT MU MIMO BRPOLL scheduler error code */ + /** 11AC VHT MU MIMO BRPOLL scheduler error code */ A_UINT32 ac_mu_mimo_brp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; } htt_tx_selfgen_ac_sched_status_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - /* 11AX HE SU NDPA scheduler completion status reason code */ + /** 11AX HE SU NDPA scheduler completion status reason code */ A_UINT32 ax_su_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; - /* 11AX SU NDP scheduler completion status reason code */ + /** 11AX SU NDP scheduler completion status reason code */ A_UINT32 ax_su_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; - /* 11AX HE SU NDP scheduler error code */ + /** 11AX HE SU NDP scheduler error code */ A_UINT32 ax_su_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; - /* 11AX HE MU MIMO NDPA scheduler completion status reason code */ + /** 11AX HE MU MIMO NDPA scheduler completion status reason code */ A_UINT32 ax_mu_mimo_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; - /* 11AX HE MU MIMO NDP scheduler completion status reason code */ + /** 11AX HE MU MIMO NDP scheduler completion status reason code */ A_UINT32 ax_mu_mimo_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; - /* 11AX HE MU MIMO NDP scheduler error code */ + /** 11AX HE MU MIMO NDP scheduler error code */ A_UINT32 ax_mu_mimo_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; - /* 11AX HE MU MIMO MU BRPOLL scheduler completion status reason code */ + /** 11AX HE MU MIMO MU BRPOLL scheduler completion status reason code */ A_UINT32 ax_mu_brp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; - /* 11AX HE MU MIMO MU BRPOLL scheduler error code */ + /** 11AX HE MU MIMO MU BRPOLL scheduler error code */ A_UINT32 ax_mu_brp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; - /* 11AX HE MU BAR scheduler completion status reason code */ + /** 11AX HE MU BAR scheduler completion status reason code */ A_UINT32 ax_mu_bar_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; - /* 11AX HE MU BAR scheduler error code */ + /** 11AX HE MU BAR scheduler error code */ A_UINT32 ax_mu_bar_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; - /* 11AX HE UL OFDMA Basic Trigger scheduler completion status reason code */ + /** + * 11AX HE UL OFDMA Basic Trigger scheduler completion status reason code + */ A_UINT32 ax_basic_trig_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; - /* 11AX HE UL OFDMA Basic Trigger scheduler error code */ + /** 11AX HE UL OFDMA Basic Trigger scheduler error code */ A_UINT32 ax_basic_trig_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; - /* 11AX HE UL MUMIMO Basic Trigger scheduler completion status reason code */ + /** + * 11AX HE UL MUMIMO Basic Trigger scheduler completion status reason code + */ A_UINT32 ax_ulmumimo_trig_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; - /* 11AX HE UL MUMIMO Basic Trigger scheduler error code */ + /** 11AX HE UL MUMIMO Basic Trigger scheduler error code */ A_UINT32 ax_ulmumimo_trig_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; } htt_tx_selfgen_ax_sched_status_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - /* 11BE EHT SU NDPA scheduler completion status reason code */ + /** 11BE EHT SU NDPA scheduler completion status reason code */ A_UINT32 be_su_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; - /* 11BE SU NDP scheduler completion status reason code */ + /** 11BE SU NDP scheduler completion status reason code */ A_UINT32 be_su_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; - /* 11BE EHT SU NDP scheduler error code */ + /** 11BE EHT SU NDP scheduler error code */ A_UINT32 be_su_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; - /* 11BE EHT MU MIMO NDPA scheduler completion status reason code */ + /** 11BE EHT MU MIMO NDPA scheduler completion status reason code */ A_UINT32 be_mu_mimo_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; - /* 11BE EHT MU MIMO NDP scheduler completion status reason code */ + /** 11BE EHT MU MIMO NDP scheduler completion status reason code */ A_UINT32 be_mu_mimo_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; - /* 11BE EHT MU MIMO NDP scheduler error code */ + /** 11BE EHT MU MIMO NDP scheduler error code */ A_UINT32 be_mu_mimo_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; - /* 11BE EHT MU MIMO MU BRPOLL scheduler completion status reason code */ + /** 11BE EHT MU MIMO MU BRPOLL scheduler completion status reason code */ A_UINT32 be_mu_brp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; - /* 11BE EHT MU MIMO MU BRPOLL scheduler error code */ + /** 11BE EHT MU MIMO MU BRPOLL scheduler error code */ A_UINT32 be_mu_brp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; - /* 11BE EHT MU BAR scheduler completion status reason code */ + /** 11BE EHT MU BAR scheduler completion status reason code */ A_UINT32 be_mu_bar_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; - /* 11BE EHT MU BAR scheduler error code */ + /** 11BE EHT MU BAR scheduler error code */ A_UINT32 be_mu_bar_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; - /* 11BE EHT UL OFDMA Basic Trigger scheduler completion status reason code */ + /** + * 11BE EHT UL OFDMA Basic Trigger scheduler completion status reason code + */ A_UINT32 be_basic_trig_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; - /* 11BE EHT UL OFDMA Basic Trigger scheduler error code */ + /** 11BE EHT UL OFDMA Basic Trigger scheduler error code */ A_UINT32 be_basic_trig_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; - /* 11BE EHT UL MUMIMO Basic Trigger scheduler completion status reason code */ + /** + * 11BE EHT UL MUMIMO Basic Trigger scheduler completion status reason code + */ A_UINT32 be_ulmumimo_trig_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; - /* 11BE EHT UL MUMIMO Basic Trigger scheduler error code */ + /** 11BE EHT UL MUMIMO Basic Trigger scheduler error code */ A_UINT32 be_ulmumimo_trig_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; } htt_tx_selfgen_be_sched_status_stats_tlv; @@ -2346,9 +2563,12 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 mu_mimo_sch_posted; /* Number of MU MIMO schedules posted to HW */ - A_UINT32 mu_mimo_sch_failed; /* Number of MU MIMO schedules failed to post */ - A_UINT32 mu_mimo_ppdu_posted; /* Number of MU MIMO PPDUs posted to HW */ + /** Number of MU MIMO schedules posted to HW */ + A_UINT32 mu_mimo_sch_posted; + /** Number of MU MIMO schedules failed to post */ + A_UINT32 mu_mimo_sch_failed; + /** Number of MU MIMO PPDUs posted to HW */ + A_UINT32 mu_mimo_ppdu_posted; /* * This is the common description for the below sch stats. * Counts the number of transmissions of each number of MU users @@ -2359,33 +2579,37 @@ typedef struct { * TX PPDUs and so on. * The same is applicable for the other TX mode stats. */ - /* Represents the count for 11AC DL MU MIMO sequences */ + /** Represents the count for 11AC DL MU MIMO sequences */ A_UINT32 ac_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; - /* Represents the count for 11AX DL MU MIMO sequences */ + /** Represents the count for 11AX DL MU MIMO sequences */ A_UINT32 ax_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; - /* Represents the count for 11AX DL MU OFDMA sequences */ + /** Represents the count for 11AX DL MU OFDMA sequences */ A_UINT32 ax_ofdma_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; - /* Represents the count for 11AX UL MU OFDMA sequences with Basic Triggers */ + /** + * Represents the count for 11AX UL MU OFDMA sequences with Basic Triggers + */ A_UINT32 ax_ul_ofdma_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; - /* Represents the count for 11AX UL MU OFDMA sequences with BSRP Triggers */ + /** Represents the count for 11AX UL MU OFDMA sequences with BSRP Triggers */ A_UINT32 ax_ul_ofdma_bsr_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; - /* Represents the count for 11AX UL MU OFDMA sequences with BAR Triggers */ + /** Represents the count for 11AX UL MU OFDMA sequences with BAR Triggers */ A_UINT32 ax_ul_ofdma_bar_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; - /* Represents the count for 11AX UL MU OFDMA sequences with BRP Triggers */ + /** Represents the count for 11AX UL MU OFDMA sequences with BRP Triggers */ A_UINT32 ax_ul_ofdma_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; - /* Represents the count for 11AX UL MU MIMO sequences with Basic Triggers */ + /** + * Represents the count for 11AX UL MU MIMO sequences with Basic Triggers + */ A_UINT32 ax_ul_mumimo_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; - /* Represents the count for 11AX UL MU MIMO sequences with BRP Triggers */ + /** Represents the count for 11AX UL MU MIMO sequences with BRP Triggers */ A_UINT32 ax_ul_mumimo_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; - /* Number of 11AC DL MU MIMO schedules posted per group size (0-3) */ + /** Number of 11AC DL MU MIMO schedules posted per group size (0-3) */ A_UINT32 ac_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; - /* Number of 11AX DL MU MIMO schedules posted per group size */ + /** Number of 11AX DL MU MIMO schedules posted per group size */ A_UINT32 ax_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; - /* Represents the count for 11BE DL MU MIMO sequences */ + /** Represents the count for 11BE DL MU MIMO sequences */ A_UINT32 be_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; - /* Number of 11BE DL MU MIMO schedules posted per group size */ + /** Number of 11BE DL MU MIMO schedules posted per group size */ A_UINT32 be_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; - /* Number of 11AC DL MU MIMO schedules posted per group size (4-7) */ + /** Number of 11AC DL MU MIMO schedules posted per group size (4-7) */ A_UINT32 ac_mu_mimo_sch_posted_per_grp_sz_ext[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; } htt_tx_pdev_mu_mimo_sch_stats_tlv; @@ -2413,9 +2637,12 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 mu_mimo_sch_posted; /* Number of MU MIMO schedules posted to HW */ - A_UINT32 mu_mimo_sch_failed; /* Number of MU MIMO schedules failed to post */ - A_UINT32 mu_mimo_ppdu_posted; /* Number of MU MIMO PPDUs posted to HW */ + /** Number of MU MIMO schedules posted to HW */ + A_UINT32 mu_mimo_sch_posted; + /** Number of MU MIMO schedules failed to post */ + A_UINT32 mu_mimo_sch_failed; + /** Number of MU MIMO PPDUs posted to HW */ + A_UINT32 mu_mimo_ppdu_posted; /* * This is the common description for the below sch stats. * Counts the number of transmissions of each number of MU users @@ -2426,99 +2653,144 @@ typedef struct { * TX PPDUs and so on. * The same is applicable for the other TX mode stats. */ - /* Represents the count for 11AC DL MU MIMO sequences */ + /** Represents the count for 11AC DL MU MIMO sequences */ A_UINT32 ac_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; - /* Represents the count for 11AX DL MU MIMO sequences */ + /** Represents the count for 11AX DL MU MIMO sequences */ A_UINT32 ax_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; - /* Number of 11AC DL MU MIMO schedules posted per group size (0-3) */ + /** Number of 11AC DL MU MIMO schedules posted per group size (0-3) */ A_UINT32 ac_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; - /* Number of 11AX DL MU MIMO schedules posted per group size */ + /** Number of 11AX DL MU MIMO schedules posted per group size */ A_UINT32 ax_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; - /* Represents the count for 11BE DL MU MIMO sequences */ + /** Represents the count for 11BE DL MU MIMO sequences */ A_UINT32 be_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; - /* Number of 11BE DL MU MIMO schedules posted per group size */ + /** Number of 11BE DL MU MIMO schedules posted per group size */ A_UINT32 be_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; - /* Number of 11AC DL MU MIMO schedules posted per group size (4 - 7)*/ + /** Number of 11AC DL MU MIMO schedules posted per group size (4 - 7)*/ A_UINT32 ac_mu_mimo_sch_posted_per_grp_sz_ext[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; } htt_tx_pdev_dl_mu_mimo_sch_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - /* Represents the count for 11AX DL MU OFDMA sequences */ + /** Represents the count for 11AX DL MU OFDMA sequences */ A_UINT32 ax_mu_ofdma_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; } htt_tx_pdev_dl_mu_ofdma_sch_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - /* Represents the count for 11BE DL MU OFDMA sequences */ + /** Represents the count for 11BE DL MU OFDMA sequences */ A_UINT32 be_mu_ofdma_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; } htt_tx_pdev_be_dl_mu_ofdma_sch_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - /* Represents the count for 11AX UL MU OFDMA sequences with Basic Triggers */ + /** + * Represents the count for 11AX UL MU OFDMA sequences with Basic Triggers + */ A_UINT32 ax_ul_mu_ofdma_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; - /* Represents the count for 11AX UL MU OFDMA sequences with BSRP Triggers */ + /** + * Represents the count for 11AX UL MU OFDMA sequences with BSRP Triggers + */ A_UINT32 ax_ul_mu_ofdma_bsr_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; - /* Represents the count for 11AX UL MU OFDMA sequences with BAR Triggers */ + /** + * Represents the count for 11AX UL MU OFDMA sequences with BAR Triggers + */ A_UINT32 ax_ul_mu_ofdma_bar_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; - /* Represents the count for 11AX UL MU OFDMA sequences with BRP Triggers */ + /** + * Represents the count for 11AX UL MU OFDMA sequences with BRP Triggers + */ A_UINT32 ax_ul_mu_ofdma_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; } htt_tx_pdev_ul_mu_ofdma_sch_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - /* Represents the count for 11BE UL MU OFDMA sequences with Basic Triggers */ + /** + * Represents the count for 11BE UL MU OFDMA sequences with Basic Triggers + */ A_UINT32 be_ul_mu_ofdma_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; - /* Represents the count for 11BE UL MU OFDMA sequences with BSRP Triggers */ + /** + * Represents the count for 11BE UL MU OFDMA sequences with BSRP Triggers + */ A_UINT32 be_ul_mu_ofdma_bsr_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; - /* Represents the count for 11BE UL MU OFDMA sequences with BAR Triggers */ + /** + * Represents the count for 11BE UL MU OFDMA sequences with BAR Triggers + */ A_UINT32 be_ul_mu_ofdma_bar_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; - /* Represents the count for 11BE UL MU OFDMA sequences with BRP Triggers */ + /** + * Represents the count for 11BE UL MU OFDMA sequences with BRP Triggers + */ A_UINT32 be_ul_mu_ofdma_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; } htt_tx_pdev_be_ul_mu_ofdma_sch_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - /* Represents the count for 11AX UL MU MIMO sequences with Basic Triggers */ + /** + * Represents the count for 11AX UL MU MIMO sequences with Basic Triggers + */ A_UINT32 ax_ul_mu_mimo_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; - /* Represents the count for 11AX UL MU MIMO sequences with BRP Triggers */ + /** + * Represents the count for 11AX UL MU MIMO sequences with BRP Triggers + */ A_UINT32 ax_ul_mu_mimo_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; } htt_tx_pdev_ul_mu_mimo_sch_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - /* Represents the count for 11BE UL MU MIMO sequences with Basic Triggers */ + /** + * Represents the count for 11BE UL MU MIMO sequences with Basic Triggers + */ A_UINT32 be_ul_mu_mimo_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; - /* Represents the count for 11BE UL MU MIMO sequences with BRP Triggers */ + /** + * Represents the count for 11BE UL MU MIMO sequences with BRP Triggers + */ A_UINT32 be_ul_mu_mimo_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; } htt_tx_pdev_be_ul_mu_mimo_sch_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 mu_mimo_mpdus_queued_usr; /* 11AC DL MU MIMO number of mpdus queued to HW, per user */ - A_UINT32 mu_mimo_mpdus_tried_usr; /* 11AC DL MU MIMO number of mpdus tried over the air, per user */ - A_UINT32 mu_mimo_mpdus_failed_usr; /* 11AC DL MU MIMO number of mpdus failed acknowledgement, per user */ - A_UINT32 mu_mimo_mpdus_requeued_usr; /* 11AC DL MU MIMO number of mpdus re-queued to HW, per user */ - A_UINT32 mu_mimo_err_no_ba_usr; /* 11AC DL MU MIMO BA not receieved, per user */ - A_UINT32 mu_mimo_mpdu_underrun_usr; /* 11AC DL MU MIMO mpdu underrun encountered, per user */ - A_UINT32 mu_mimo_ampdu_underrun_usr; /* 11AC DL MU MIMO ampdu underrun encountered, per user */ - - A_UINT32 ax_mu_mimo_mpdus_queued_usr; /* 11AX MU MIMO number of mpdus queued to HW, per user */ - A_UINT32 ax_mu_mimo_mpdus_tried_usr; /* 11AX MU MIMO number of mpdus tried over the air, per user */ - A_UINT32 ax_mu_mimo_mpdus_failed_usr; /* 11AX DL MU MIMO number of mpdus failed acknowledgement, per user */ - A_UINT32 ax_mu_mimo_mpdus_requeued_usr; /* 11AX DL MU MIMO number of mpdus re-queued to HW, per user */ - A_UINT32 ax_mu_mimo_err_no_ba_usr; /* 11AX DL MU MIMO BA not receieved, per user */ - A_UINT32 ax_mu_mimo_mpdu_underrun_usr; /* 11AX DL MU MIMO mpdu underrun encountered, per user */ - A_UINT32 ax_mu_mimo_ampdu_underrun_usr; /* 11AX DL MU MIMO ampdu underrun encountered, per user */ - - A_UINT32 ax_ofdma_mpdus_queued_usr; /* 11AX MU OFDMA number of mpdus queued to HW, per user */ - A_UINT32 ax_ofdma_mpdus_tried_usr; /* 11AX MU OFDMA number of mpdus tried over the air, per user */ - A_UINT32 ax_ofdma_mpdus_failed_usr; /* 11AX MU OFDMA number of mpdus failed acknowledgement, per user */ - A_UINT32 ax_ofdma_mpdus_requeued_usr; /* 11AX MU OFDMA number of mpdus re-queued to HW, per user */ - A_UINT32 ax_ofdma_err_no_ba_usr; /* 11AX MU OFDMA BA not receieved, per user */ - A_UINT32 ax_ofdma_mpdu_underrun_usr; /* 11AX MU OFDMA mpdu underrun encountered, per user */ - A_UINT32 ax_ofdma_ampdu_underrun_usr; /* 11AX MU OFDMA ampdu underrun encountered, per user */ + /** 11AC DL MU MIMO number of mpdus queued to HW, per user */ + A_UINT32 mu_mimo_mpdus_queued_usr; + /** 11AC DL MU MIMO number of mpdus tried over the air, per user */ + A_UINT32 mu_mimo_mpdus_tried_usr; + /** 11AC DL MU MIMO number of mpdus failed acknowledgement, per user */ + A_UINT32 mu_mimo_mpdus_failed_usr; + /** 11AC DL MU MIMO number of mpdus re-queued to HW, per user */ + A_UINT32 mu_mimo_mpdus_requeued_usr; + /** 11AC DL MU MIMO BA not receieved, per user */ + A_UINT32 mu_mimo_err_no_ba_usr; + /** 11AC DL MU MIMO mpdu underrun encountered, per user */ + A_UINT32 mu_mimo_mpdu_underrun_usr; + /** 11AC DL MU MIMO ampdu underrun encountered, per user */ + A_UINT32 mu_mimo_ampdu_underrun_usr; + + /** 11AX MU MIMO number of mpdus queued to HW, per user */ + A_UINT32 ax_mu_mimo_mpdus_queued_usr; + /** 11AX MU MIMO number of mpdus tried over the air, per user */ + A_UINT32 ax_mu_mimo_mpdus_tried_usr; + /** 11AX DL MU MIMO number of mpdus failed acknowledgement, per user */ + A_UINT32 ax_mu_mimo_mpdus_failed_usr; + /** 11AX DL MU MIMO number of mpdus re-queued to HW, per user */ + A_UINT32 ax_mu_mimo_mpdus_requeued_usr; + /** 11AX DL MU MIMO BA not receieved, per user */ + A_UINT32 ax_mu_mimo_err_no_ba_usr; + /** 11AX DL MU MIMO mpdu underrun encountered, per user */ + A_UINT32 ax_mu_mimo_mpdu_underrun_usr; + /** 11AX DL MU MIMO ampdu underrun encountered, per user */ + A_UINT32 ax_mu_mimo_ampdu_underrun_usr; + + /** 11AX MU OFDMA number of mpdus queued to HW, per user */ + A_UINT32 ax_ofdma_mpdus_queued_usr; + /** 11AX MU OFDMA number of mpdus tried over the air, per user */ + A_UINT32 ax_ofdma_mpdus_tried_usr; + /** 11AX MU OFDMA number of mpdus failed acknowledgement, per user */ + A_UINT32 ax_ofdma_mpdus_failed_usr; + /** 11AX MU OFDMA number of mpdus re-queued to HW, per user */ + A_UINT32 ax_ofdma_mpdus_requeued_usr; + /** 11AX MU OFDMA BA not receieved, per user */ + A_UINT32 ax_ofdma_err_no_ba_usr; + /** 11AX MU OFDMA mpdu underrun encountered, per user */ + A_UINT32 ax_ofdma_mpdu_underrun_usr; + /** 11AX MU OFDMA ampdu underrun encountered, per user */ + A_UINT32 ax_ofdma_ampdu_underrun_usr; } htt_tx_pdev_mu_mimo_mpdu_stats_tlv; #define HTT_STATS_TX_SCHED_MODE_MU_MIMO_AC 1 /* SCHED_TX_MODE_MU_MIMO_AC */ @@ -2538,7 +2810,8 @@ typedef struct { A_UINT32 mpdu_underrun_usr; A_UINT32 ampdu_underrun_usr; A_UINT32 user_index; - A_UINT32 tx_sched_mode; /* HTT_STATS_TX_SCHED_MODE_xxx */ + /** HTT_STATS_TX_SCHED_MODE_xxx */ + A_UINT32 tx_sched_mode; } htt_tx_pdev_mpdu_stats_tlv; /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TX_MU @@ -2571,7 +2844,7 @@ typedef struct { /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - /* Scheduler command posted per tx_mode */ + /** Scheduler command posted per tx_mode */ A_UINT32 sched_cmd_posted[1/* length = num tx modes */]; } htt_sched_txq_cmd_posted_tlv_v; @@ -2580,7 +2853,7 @@ typedef struct { /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - /* Scheduler command reaped per tx_mode */ + /** Scheduler command reaped per tx_mode */ A_UINT32 sched_cmd_reaped[1/* length = num tx modes */]; } htt_sched_txq_cmd_reaped_tlv_v; @@ -2589,7 +2862,7 @@ typedef struct { /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - /* + /** * sched_order_su contains the peer IDs of peers chosen in the last * NUM_SCHED_ORDER_LOG scheduler instances. * The array is circular; it's unspecified which array element corresponds @@ -2644,8 +2917,14 @@ typedef enum { /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - /* sched_ineligibility counts the number of occurrences of different reasons for tid ineligibility during eligibility checks per txq in scheduling */ - A_UINT32 sched_ineligibility[1]; /* indexed by htt_sched_txq_sched_ineligibility_tlv_enum */ + /** + * sched_ineligibility counts the number of occurrences of different + * reasons for tid ineligibility during eligibility checks per txq + * in scheduling + * + * Indexed by htt_sched_txq_sched_ineligibility_tlv_enum. + */ + A_UINT32 sched_ineligibility[1]; } htt_sched_txq_sched_ineligibility_tlv_v; typedef enum { @@ -2664,7 +2943,7 @@ typedef enum { /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - /* + /** * supercycle_triggers[] is a histogram that counts the number of * occurrences of each different reason for a transmit scheduler * supercycle to be triggered. @@ -2706,66 +2985,70 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* BIT [ 7 : 0] :- mac_id + /** + * BIT [ 7 : 0] :- mac_id * BIT [15 : 8] :- txq_id * BIT [31 : 16] :- reserved */ A_UINT32 mac_id__txq_id__word; - /* Scheduler policy ised for this TxQ */ + /** Scheduler policy ised for this TxQ */ A_UINT32 sched_policy; - /* Timestamp of last scheduler command posted */ + /** Timestamp of last scheduler command posted */ A_UINT32 last_sched_cmd_posted_timestamp; - /* Timestamp of last scheduler command completed */ + /** Timestamp of last scheduler command completed */ A_UINT32 last_sched_cmd_compl_timestamp; - /* Num of Sched2TAC ring hit Low Water Mark condition */ + /** Num of Sched2TAC ring hit Low Water Mark condition */ A_UINT32 sched_2_tac_lwm_count; - /* Num of Sched2TAC ring full condition */ + /** Num of Sched2TAC ring full condition */ A_UINT32 sched_2_tac_ring_full; - /* Num of scheduler command post failures that includes su/mu mimo/mu ofdma sequence type */ + /** + * Num of scheduler command post failures that includes SU/MU-MIMO/MU-OFDMA + * sequence type + */ A_UINT32 sched_cmd_post_failure; - /* Num of active tids for this TxQ at current instance */ + /** Num of active tids for this TxQ at current instance */ A_UINT32 num_active_tids; - /* Num of powersave schedules */ + /** Num of powersave schedules */ A_UINT32 num_ps_schedules; - /* Num of scheduler commands pending for this TxQ */ + /** Num of scheduler commands pending for this TxQ */ A_UINT32 sched_cmds_pending; - /* Num of tidq registration for this TxQ */ + /** Num of tidq registration for this TxQ */ A_UINT32 num_tid_register; - /* Num of tidq de-registration for this TxQ */ + /** Num of tidq de-registration for this TxQ */ A_UINT32 num_tid_unregister; - /* Num of iterations msduq stats was updated */ + /** Num of iterations msduq stats was updated */ A_UINT32 num_qstats_queried; - /* qstats query update status */ + /** qstats query update status */ A_UINT32 qstats_update_pending; - /* Timestamp of Last query stats made */ + /** Timestamp of Last query stats made */ A_UINT32 last_qstats_query_timestamp; - /* Num of sched2tqm command queue full condition */ + /** Num of sched2tqm command queue full condition */ A_UINT32 num_tqm_cmdq_full; - /* Num of scheduler trigger from DE Module */ + /** Num of scheduler trigger from DE Module */ A_UINT32 num_de_sched_algo_trigger; - /* Num of scheduler trigger from RT Module */ + /** Num of scheduler trigger from RT Module */ A_UINT32 num_rt_sched_algo_trigger; - /* Num of scheduler trigger from TQM Module */ + /** Num of scheduler trigger from TQM Module */ A_UINT32 num_tqm_sched_algo_trigger; - /* Num of schedules for notify frame */ + /** Num of schedules for notify frame */ A_UINT32 notify_sched; - /* Duration based sendn termination */ + /** Duration based sendn termination */ A_UINT32 dur_based_sendn_term; - /* scheduled via NOTIFY2 */ + /** scheduled via NOTIFY2 */ A_UINT32 su_notify2_sched; - /* schedule if queued packets are greater than avg MSDUs in PPDU */ + /** schedule if queued packets are greater than avg MSDUs in PPDU */ A_UINT32 su_optimal_queued_msdus_sched; - /* schedule due to timeout */ + /** schedule due to timeout */ A_UINT32 su_delay_timeout_sched; - /* delay if txtime is less than 500us */ + /** delay if txtime is less than 500us */ A_UINT32 su_min_txtime_sched_delay; - /* scheduled via no delay */ + /** scheduled via no delay */ A_UINT32 su_no_delay; - /* Num of supercycles for this TxQ */ + /** Num of supercycles for this TxQ */ A_UINT32 num_supercycles; - /* Num of subcycles with sort for this TxQ */ + /** Num of subcycles with sort for this TxQ */ A_UINT32 num_subcycles_with_sort; - /* Num of subcycles without sort for this Txq */ + /** Num of subcycles without sort for this Txq */ A_UINT32 num_subcycles_no_sort; } htt_tx_pdev_stats_sched_per_txq_tlv; @@ -2785,11 +3068,12 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* BIT [ 7 : 0] :- mac_id + /** + * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ A_UINT32 mac_id__word; - /* Current timestamp */ + /** Current timestamp */ A_UINT32 current_timestamp; } htt_stats_tx_sched_cmn_tlv; @@ -2851,33 +3135,33 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 msdu_count; - A_UINT32 mpdu_count; - A_UINT32 remove_msdu; - A_UINT32 remove_mpdu; - A_UINT32 remove_msdu_ttl; - A_UINT32 send_bar; - A_UINT32 bar_sync; - A_UINT32 notify_mpdu; - A_UINT32 sync_cmd; - A_UINT32 write_cmd; - A_UINT32 hwsch_trigger; - A_UINT32 ack_tlv_proc; - A_UINT32 gen_mpdu_cmd; - A_UINT32 gen_list_cmd; - A_UINT32 remove_mpdu_cmd; - A_UINT32 remove_mpdu_tried_cmd; - A_UINT32 mpdu_queue_stats_cmd; - A_UINT32 mpdu_head_info_cmd; - A_UINT32 msdu_flow_stats_cmd; - A_UINT32 remove_msdu_cmd; - A_UINT32 remove_msdu_ttl_cmd; - A_UINT32 flush_cache_cmd; - A_UINT32 update_mpduq_cmd; - A_UINT32 enqueue; - A_UINT32 enqueue_notify; - A_UINT32 notify_mpdu_at_head; - A_UINT32 notify_mpdu_state_valid; + A_UINT32 msdu_count; + A_UINT32 mpdu_count; + A_UINT32 remove_msdu; + A_UINT32 remove_mpdu; + A_UINT32 remove_msdu_ttl; + A_UINT32 send_bar; + A_UINT32 bar_sync; + A_UINT32 notify_mpdu; + A_UINT32 sync_cmd; + A_UINT32 write_cmd; + A_UINT32 hwsch_trigger; + A_UINT32 ack_tlv_proc; + A_UINT32 gen_mpdu_cmd; + A_UINT32 gen_list_cmd; + A_UINT32 remove_mpdu_cmd; + A_UINT32 remove_mpdu_tried_cmd; + A_UINT32 mpdu_queue_stats_cmd; + A_UINT32 mpdu_head_info_cmd; + A_UINT32 msdu_flow_stats_cmd; + A_UINT32 remove_msdu_cmd; + A_UINT32 remove_msdu_ttl_cmd; + A_UINT32 flush_cache_cmd; + A_UINT32 update_mpduq_cmd; + A_UINT32 enqueue; + A_UINT32 enqueue_notify; + A_UINT32 notify_mpdu_at_head; + A_UINT32 notify_mpdu_state_valid; /* * On receiving TQM_FLOW_NOT_EMPTY_STATUS from TQM, (on MSDUs being enqueued * the flow is non empty), if the number of MSDUs is greater than the threshold, @@ -2912,7 +3196,8 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* BIT [ 7 : 0] :- mac_id + /** + * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ A_UINT32 mac_id__word; @@ -3011,7 +3296,8 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* BIT [ 7 : 0] :- mac_id + /* + * BIT [ 7 : 0] :- mac_id * BIT [15 : 8] :- cmdq_id * BIT [31 : 16] :- reserved */ @@ -3050,77 +3336,77 @@ typedef struct { /* Structures for tx de stats */ typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 m1_packets; - A_UINT32 m2_packets; - A_UINT32 m3_packets; - A_UINT32 m4_packets; - A_UINT32 g1_packets; - A_UINT32 g2_packets; - A_UINT32 rc4_packets; - A_UINT32 eap_packets; - A_UINT32 eapol_start_packets; - A_UINT32 eapol_logoff_packets; - A_UINT32 eapol_encap_asf_packets; + A_UINT32 m1_packets; + A_UINT32 m2_packets; + A_UINT32 m3_packets; + A_UINT32 m4_packets; + A_UINT32 g1_packets; + A_UINT32 g2_packets; + A_UINT32 rc4_packets; + A_UINT32 eap_packets; + A_UINT32 eapol_start_packets; + A_UINT32 eapol_logoff_packets; + A_UINT32 eapol_encap_asf_packets; } htt_tx_de_eapol_packets_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 ap_bss_peer_not_found; - A_UINT32 ap_bcast_mcast_no_peer; - A_UINT32 sta_delete_in_progress; - A_UINT32 ibss_no_bss_peer; - A_UINT32 invaild_vdev_type; - A_UINT32 invalid_ast_peer_entry; - A_UINT32 peer_entry_invalid; - A_UINT32 ethertype_not_ip; - A_UINT32 eapol_lookup_failed; - A_UINT32 qpeer_not_allow_data; - A_UINT32 fse_tid_override; - A_UINT32 ipv6_jumbogram_zero_length; - A_UINT32 qos_to_non_qos_in_prog; - A_UINT32 ap_bcast_mcast_eapol; - A_UINT32 unicast_on_ap_bss_peer; - A_UINT32 ap_vdev_invalid; - A_UINT32 incomplete_llc; - A_UINT32 eapol_duplicate_m3; - A_UINT32 eapol_duplicate_m4; + A_UINT32 ap_bss_peer_not_found; + A_UINT32 ap_bcast_mcast_no_peer; + A_UINT32 sta_delete_in_progress; + A_UINT32 ibss_no_bss_peer; + A_UINT32 invaild_vdev_type; + A_UINT32 invalid_ast_peer_entry; + A_UINT32 peer_entry_invalid; + A_UINT32 ethertype_not_ip; + A_UINT32 eapol_lookup_failed; + A_UINT32 qpeer_not_allow_data; + A_UINT32 fse_tid_override; + A_UINT32 ipv6_jumbogram_zero_length; + A_UINT32 qos_to_non_qos_in_prog; + A_UINT32 ap_bcast_mcast_eapol; + A_UINT32 unicast_on_ap_bss_peer; + A_UINT32 ap_vdev_invalid; + A_UINT32 incomplete_llc; + A_UINT32 eapol_duplicate_m3; + A_UINT32 eapol_duplicate_m4; } htt_tx_de_classify_failed_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 arp_packets; - A_UINT32 igmp_packets; - A_UINT32 dhcp_packets; - A_UINT32 host_inspected; - A_UINT32 htt_included; - A_UINT32 htt_valid_mcs; - A_UINT32 htt_valid_nss; - A_UINT32 htt_valid_preamble_type; - A_UINT32 htt_valid_chainmask; - A_UINT32 htt_valid_guard_interval; - A_UINT32 htt_valid_retries; - A_UINT32 htt_valid_bw_info; - A_UINT32 htt_valid_power; - A_UINT32 htt_valid_key_flags; - A_UINT32 htt_valid_no_encryption; - A_UINT32 fse_entry_count; - A_UINT32 fse_priority_be; - A_UINT32 fse_priority_high; - A_UINT32 fse_priority_low; - A_UINT32 fse_traffic_ptrn_be; - A_UINT32 fse_traffic_ptrn_over_sub; - A_UINT32 fse_traffic_ptrn_bursty; - A_UINT32 fse_traffic_ptrn_interactive; - A_UINT32 fse_traffic_ptrn_periodic; - A_UINT32 fse_hwqueue_alloc; - A_UINT32 fse_hwqueue_created; - A_UINT32 fse_hwqueue_send_to_host; - A_UINT32 mcast_entry; - A_UINT32 bcast_entry; - A_UINT32 htt_update_peer_cache; - A_UINT32 htt_learning_frame; - A_UINT32 fse_invalid_peer; - /* + A_UINT32 arp_packets; + A_UINT32 igmp_packets; + A_UINT32 dhcp_packets; + A_UINT32 host_inspected; + A_UINT32 htt_included; + A_UINT32 htt_valid_mcs; + A_UINT32 htt_valid_nss; + A_UINT32 htt_valid_preamble_type; + A_UINT32 htt_valid_chainmask; + A_UINT32 htt_valid_guard_interval; + A_UINT32 htt_valid_retries; + A_UINT32 htt_valid_bw_info; + A_UINT32 htt_valid_power; + A_UINT32 htt_valid_key_flags; + A_UINT32 htt_valid_no_encryption; + A_UINT32 fse_entry_count; + A_UINT32 fse_priority_be; + A_UINT32 fse_priority_high; + A_UINT32 fse_priority_low; + A_UINT32 fse_traffic_ptrn_be; + A_UINT32 fse_traffic_ptrn_over_sub; + A_UINT32 fse_traffic_ptrn_bursty; + A_UINT32 fse_traffic_ptrn_interactive; + A_UINT32 fse_traffic_ptrn_periodic; + A_UINT32 fse_hwqueue_alloc; + A_UINT32 fse_hwqueue_created; + A_UINT32 fse_hwqueue_send_to_host; + A_UINT32 mcast_entry; + A_UINT32 bcast_entry; + A_UINT32 htt_update_peer_cache; + A_UINT32 htt_learning_frame; + A_UINT32 fse_invalid_peer; + /** * mec_notify is HTT TX WBM multicast echo check notification * from firmware to host. FW sends SA addresses to host for all * multicast/broadcast packets received on STA side. @@ -3130,37 +3416,37 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 eok; - A_UINT32 classify_done; - A_UINT32 lookup_failed; - A_UINT32 send_host_dhcp; - A_UINT32 send_host_mcast; - A_UINT32 send_host_unknown_dest; - A_UINT32 send_host; - A_UINT32 status_invalid; + A_UINT32 eok; + A_UINT32 classify_done; + A_UINT32 lookup_failed; + A_UINT32 send_host_dhcp; + A_UINT32 send_host_mcast; + A_UINT32 send_host_unknown_dest; + A_UINT32 send_host; + A_UINT32 status_invalid; } htt_tx_de_classify_status_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 enqueued_pkts; - A_UINT32 to_tqm; - A_UINT32 to_tqm_bypass; + A_UINT32 enqueued_pkts; + A_UINT32 to_tqm; + A_UINT32 to_tqm_bypass; } htt_tx_de_enqueue_packets_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 discarded_pkts; - A_UINT32 local_frames; - A_UINT32 is_ext_msdu; + A_UINT32 discarded_pkts; + A_UINT32 local_frames; + A_UINT32 is_ext_msdu; } htt_tx_de_enqueue_discard_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 tcl_dummy_frame; - A_UINT32 tqm_dummy_frame; - A_UINT32 tqm_notify_frame; - A_UINT32 fw2wbm_enq; - A_UINT32 tqm_bypass_frame; + A_UINT32 tcl_dummy_frame; + A_UINT32 tqm_dummy_frame; + A_UINT32 tqm_notify_frame; + A_UINT32 fw2wbm_enq; + A_UINT32 tqm_bypass_frame; } htt_tx_de_compl_stats_tlv; #define HTT_TX_DE_CMN_STATS_MAC_ID_M 0x000000ff @@ -3195,7 +3481,8 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* BIT [ 7 : 0] :- mac_id + /** + * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ A_UINT32 mac_id__word; @@ -3219,7 +3506,9 @@ typedef struct { /* Rx debug info for status rings */ typedef struct { htt_tlv_hdr_t tlv_hdr; - /* BIT [15 : 0] :- max possible number of entries in respective ring (size of the ring in terms of entries) + /** + * BIT [15 : 0] :- max possible number of entries in respective ring + * (size of the ring in terms of entries) * BIT [16 : 31] :- current number of entries occupied in respective ring */ A_UINT32 entry_status_sw2rxdma; @@ -3228,16 +3517,16 @@ typedef struct { A_UINT32 entry_status_reo2sw4; A_UINT32 entry_status_refillringipa; A_UINT32 entry_status_refillringhost; - /* datarate - Moving Average of Number of Entries */ + /** datarate - Moving Average of Number of Entries */ A_UINT32 datarate_refillringipa; A_UINT32 datarate_refillringhost; - /* + /** * refillringhost_backpress_hist and refillringipa_backpress_hist are * deprecated, and will be filled with 0x0 by the target. */ A_UINT32 refillringhost_backpress_hist[3]; A_UINT32 refillringipa_backpress_hist[3]; - /* reo2sw4ringipa_backpress_hist: + /** * Number of times reo2sw4(IPA_DEST_RING) ring is back-pressured * in recent time periods * element 0: in last 0 to 250ms @@ -3388,24 +3677,30 @@ typedef struct { #define HTT_STATS_HIGH_WM_BINS 5 typedef struct { - A_UINT32 base_addr; /* DWORD aligned base memory address of the ring */ + /** DWORD aligned base memory address of the ring */ + A_UINT32 base_addr; - A_UINT32 elem_size; /* size of each ring element */ + /** size of each ring element */ + A_UINT32 elem_size; - /* BIT [15 : 0] :- num_elems + /** + * BIT [15 : 0] :- num_elems * BIT [31 : 16] :- prefetch_tail_idx */ A_UINT32 num_elems__prefetch_tail_idx; - /* BIT [15 : 0] :- head_idx + /** + * BIT [15 : 0] :- head_idx * BIT [31 : 16] :- tail_idx */ A_UINT32 head_idx__tail_idx; - /* BIT [15 : 0] :- shadow_head_idx + /** + * BIT [15 : 0] :- shadow_head_idx * BIT [31 : 16] :- shadow_tail_idx */ A_UINT32 shadow_head_idx__shadow_tail_idx; A_UINT32 num_tail_incr; - /* BIT [15 : 0] :- lwm_thresh + /** + * BIT [15 : 0] :- lwm_thresh * BIT [31 : 16] :- hwm_thresh */ A_UINT32 lwm_thresh__hwm_thresh; @@ -3413,8 +3708,8 @@ typedef struct { A_UINT32 underrun_hit_count; A_UINT32 prod_blockwait_count; A_UINT32 cons_blockwait_count; - A_UINT32 low_wm_hit_count[HTT_STATS_LOW_WM_BINS]; /* FIX THIS: explain what each array element is for */ - A_UINT32 high_wm_hit_count[HTT_STATS_HIGH_WM_BINS]; /* FIX THIS: explain what each array element is for */ + A_UINT32 low_wm_hit_count[HTT_STATS_LOW_WM_BINS]; + A_UINT32 high_wm_hit_count[HTT_STATS_HIGH_WM_BINS]; } htt_ring_if_stats_tlv; #define HTT_RING_IF_CMN_MAC_ID_M 0x000000ff @@ -3433,7 +3728,8 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* BIT [ 7 : 0] :- mac_id + /** + * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ A_UINT32 mac_id__word; @@ -3452,7 +3748,7 @@ typedef struct { */ typedef struct { htt_ring_if_cmn_tlv cmn_tlv; - /* Variable based on the Number of records. */ + /** Variable based on the Number of records. */ struct _ring_if { htt_stats_string_tlv ring_str_tlv; htt_ring_if_stats_tlv ring_tlv; @@ -3466,25 +3762,25 @@ typedef struct { /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - /* Number of DWORDS used per user and per client */ + /** Number of DWORDS used per user and per client */ A_UINT32 dwords_used_by_user_n[1]; } htt_sfm_client_user_tlv_v; typedef struct { htt_tlv_hdr_t tlv_hdr; - /* Client ID */ + /** Client ID */ A_UINT32 client_id; - /* Minimum number of buffers */ + /** Minimum number of buffers */ A_UINT32 buf_min; - /* Maximum number of buffers */ + /** Maximum number of buffers */ A_UINT32 buf_max; - /* Number of Busy buffers */ + /** Number of Busy buffers */ A_UINT32 buf_busy; - /* Number of Allocated buffers */ + /** Number of Allocated buffers */ A_UINT32 buf_alloc; - /* Number of Available/Usable buffers */ + /** Number of Available/Usable buffers */ A_UINT32 buf_avail; - /* Number of users */ + /** Number of users */ A_UINT32 num_users; } htt_sfm_client_tlv; @@ -3504,17 +3800,24 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* BIT [ 7 : 0] :- mac_id + /** + * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ A_UINT32 mac_id__word; - /* Indicates the total number of 128 byte buffers in the CMEM that are available for buffer sharing */ + /** + * Indicates the total number of 128 byte buffers in the CMEM + * that are available for buffer sharing + */ A_UINT32 buf_total; - /* Indicates for certain client or all the clients there is no dowrd saved in SFM, refer to SFM_R1_MEM_EMPTY */ + /** + * Indicates for certain client or all the clients there is no + * dword saved in SFM, refer to SFM_R1_MEM_EMPTY + */ A_UINT32 mem_empty; - /* DEALLOCATE_BUFFERS, refer to register SFM_R0_DEALLOCATE_BUFFERS */ + /** DEALLOCATE_BUFFERS, refer to register SFM_R0_DEALLOCATE_BUFFERS */ A_UINT32 deallocate_bufs; - /* Number of Records */ + /** Number of Records */ A_UINT32 num_records; } htt_sfm_cmn_tlv; @@ -3531,7 +3834,7 @@ typedef struct { */ typedef struct { htt_sfm_cmn_tlv cmn_tlv; - /* Variable based on the Number of records. */ + /** Variable based on the Number of records. */ struct _sfm_client { htt_stats_string_tlv client_str_tlv; htt_sfm_client_tlv client_tlv; @@ -3704,38 +4007,43 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* BIT [ 7 : 0] :- mac_id + /** + * BIT [ 7 : 0] :- mac_id * BIT [15 : 8] :- ring_id * BIT [23 : 16] :- arena 0 -SRING_HRAM, 1 - SRING_HCRAM, 2 - SRING_HW2HW. * BIT [24 : 24] :- EP 0 -consumer, 1 - producer * BIT [31 : 25] :- reserved */ A_UINT32 mac_id__ring_id__arena__ep; - A_UINT32 base_addr_lsb; /* DWORD aligned base memory address of the ring */ + /** DWORD aligned base memory address of the ring */ + A_UINT32 base_addr_lsb; A_UINT32 base_addr_msb; - A_UINT32 ring_size; /* size of ring */ - A_UINT32 elem_size; /* size of each ring element */ + /** size of ring */ + A_UINT32 ring_size; + /** size of each ring element */ + A_UINT32 elem_size; - /* Ring status */ - /* BIT [15 : 0] :- num_avail_words + /** Ring status + * + * BIT [15 : 0] :- num_avail_words * BIT [31 : 16] :- num_valid_words */ A_UINT32 num_avail_words__num_valid_words; - /* Index of head and tail */ - /* BIT [15 : 0] :- head_ptr + /** Index of head and tail + * BIT [15 : 0] :- head_ptr * BIT [31 : 16] :- tail_ptr */ A_UINT32 head_ptr__tail_ptr; - /* Empty or full counter of rings */ - /* BIT [15 : 0] :- consumer_empty + /** Empty or full counter of rings + * BIT [15 : 0] :- consumer_empty * BIT [31 : 16] :- producer_full */ A_UINT32 consumer_empty__producer_full; - /* Prefetch status of consumer ring */ - /* BIT [15 : 0] :- prefetch_count + /** Prefetch status of consumer ring + * BIT [15 : 0] :- prefetch_count * BIT [31 : 16] :- internal_tail_ptr */ A_UINT32 prefetch_count__internal_tail_ptr; @@ -3758,7 +4066,7 @@ typedef struct { */ typedef struct { htt_sring_cmn_tlv cmn_tlv; - /* Variable based on the Number of records. */ + /** Variable based on the Number of records */ struct _sring_stats { htt_stats_string_tlv sring_str_tlv; htt_sring_stats_tlv sring_stats_tlv; @@ -3817,37 +4125,43 @@ typedef enum { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* BIT [ 7 : 0] :- mac_id + /** + * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ A_UINT32 mac_id__word; - /* Number of tx ldpc packets */ + /** Number of tx ldpc packets */ A_UINT32 tx_ldpc; - /* Number of tx rts packets */ + /** Number of tx rts packets */ A_UINT32 rts_cnt; - /* RSSI value of last ack packet (units = dB above noise floor) */ + /** RSSI value of last ack packet (units = dB above noise floor) */ A_UINT32 ack_rssi; A_UINT32 tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; - /* tx_xx_mcs: currently unused */ + /** tx_xx_mcs: currently unused */ A_UINT32 tx_su_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; A_UINT32 tx_mu_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; - A_UINT32 tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; /* element 0,1, ...7 -> NSS 1,2, ...8 */ - A_UINT32 tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ + /* element 0,1, ...7 -> NSS 1,2, ...8 */ + A_UINT32 tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; + /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ + A_UINT32 tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; A_UINT32 tx_stbc[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; A_UINT32 tx_pream[HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES]; - /* Counters to track number of tx packets in each GI (400us, 800us, 1600us & 3200us) in each mcs (0-11) */ + /** + * Counters to track number of tx packets in each GI + * (400us, 800us, 1600us & 3200us) in each mcs (0-11) + */ A_UINT32 tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; - /* Counters to track packets in dcm mcs (MCS 0, 1, 3, 4) */ + /** Counters to track packets in dcm mcs (MCS 0, 1, 3, 4) */ A_UINT32 tx_dcm[HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS]; - /* Number of CTS-acknowledged RTS packets */ + /** Number of CTS-acknowledged RTS packets */ A_UINT32 rts_success; - /* + /** * Counters for legacy 11a and 11b transmissions. * * The index corresponds to: @@ -3860,11 +4174,14 @@ typedef struct { A_UINT32 tx_legacy_cck_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS]; A_UINT32 tx_legacy_ofdm_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; - A_UINT32 ac_mu_mimo_tx_ldpc; /* 11AC VHT DL MU MIMO LDPC count */ - A_UINT32 ax_mu_mimo_tx_ldpc; /* 11AX HE DL MU MIMO LDPC count */ - A_UINT32 ofdma_tx_ldpc; /* 11AX HE DL MU OFDMA LDPC count */ + /** 11AC VHT DL MU MIMO LDPC count */ + A_UINT32 ac_mu_mimo_tx_ldpc; + /** 11AX HE DL MU MIMO LDPC count */ + A_UINT32 ax_mu_mimo_tx_ldpc; + /** 11AX HE DL MU OFDMA LDPC count */ + A_UINT32 ofdma_tx_ldpc; - /* + /** * Counters for 11ax HE LTF selection during TX. * * The index corresponds to: @@ -3873,32 +4190,32 @@ typedef struct { */ A_UINT32 tx_he_ltf[HTT_TX_PDEV_STATS_NUM_LTF]; - /* 11AC VHT DL MU MIMO TX MCS stats */ + /** 11AC VHT DL MU MIMO TX MCS stats */ A_UINT32 ac_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; - /* 11AX HE DL MU MIMO TX MCS stats */ + /** 11AX HE DL MU MIMO TX MCS stats */ A_UINT32 ax_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; - /* 11AX HE DL MU OFDMA TX MCS stats */ + /** 11AX HE DL MU OFDMA TX MCS stats */ A_UINT32 ofdma_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; - /* 11AC VHT DL MU MIMO TX NSS stats (Indicates NSS for individual users) */ + /** 11AC VHT DL MU MIMO TX NSS stats (Indicates NSS for individual users) */ A_UINT32 ac_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; - /* 11AX HE DL MU MIMO TX NSS stats (Indicates NSS for individual users) */ + /** 11AX HE DL MU MIMO TX NSS stats (Indicates NSS for individual users) */ A_UINT32 ax_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; - /* 11AX HE DL MU OFDMA TX NSS stats (Indicates NSS for individual users) */ + /** 11AX HE DL MU OFDMA TX NSS stats (Indicates NSS for individual users) */ A_UINT32 ofdma_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; - /* 11AC VHT DL MU MIMO TX BW stats */ + /** 11AC VHT DL MU MIMO TX BW stats */ A_UINT32 ac_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; - /* 11AX HE DL MU MIMO TX BW stats */ + /** 11AX HE DL MU MIMO TX BW stats */ A_UINT32 ax_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; - /* 11AX HE DL MU OFDMA TX BW stats */ + /** 11AX HE DL MU OFDMA TX BW stats */ A_UINT32 ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; - /* 11AC VHT DL MU MIMO TX guard interval stats */ + /** 11AC VHT DL MU MIMO TX guard interval stats */ A_UINT32 ac_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; - /* 11AX HE DL MU MIMO TX guard interval stats */ + /** 11AX HE DL MU MIMO TX guard interval stats */ A_UINT32 ax_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; - /* 11AX HE DL MU OFDMA TX guard interval stats */ + /** 11AX HE DL MU OFDMA TX guard interval stats */ A_UINT32 ofdma_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; A_UINT32 trigger_type_11ax[HTT_TX_PDEV_STATS_NUM_11AX_TRIGGER_TYPES]; A_UINT32 tx_11ax_su_ext; @@ -3907,13 +4224,13 @@ typedef struct { A_UINT32 tx_mcs_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; A_UINT32 tx_stbc_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; A_UINT32 tx_gi_ext[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; - /* 11AX VHT DL MU MIMO extended TX MCS stats for MCS 12/13 */ + /** 11AX VHT DL MU MIMO extended TX MCS stats for MCS 12/13 */ A_UINT32 ax_mu_mimo_tx_mcs_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; - /* 11AX VHT DL MU OFDMA extended TX MCS stats for MCS 12/13 */ + /** 11AX VHT DL MU OFDMA extended TX MCS stats for MCS 12/13 */ A_UINT32 ofdma_tx_mcs_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; - /* 11AX VHT DL MU MIMO extended TX guard interval stats for MCS 12/13 */ + /** 11AX VHT DL MU MIMO extended TX guard interval stats for MCS 12/13 */ A_UINT32 ax_mu_mimo_tx_gi_ext[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; - /* 11AX VHT DL MU OFDMA extended TX guard interval stats for MCS 12/13 */ + /** 11AX VHT DL MU OFDMA extended TX guard interval stats for MCS 12/13 */ A_UINT32 ofdma_tx_gi_ext[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; /* Stats for MCS 14/15 */ A_UINT32 tx_mcs_ext_2[HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; @@ -3921,45 +4238,49 @@ typedef struct { A_UINT32 tx_gi_ext_2[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; A_UINT32 tx_su_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; A_UINT32 reduced_tx_bw[HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; - /* 11AC VHT DL MU MIMO TX BW stats at reduced channel config */ + /** 11AC VHT DL MU MIMO TX BW stats at reduced channel config */ A_UINT32 reduced_ac_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; - /* 11AX HE DL MU MIMO TX BW stats at reduced channel config */ + /** 11AX HE DL MU MIMO TX BW stats at reduced channel config */ A_UINT32 reduced_ax_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; - /* 11AX HE DL MU OFDMA TX BW stats at reduced channel config */ + /** 11AX HE DL MU OFDMA TX BW stats at reduced channel config */ A_UINT32 reduced_ax_mu_ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; } htt_tx_pdev_rate_stats_tlv; typedef struct { /* 11be mode pdev rate stats; placed in a separate TLV to adhere to size restrictions */ htt_tlv_hdr_t tlv_hdr; - /* 11BE EHT DL MU MIMO TX MCS stats */ + /** 11BE EHT DL MU MIMO TX MCS stats */ A_UINT32 be_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; - /* 11BE EHT DL MU MIMO TX NSS stats (Indicates NSS for individual users) */ + /** 11BE EHT DL MU MIMO TX NSS stats (Indicates NSS for individual users) */ A_UINT32 be_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; - /* 11BE EHT DL MU MIMO TX BW stats */ + /** 11BE EHT DL MU MIMO TX BW stats */ A_UINT32 be_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BE_BW_COUNTERS]; - /* 11BE EHT DL MU MIMO TX guard interval stats */ + /** 11BE EHT DL MU MIMO TX guard interval stats */ A_UINT32 be_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; - /* 11BE DL MU MIMO LDPC count */ + /** 11BE DL MU MIMO LDPC count */ A_UINT32 be_mu_mimo_tx_ldpc; } htt_tx_pdev_rate_stats_be_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - /* BIT [ 7 : 0] :- mac_id + /** + * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ A_UINT32 mac_id__word; - A_UINT32 be_ofdma_tx_ldpc; /* 11BE EHT DL MU OFDMA LDPC count */ - /* 11BE EHT DL MU OFDMA TX MCS stats */ + /** 11BE EHT DL MU OFDMA LDPC count */ + A_UINT32 be_ofdma_tx_ldpc; + /** 11BE EHT DL MU OFDMA TX MCS stats */ A_UINT32 be_ofdma_tx_mcs[HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; - /* 11BE EHT DL MU OFDMA TX NSS stats (Indicates NSS for individual users) */ + /** + * 11BE EHT DL MU OFDMA TX NSS stats (Indicates NSS for individual users) + */ A_UINT32 be_ofdma_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; - /* 11BE EHT DL MU OFDMA TX BW stats */ + /** 11BE EHT DL MU OFDMA TX BW stats */ A_UINT32 be_ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_BE_BW_COUNTERS]; - /* 11BE EHT DL MU OFDMA TX guard interval stats */ + /** 11BE EHT DL MU OFDMA TX guard interval stats */ A_UINT32 be_ofdma_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; } htt_tx_pdev_rate_stats_be_ofdma_tlv; @@ -4067,31 +4388,39 @@ typedef enum { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* BIT [ 7 : 0] :- mac_id + /** + * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ A_UINT32 mac_id__word; A_UINT32 nsts; - /* Number of rx ldpc packets */ + /** Number of rx ldpc packets */ A_UINT32 rx_ldpc; - /* Number of rx rts packets */ + /** Number of rx rts packets */ A_UINT32 rts_cnt; - A_UINT32 rssi_mgmt; /* units = dB above noise floor */ - A_UINT32 rssi_data; /* units = dB above noise floor */ - A_UINT32 rssi_comb; /* units = dB above noise floor */ + /** units = dB above noise floor */ + A_UINT32 rssi_mgmt; + /** units = dB above noise floor */ + A_UINT32 rssi_data; + /** units = dB above noise floor */ + A_UINT32 rssi_comb; A_UINT32 rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; - A_UINT32 rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; /* element 0,1, ...7 -> NSS 1,2, ...8 */ + /** element 0,1, ...7 -> NSS 1,2, ...8 */ + A_UINT32 rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; A_UINT32 rx_dcm[HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS]; A_UINT32 rx_stbc[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; - A_UINT32 rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ + /** element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ + A_UINT32 rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; A_UINT32 rx_pream[HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES]; - A_UINT8 rssi_chain[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; /* units = dB above noise floor */ + /** units = dB above noise floor */ + A_UINT8 rssi_chain[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; - /* Counters to track number of rx packets in each GI in each mcs (0-11) */ + /** Counters to track number of rx packets in each GI in each mcs (0-11) */ A_UINT32 rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; - A_INT32 rssi_in_dbm; /* rx Signal Strength value in dBm unit */ + /** rx Signal Strength value in dBm unit */ + A_INT32 rssi_in_dbm; A_UINT32 rx_11ax_su_ext; A_UINT32 rx_11ac_mumimo; @@ -4103,42 +4432,58 @@ typedef struct { A_UINT32 rx_active_dur_us_low; A_UINT32 rx_active_dur_us_high; - /* number of times UL MU MIMO RX packets received */ + /** number of times UL MU MIMO RX packets received */ A_UINT32 rx_11ax_ul_ofdma; - /* 11AX HE UL OFDMA RX TB PPDU MCS stats */ + /** 11AX HE UL OFDMA RX TB PPDU MCS stats */ A_UINT32 ul_ofdma_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; - /* 11AX HE UL OFDMA RX TB PPDU GI stats */ + /** 11AX HE UL OFDMA RX TB PPDU GI stats */ A_UINT32 ul_ofdma_rx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; - /* 11AX HE UL OFDMA RX TB PPDU NSS stats (Increments the individual user NSS in the OFDMA PPDU received) */ + /** + * 11AX HE UL OFDMA RX TB PPDU NSS stats + * (Increments the individual user NSS in the OFDMA PPDU received) + */ A_UINT32 ul_ofdma_rx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; - /* 11AX HE UL OFDMA RX TB PPDU BW stats */ + /** 11AX HE UL OFDMA RX TB PPDU BW stats */ A_UINT32 ul_ofdma_rx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; - /* Number of times UL OFDMA TB PPDUs received with stbc */ + /** Number of times UL OFDMA TB PPDUs received with stbc */ A_UINT32 ul_ofdma_rx_stbc; - /* Number of times UL OFDMA TB PPDUs received with ldpc */ + /** Number of times UL OFDMA TB PPDUs received with ldpc */ A_UINT32 ul_ofdma_rx_ldpc; - /* Number of non data PPDUs received for each degree (number of users) in UL OFDMA */ + /** + * Number of non data PPDUs received for each degree (number of users) + * in UL OFDMA + */ A_UINT32 rx_ulofdma_non_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; - /* Number of data ppdus received for each degree (number of users) in UL OFDMA */ + /** + * Number of data ppdus received for each degree (number of users) + * in UL OFDMA + */ A_UINT32 rx_ulofdma_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; - /* Number of mpdus passed for each degree (number of users) in UL OFDMA TB PPDU */ + /** + * Number of mpdus passed for each degree (number of users) + * in UL OFDMA TB PPDU + */ A_UINT32 rx_ulofdma_mpdu_ok[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; - /* Number of mpdus failed for each degree (number of users) in UL OFDMA TB PPDU */ + /** + * Number of mpdus failed for each degree (number of users) + * in UL OFDMA TB PPDU + */ A_UINT32 rx_ulofdma_mpdu_fail[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; A_UINT32 nss_count; A_UINT32 pilot_count; - /* RxEVM stats in dB */ + /** RxEVM stats in dB */ A_INT32 rx_pilot_evm_dB[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_PER_NSS]; - /* rx_pilot_evm_dB_mean: + /** * EVM mean across pilots, computed as * mean(10*log10(rx_pilot_evm_linear)) = mean(rx_pilot_evm_dB) */ A_INT32 rx_pilot_evm_dB_mean[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; - A_INT8 rx_ul_fd_rssi[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* dBm units */ - /* per_chain_rssi_pkt_type: + /** dBm units */ + A_INT8 rx_ul_fd_rssi[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; + /** per_chain_rssi_pkt_type: * This field shows what type of rx frame the per-chain RSSI was computed * on, by recording the frame type and sub-type as bit-fields within this * field: @@ -4156,17 +4501,35 @@ typedef struct { A_UINT32 rx_11ax_dl_ofdma_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; A_UINT32 rx_11ax_dl_ofdma_ru[HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS]; - /* Number of non data ppdus received for each degree (number of users) with UL MUMIMO */ + /** + * Number of non data ppdus received for each degree (number of users) + * with UL MUMIMO + */ A_UINT32 rx_ulmumimo_non_data_ppdu[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; - /* Number of data ppdus received for each degree (number of users) with UL MUMIMO */ + /** + * Number of data ppdus received for each degree (number of users) + * with UL MUMIMO + */ A_UINT32 rx_ulmumimo_data_ppdu[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; - /* Number of mpdus passed for each degree (number of users) with UL MUMIMO TB PPDU */ + /** + * Number of mpdus passed for each degree (number of users) + * with UL MUMIMO TB PPDU + */ A_UINT32 rx_ulmumimo_mpdu_ok[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; - /* Number of mpdus failed for each degree (number of users) with UL MUMIMO TB PPDU */ + /** + * Number of mpdus failed for each degree (number of users) + * with UL MUMIMO TB PPDU + */ A_UINT32 rx_ulmumimo_mpdu_fail[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; - /* Number of non data ppdus received for each degree (number of users) in UL OFDMA */ + /** + * Number of non data ppdus received for each degree (number of users) + * in UL OFDMA + */ A_UINT32 rx_ulofdma_non_data_nusers[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; - /* Number of data ppdus received for each degree (number of users) in UL OFDMA */ + /** + * Number of data ppdus received for each degree (number of users) + *in UL OFDMA + */ A_UINT32 rx_ulofdma_data_nusers[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* @@ -4192,10 +4555,13 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT8 rssi_chain_ext[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS]; /* units = dB above noise floor */ + /** units = dB above noise floor */ + A_UINT8 rssi_chain_ext[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS]; A_INT8 rx_per_chain_rssi_ext_in_dbm[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS]; - A_INT32 rssi_mcast_in_dbm; /* rx mcast signal strength value in dBm unit */ - A_INT32 rssi_mgmt_in_dbm; /* rx mgmt packet signal Strength value in dBm unit */ + /** rx mcast signal strength value in dBm unit */ + A_INT32 rssi_mcast_in_dbm; + /** rx mgmt packet signal Strength value in dBm unit */ + A_INT32 rssi_mgmt_in_dbm; /* * Stats for MCS 0-13 since rx_pdev_rate_stats_tlv cannot be updated, * due to message size limitations. @@ -4246,7 +4612,8 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* BIT [ 7 : 0] :- mac_id + /** + * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ A_UINT32 mac_id__word; @@ -4275,20 +4642,20 @@ typedef struct { * Array acts a circular buffer and holds values for last 5 STAs * in the same order as RX. */ - /* uplink_sta_aid: + /** * STA AID array for identifying which STA the * Target-RSSI / FD-RSSI / pwr headroom stats are for */ A_UINT32 uplink_sta_aid[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; - /* uplink_sta_target_rssi: + /** * Trig Target RSSI for STA AID in same index - UNIT(dBm) */ A_INT32 uplink_sta_target_rssi[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; - /* uplink_sta_fd_rssi: + /** * Trig FD RSSI from STA AID in same index - UNIT(dBm) */ A_INT32 uplink_sta_fd_rssi[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; - /* uplink_sta_power_headroom: + /** * Trig power headroom for STA AID in same idx - UNIT(dB) */ A_UINT32 uplink_sta_power_headroom[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; @@ -4309,7 +4676,8 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* BIT [ 7 : 0] :- mac_id + /** + * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ A_UINT32 mac_id__word; @@ -4328,8 +4696,10 @@ typedef struct { * E.g. PPDUs (data or non data) received in RU26 will be incremented in * array offset 0 and similarly RU52 will be incremented in array offset 1 */ - A_UINT32 be_rx_ulofdma_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS]; /* ppdu level */ - A_UINT32 be_rx_ulofdma_non_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS]; /* ppdu level */ + /** PPDU level */ + A_UINT32 be_rx_ulofdma_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS]; + /** PPDU level */ + A_UINT32 be_rx_ulofdma_non_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS]; /* * These arrays hold Target RSSI (rx power the AP wants), @@ -4338,20 +4708,20 @@ typedef struct { * Array acts a circular buffer and holds values for last 5 STAs * in the same order as RX. */ - /* uplink_sta_aid: + /** * STA AID array for identifying which STA the * Target-RSSI / FD-RSSI / pwr headroom stats are for */ A_UINT32 be_uplink_sta_aid[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; - /* uplink_sta_target_rssi: + /** * Trig Target RSSI for STA AID in same index - UNIT(dBm) */ A_INT32 be_uplink_sta_target_rssi[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; - /* uplink_sta_fd_rssi: + /** * Trig FD RSSI from STA AID in same index - UNIT(dBm) */ A_INT32 be_uplink_sta_fd_rssi[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; - /* uplink_sta_power_headroom: + /** * Trig power headroom for STA AID in same idx - UNIT(dB) */ A_UINT32 be_uplink_sta_power_headroom[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; @@ -4372,10 +4742,14 @@ typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 user_index; - A_UINT32 rx_ulofdma_non_data_ppdu; /* ppdu level */ - A_UINT32 rx_ulofdma_data_ppdu; /* ppdu level */ - A_UINT32 rx_ulofdma_mpdu_ok; /* mpdu level */ - A_UINT32 rx_ulofdma_mpdu_fail; /* mpdu level */ + /** PPDU level */ + A_UINT32 rx_ulofdma_non_data_ppdu; + /** PPDU level */ + A_UINT32 rx_ulofdma_data_ppdu; + /** MPDU level */ + A_UINT32 rx_ulofdma_mpdu_ok; + /** MPDU level */ + A_UINT32 rx_ulofdma_mpdu_fail; A_UINT32 rx_ulofdma_non_data_nusers; A_UINT32 rx_ulofdma_data_nusers; } htt_rx_pdev_ul_ofdma_user_stats_tlv; @@ -4384,20 +4758,28 @@ typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 user_index; - A_UINT32 rx_ulmumimo_non_data_ppdu; /* ppdu level */ - A_UINT32 rx_ulmumimo_data_ppdu; /* ppdu level */ - A_UINT32 rx_ulmumimo_mpdu_ok; /* mpdu level */ - A_UINT32 rx_ulmumimo_mpdu_fail; /* mpdu level */ + /** PPDU level */ + A_UINT32 rx_ulmumimo_non_data_ppdu; + /** PPDU level */ + A_UINT32 rx_ulmumimo_data_ppdu; + /** MPDU level */ + A_UINT32 rx_ulmumimo_mpdu_ok; + /** MPDU level */ + A_UINT32 rx_ulmumimo_mpdu_fail; } htt_rx_pdev_ul_mimo_user_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 user_index; - A_UINT32 be_rx_ulmumimo_non_data_ppdu; /* ppdu level */ - A_UINT32 be_rx_ulmumimo_data_ppdu; /* ppdu level */ - A_UINT32 be_rx_ulmumimo_mpdu_ok; /* mpdu level */ - A_UINT32 be_rx_ulmumimo_mpdu_fail; /* mpdu level */ + /** PPDU level */ + A_UINT32 be_rx_ulmumimo_non_data_ppdu; + /** PPDU level */ + A_UINT32 be_rx_ulmumimo_data_ppdu; + /** MPDU level */ + A_UINT32 be_rx_ulmumimo_mpdu_ok; + /** MPDU level */ + A_UINT32 be_rx_ulmumimo_mpdu_fail; } htt_rx_pdev_be_ul_mimo_user_stats_tlv; /* == RX PDEV/SOC STATS == */ @@ -4405,7 +4787,7 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* + /** * BIT [7:0] :- mac_id * BIT [31:8] :- reserved * @@ -4413,38 +4795,41 @@ typedef struct { */ A_UINT32 mac_id__word; - /* Number of times UL MUMIMO RX packets received */ + /** Number of times UL MUMIMO RX packets received */ A_UINT32 rx_11ax_ul_mumimo; - /* 11AX HE UL MU-MIMO RX TB PPDU MCS stats */ + /** 11AX HE UL MU-MIMO RX TB PPDU MCS stats */ A_UINT32 ul_mumimo_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; - /* + /** * 11AX HE UL MU-MIMO RX GI & LTF stats. * Index 0 indicates 1xLTF + 1.6 msec GI * Index 1 indicates 2xLTF + 1.6 msec GI * Index 2 indicates 4xLTF + 3.2 msec GI */ A_UINT32 ul_mumimo_rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; - /* 11AX HE UL MU-MIMO RX TB PPDU NSS stats (Increments the individual user NSS in the UL MU MIMO PPDU received) */ + /** + * 11AX HE UL MU-MIMO RX TB PPDU NSS stats + * (Increments the individual user NSS in the UL MU MIMO PPDU received) + */ A_UINT32 ul_mumimo_rx_nss[HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; - /* 11AX HE UL MU-MIMO RX TB PPDU BW stats */ + /** 11AX HE UL MU-MIMO RX TB PPDU BW stats */ A_UINT32 ul_mumimo_rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; - /* Number of times UL MUMIMO TB PPDUs received with STBC */ + /** Number of times UL MUMIMO TB PPDUs received with STBC */ A_UINT32 ul_mumimo_rx_stbc; - /* Number of times UL MUMIMO TB PPDUs received with LDPC */ + /** Number of times UL MUMIMO TB PPDUs received with LDPC */ A_UINT32 ul_mumimo_rx_ldpc; /* Stats for MCS 12/13 */ A_UINT32 ul_mumimo_rx_mcs_ext[HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; A_UINT32 ul_mumimo_rx_gi_ext[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; - /* RSSI in dBm for Rx TB PPDUs */ + /** RSSI in dBm for Rx TB PPDUs */ A_INT8 rx_ul_mumimo_chain_rssi_in_dbm[HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_TOTAL_BW_COUNTERS]; - /* Target RSSI programmed in UL MUMIMO triggers (units dBm) */ + /** Target RSSI programmed in UL MUMIMO triggers (units dBm) */ A_INT8 rx_ul_mumimo_target_rssi[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS][HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; - /* FD RSSI measured for Rx UL TB PPDUs (units dBm) */ + /** FD RSSI measured for Rx UL TB PPDUs (units dBm) */ A_INT8 rx_ul_mumimo_fd_rssi[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS][HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; - /* Average pilot EVM measued for RX UL TB PPDU */ + /** Average pilot EVM measued for RX UL TB PPDU */ A_INT8 rx_ulmumimo_pilot_evm_dB_mean[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS][HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; A_UINT32 reduced_ul_mumimo_rx_bw[HTT_RX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; } htt_rx_pdev_ul_mumimo_trig_stats_tlv; @@ -4452,7 +4837,7 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* + /** * BIT [7:0] :- mac_id * BIT [31:8] :- reserved * @@ -4460,34 +4845,37 @@ typedef struct { */ A_UINT32 mac_id__word; - /* Number of times UL MUMIMO RX packets received */ + /** Number of times UL MUMIMO RX packets received */ A_UINT32 rx_11be_ul_mumimo; - /* 11BE EHT UL MU-MIMO RX TB PPDU MCS stats */ + /** 11BE EHT UL MU-MIMO RX TB PPDU MCS stats */ A_UINT32 be_ul_mumimo_rx_mcs[HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; - /* + /** * 11BE EHT UL MU-MIMO RX GI & LTF stats. * Index 0 indicates 1xLTF + 1.6 msec GI * Index 1 indicates 2xLTF + 1.6 msec GI * Index 2 indicates 4xLTF + 3.2 msec GI */ A_UINT32 be_ul_mumimo_rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; - /* 11BE EHT UL MU-MIMO RX TB PPDU NSS stats (Increments the individual user NSS in the UL MU MIMO PPDU received) */ + /** + * 11BE EHT UL MU-MIMO RX TB PPDU NSS stats + * (Increments the individual user NSS in the UL MU MIMO PPDU received) + */ A_UINT32 be_ul_mumimo_rx_nss[HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; - /* 11BE EHT UL MU-MIMO RX TB PPDU BW stats */ + /** 11BE EHT UL MU-MIMO RX TB PPDU BW stats */ A_UINT32 be_ul_mumimo_rx_bw[HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS]; - /* Number of times UL MUMIMO TB PPDUs received with STBC */ + /** Number of times UL MUMIMO TB PPDUs received with STBC */ A_UINT32 be_ul_mumimo_rx_stbc; - /* Number of times UL MUMIMO TB PPDUs received with LDPC */ + /** Number of times UL MUMIMO TB PPDUs received with LDPC */ A_UINT32 be_ul_mumimo_rx_ldpc; - /* RSSI in dBm for Rx TB PPDUs */ + /** RSSI in dBm for Rx TB PPDUs */ A_INT8 be_rx_ul_mumimo_chain_rssi_in_dbm[HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS]; - /* Target RSSI programmed in UL MUMIMO triggers (units dBm) */ + /** Target RSSI programmed in UL MUMIMO triggers (units dBm) */ A_INT8 be_rx_ul_mumimo_target_rssi[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER][HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS]; - /* FD RSSI measured for Rx UL TB PPDUs (units dBm) */ + /** FD RSSI measured for Rx UL TB PPDUs (units dBm) */ A_INT8 be_rx_ul_mumimo_fd_rssi[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER][HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; - /* Average pilot EVM measued for RX UL TB PPDU */ + /** Average pilot EVM measued for RX UL TB PPDU */ A_INT8 be_rx_ulmumimo_pilot_evm_dB_mean[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER][HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; } htt_rx_pdev_ul_mumimo_trig_be_stats_tlv; @@ -4503,30 +4891,33 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* Num Packets received on REO FW ring */ + /** Num Packets received on REO FW ring */ A_UINT32 fw_reo_ring_data_msdu; - /* Num bc/mc packets indicated from fw to host */ + /** Num bc/mc packets indicated from fw to host */ A_UINT32 fw_to_host_data_msdu_bcmc; - /* Num unicast packets indicated from fw to host */ + /** Num unicast packets indicated from fw to host */ A_UINT32 fw_to_host_data_msdu_uc; - /* Num remote buf recycle from offload */ + /** Num remote buf recycle from offload */ A_UINT32 ofld_remote_data_buf_recycle_cnt; - /* Num remote free buf given to offload */ + /** Num remote free buf given to offload */ A_UINT32 ofld_remote_free_buf_indication_cnt; - /* Num unicast packets from local path indicated to host */ + /** Num unicast packets from local path indicated to host */ A_UINT32 ofld_buf_to_host_data_msdu_uc; - /* Num unicast packets from REO indicated to host */ + /** Num unicast packets from REO indicated to host */ A_UINT32 reo_fw_ring_to_host_data_msdu_uc; - /* Num Packets received from WBM SW1 ring */ + /** Num Packets received from WBM SW1 ring */ A_UINT32 wbm_sw_ring_reap; - /* Num packets from WBM forwarded from fw to host via WBM */ + /** Num packets from WBM forwarded from fw to host via WBM */ A_UINT32 wbm_forward_to_host_cnt; - /* Num packets from WBM recycled to target refill ring */ + /** Num packets from WBM recycled to target refill ring */ A_UINT32 wbm_target_recycle_cnt; - /* Total Num of recycled to refill ring, including packets from WBM and REO */ + /** + * Total Num of recycled to refill ring, + * including packets from WBM and REO + */ A_UINT32 target_refill_ring_recycle_cnt; } htt_rx_soc_fw_stats_tlv; @@ -4535,7 +4926,7 @@ typedef struct { /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - /* Num ring empty encountered */ + /** Num ring empty encountered */ A_UINT32 refill_ring_empty_cnt[1]; /* HTT_RX_STATS_REFILL_MAX_RING */ } htt_rx_soc_fw_refill_ring_empty_tlv_v; @@ -4544,7 +4935,7 @@ typedef struct { /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - /* Num total buf refilled from refill ring */ + /** Num total buf refilled from refill ring */ A_UINT32 refill_ring_num_refill[1]; /* HTT_RX_STATS_REFILL_MAX_RING */ } htt_rx_soc_fw_refill_ring_num_refill_tlv_v; @@ -4580,7 +4971,7 @@ typedef enum { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* NOTE: + /** NOTE: * The mapping of RXDMA error types to rxdma_err array elements is HW dependent. * It is expected but not required that the target will provide a rxdma_err element * for each of the htt_rx_rxdma_error_code_enum values, up to but not including @@ -4622,7 +5013,7 @@ typedef enum { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* NOTE: + /** NOTE: * The mapping of REO error types to reo_err array elements is HW dependent. * It is expected but not required that the target will provide a rxdma_err element * for each of the htt_rx_reo_error_code_enum values, up to but not including @@ -4661,113 +5052,114 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* BIT [ 7 : 0] :- mac_id + /** + * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ A_UINT32 mac_id__word; - /* Num PPDU status processed from HW */ + /** Num PPDU status processed from HW */ A_UINT32 ppdu_recvd; - /* Num MPDU across PPDUs with FCS ok */ + /** Num MPDU across PPDUs with FCS ok */ A_UINT32 mpdu_cnt_fcs_ok; - /* Num MPDU across PPDUs with FCS err */ + /** Num MPDU across PPDUs with FCS err */ A_UINT32 mpdu_cnt_fcs_err; - /* Num MSDU across PPDUs */ + /** Num MSDU across PPDUs */ A_UINT32 tcp_msdu_cnt; - /* Num MSDU across PPDUs */ + /** Num MSDU across PPDUs */ A_UINT32 tcp_ack_msdu_cnt; - /* Num MSDU across PPDUs */ + /** Num MSDU across PPDUs */ A_UINT32 udp_msdu_cnt; - /* Num MSDU across PPDUs */ + /** Num MSDU across PPDUs */ A_UINT32 other_msdu_cnt; - /* Num MPDU on FW ring indicated */ + /** Num MPDU on FW ring indicated */ A_UINT32 fw_ring_mpdu_ind; - /* Num MGMT MPDU given to protocol */ + /** Num MGMT MPDU given to protocol */ A_UINT32 fw_ring_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; - /* Num ctrl MPDU given to protocol */ + /** Num ctrl MPDU given to protocol */ A_UINT32 fw_ring_ctrl_subtype[HTT_STATS_SUBTYPE_MAX]; - /* Num mcast data packet received */ + /** Num mcast data packet received */ A_UINT32 fw_ring_mcast_data_msdu; - /* Num broadcast data packet received */ + /** Num broadcast data packet received */ A_UINT32 fw_ring_bcast_data_msdu; - /* Num unicat data packet received */ + /** Num unicast data packet received */ A_UINT32 fw_ring_ucast_data_msdu; - /* Num null data packet received */ + /** Num null data packet received */ A_UINT32 fw_ring_null_data_msdu; - /* Num MPDU on FW ring dropped */ + /** Num MPDU on FW ring dropped */ A_UINT32 fw_ring_mpdu_drop; - /* Num buf indication to offload */ + /** Num buf indication to offload */ A_UINT32 ofld_local_data_ind_cnt; - /* Num buf recycle from offload */ + /** Num buf recycle from offload */ A_UINT32 ofld_local_data_buf_recycle_cnt; - /* Num buf indication to data_rx */ + /** Num buf indication to data_rx */ A_UINT32 drx_local_data_ind_cnt; - /* Num buf recycle from data_rx */ + /** Num buf recycle from data_rx */ A_UINT32 drx_local_data_buf_recycle_cnt; - /* Num buf indication to protocol */ + /** Num buf indication to protocol */ A_UINT32 local_nondata_ind_cnt; - /* Num buf recycle from protocol */ + /** Num buf recycle from protocol */ A_UINT32 local_nondata_buf_recycle_cnt; - /* Num buf fed */ + /** Num buf fed */ A_UINT32 fw_status_buf_ring_refill_cnt; - /* Num ring empty encountered */ + /** Num ring empty encountered */ A_UINT32 fw_status_buf_ring_empty_cnt; - /* Num buf fed */ + /** Num buf fed */ A_UINT32 fw_pkt_buf_ring_refill_cnt; - /* Num ring empty encountered */ + /** Num ring empty encountered */ A_UINT32 fw_pkt_buf_ring_empty_cnt; - /* Num buf fed */ + /** Num buf fed */ A_UINT32 fw_link_buf_ring_refill_cnt; - /* Num ring empty encountered */ + /** Num ring empty encountered */ A_UINT32 fw_link_buf_ring_empty_cnt; - /* Num buf fed */ + /** Num buf fed */ A_UINT32 host_pkt_buf_ring_refill_cnt; - /* Num ring empty encountered */ + /** Num ring empty encountered */ A_UINT32 host_pkt_buf_ring_empty_cnt; - /* Num buf fed */ + /** Num buf fed */ A_UINT32 mon_pkt_buf_ring_refill_cnt; - /* Num ring empty encountered */ + /** Num ring empty encountered */ A_UINT32 mon_pkt_buf_ring_empty_cnt; - /* Num buf fed */ + /** Num buf fed */ A_UINT32 mon_status_buf_ring_refill_cnt; - /* Num ring empty encountered */ + /** Num ring empty encountered */ A_UINT32 mon_status_buf_ring_empty_cnt; - /* Num buf fed */ + /** Num buf fed */ A_UINT32 mon_desc_buf_ring_refill_cnt; - /* Num ring empty encountered */ + /** Num ring empty encountered */ A_UINT32 mon_desc_buf_ring_empty_cnt; - /* Num buf fed */ + /** Num buf fed */ A_UINT32 mon_dest_ring_update_cnt; - /* Num ring full encountered */ + /** Num ring full encountered */ A_UINT32 mon_dest_ring_full_cnt; - /* Num rx suspend is attempted */ + /** Num rx suspend is attempted */ A_UINT32 rx_suspend_cnt; - /* Num rx suspend failed */ + /** Num rx suspend failed */ A_UINT32 rx_suspend_fail_cnt; - /* Num rx resume attempted */ + /** Num rx resume attempted */ A_UINT32 rx_resume_cnt; - /* Num rx resume failed */ + /** Num rx resume failed */ A_UINT32 rx_resume_fail_cnt; - /* Num rx ring switch */ + /** Num rx ring switch */ A_UINT32 rx_ring_switch_cnt; - /* Num rx ring restore */ + /** Num rx ring restore */ A_UINT32 rx_ring_restore_cnt; - /* Num rx flush issued */ + /** Num rx flush issued */ A_UINT32 rx_flush_cnt; - /* Num rx recovery */ + /** Num rx recovery */ A_UINT32 rx_recovery_reset_cnt; } htt_rx_pdev_fw_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - /* peer mac address */ + /** peer mac address */ htt_mac_addr peer_mac_addr; - /* Num of tx mgmt frames with subtype on peer level */ + /** Num of tx mgmt frames with subtype on peer level */ A_UINT32 peer_tx_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; - /* Num of rx mgmt frames with subtype on peer level */ + /** Num of rx mgmt frames with subtype on peer level */ A_UINT32 peer_rx_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; } htt_peer_ctrl_path_txrx_stats_tlv; @@ -4776,13 +5168,14 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* BIT [ 7 : 0] :- mac_id + /** + * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ A_UINT32 mac_id__word; - /* Num of phy err */ + /** Num of phy err */ A_UINT32 total_phy_err_cnt; - /* Counts of different types of phy errs + /** Counts of different types of phy errs * The mapping of PHY error types to phy_err array elements is HW dependent. * The only currently-supported mapping is shown below: * @@ -4838,7 +5231,7 @@ typedef struct { /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - /* Num error MPDU for each RxDMA error type */ + /** Num error MPDU for each RxDMA error type */ A_UINT32 fw_ring_mpdu_err[1]; /* HTT_RX_STATS_RXDMA_MAX_ERR */ } htt_rx_pdev_fw_ring_mpdu_err_tlv_v; @@ -4847,7 +5240,7 @@ typedef struct { /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - /* Num MPDU dropped */ + /** Num MPDU dropped */ A_UINT32 fw_mpdu_drop[1]; /* HTT_RX_STATS_FW_DROP_REASON_MAX */ } htt_rx_pdev_fw_mpdu_drop_tlv_v; @@ -4911,13 +5304,13 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* The channel number on which these stats were collected */ + /** The channel number on which these stats were collected */ A_UINT32 chan_num; - /* num of CCA records (Num of htt_pdev_stats_cca_counters_tlv)*/ + /** num of CCA records (Num of htt_pdev_stats_cca_counters_tlv)*/ A_UINT32 num_records; - /* + /** * Bit map of valid CCA counters * Bit0 - tx_frame_usec * Bit1 - rx_frame_usec @@ -4932,7 +5325,7 @@ typedef struct { */ A_UINT32 valid_cca_counters_bitmap; - /* Indicates the stats collection interval + /** Indicates the stats collection interval * Valid Values: * 100 - For the 100ms interval CCA stats histogram * 1000 - For 1sec interval CCA histogram @@ -4953,13 +5346,13 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* The channel number on which these stats were collected */ + /** The channel number on which these stats were collected */ A_UINT32 chan_num; - /* num of CCA records (Num of htt_pdev_stats_cca_counters_tlv)*/ + /** num of CCA records (Num of htt_pdev_stats_cca_counters_tlv)*/ A_UINT32 num_records; - /* + /** * Bit map of valid CCA counters * Bit0 - tx_frame_usec * Bit1 - rx_frame_usec @@ -4974,7 +5367,7 @@ typedef struct { */ A_UINT32 valid_cca_counters_bitmap; - /* Indicates the stats collection interval + /** Indicates the stats collection interval * Valid Values: * 100 - For the 100ms interval CCA stats histogram * 1000 - For 1sec interval CCA histogram @@ -5052,7 +5445,11 @@ typedef struct { A_UINT32 vdev_id; htt_mac_addr peer_mac; A_UINT32 flow_id_flags; - A_UINT32 dialog_id; /* TWT_DIALOG_ID_UNAVAILABLE is used when TWT session is not initiated by host */ + /** + * TWT_DIALOG_ID_UNAVAILABLE is used when TWT session is + * not initiated by host + */ + A_UINT32 dialog_id; A_UINT32 wake_dura_us; A_UINT32 wake_intvl_us; A_UINT32 sp_offset_us; @@ -5102,25 +5499,25 @@ typedef enum { typedef struct { htt_tlv_hdr_t tlv_hdr; /* Variable based on the Number of records. HTT_RX_REO_RESOURCE_STATS_MAX */ - /* htt_rx_reo_debug_sample_id_enum */ + /** htt_rx_reo_debug_sample_id_enum */ A_UINT32 sample_id; - /* Max value of all samples */ + /** Max value of all samples */ A_UINT32 total_max; - /* Average value of total samples */ + /** Average value of total samples */ A_UINT32 total_avg; - /* Num of samples including both zeros and non zeros ones*/ + /** Num of samples including both zeros and non zeros ones*/ A_UINT32 total_sample; - /* Average value of all non zeros samples */ + /** Average value of all non zeros samples */ A_UINT32 non_zeros_avg; - /* Num of non zeros samples */ + /** Num of non zeros samples */ A_UINT32 non_zeros_sample; - /* Max value of last N non zero samples (N = last_non_zeros_sample) */ + /** Max value of last N non zero samples (N = last_non_zeros_sample) */ A_UINT32 last_non_zeros_max; - /* Min value of last N non zero samples (N = last_non_zeros_sample) */ + /** Min value of last N non zero samples (N = last_non_zeros_sample) */ A_UINT32 last_non_zeros_min; - /* Average value of last N non zero samples (N = last_non_zeros_sample) */ + /** Average value of last N non zero samples (N = last_non_zeros_sample) */ A_UINT32 last_non_zeros_avg; - /* Num of last non zero samples */ + /** Num of last non zero samples */ A_UINT32 last_non_zeros_sample; } htt_rx_reo_resource_stats_tlv_v; @@ -5173,7 +5570,7 @@ typedef struct { A_UINT32 cbf_40[HTT_TXBF_MAX_NUM_OF_MODES]; A_UINT32 cbf_80[HTT_TXBF_MAX_NUM_OF_MODES]; A_UINT32 cbf_160[HTT_TXBF_MAX_NUM_OF_MODES]; - /* + /** * The sounding array is a 2-D array stored as an 1-D array of * A_UINT32. The stats for a particular user/bw combination is * referenced with the following: @@ -5211,9 +5608,9 @@ typedef struct { A_UINT32 cv_in_use_cnt_exceeded; A_UINT32 cv_found; A_UINT32 cv_not_found; - /* Sounding per user in 320MHz bandwidth */ + /** Sounding per user in 320MHz bandwidth */ A_UINT32 sounding_320[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; - /* Counts number of soundings for all steering modes in 320MHz bandwidth */ + /** Counts number of soundings for all steering modes in 320MHz bandwidth */ A_UINT32 cbf_320[HTT_TXBF_MAX_NUM_OF_MODES]; } htt_tx_sounding_stats_tlv; @@ -5234,7 +5631,7 @@ typedef struct { A_UINT32 num_obss_tx_ppdu_success; A_UINT32 num_obss_tx_ppdu_failure; - /* num_sr_tx_transmissions: + /** num_sr_tx_transmissions: * Counter of TX done by aborting other BSS RX with spatial reuse * (for cases where rx RSSI from other BSS is below the packet-detection * threshold for doing spatial reuse) @@ -5244,7 +5641,7 @@ typedef struct { A_UINT32 num_sr_tx_tranmissions; /* DEPRECATED - has typo in name */ }; union { - /* + /** * Count the number of times the RSSI from an other-BSS signal * is below the spatial reuse power threshold, thus providing an * opportunity for spatial reuse since OBSS interference will be @@ -5262,7 +5659,7 @@ typedef struct { A_UINT32 num_sr_rx_ge_pd_rssi_thr; }; - /* + /** * Count of number of times OBSS frames were aborted and non-SRG * opportunities were created. Non-SRG opportunities are created when * incoming OBSS RSSI is lesser than the global configured non-SRG RSSI @@ -5270,7 +5667,7 @@ typedef struct { * allow non-SRG TX. */ A_UINT32 num_non_srg_opportunities; - /* + /** * Count of number of times TX PPDU were transmitted using non-SRG * opportunities created. Incoming OBSS frame RSSI is compared with per * PPDU non-SRG RSSI threshold configured in each PPDU. If incoming OBSS @@ -5278,11 +5675,11 @@ typedef struct { * tranmission happens. */ A_UINT32 num_non_srg_ppdu_tried; - /* + /** * Count of number of times non-SRG based TX transmissions were successful */ A_UINT32 num_non_srg_ppdu_success; - /* + /** * Count of number of times OBSS frames were aborted and SRG opportunities * were created. Srg opportunities are created when incoming OBSS RSSI * is less than the global configured SRG RSSI threshold and SRC OBSS @@ -5290,7 +5687,7 @@ typedef struct { * registers allow SRG TX. */ A_UINT32 num_srg_opportunities; - /* + /** * Count of number of times TX PPDU were transmitted using SRG * opportunities created. * Incoming OBSS frame RSSI is compared with per PPDU SRG RSSI @@ -5299,23 +5696,23 @@ typedef struct { * then SRG tranmission happens. */ A_UINT32 num_srg_ppdu_tried; - /* + /** * Count of number of times SRG based TX transmissions were successful */ A_UINT32 num_srg_ppdu_success; - /* + /** * Count of number of times PSR opportunities were created by aborting * OBSS UL OFDMA HE-TB PPDU frame. HE-TB ppdu frames are aborted if the * spatial reuse info in the OBSS trigger common field is set to allow PSR * based spatial reuse. */ A_UINT32 num_psr_opportunities; - /* + /** * Count of number of times TX PPDU were transmitted using PSR * opportunities created. */ A_UINT32 num_psr_ppdu_tried; - /* + /** * Count of number of times PSR based TX transmissions were successful. */ A_UINT32 num_psr_ppdu_success; @@ -5335,13 +5732,14 @@ typedef struct { A_UINT32 current_head_idx; A_UINT32 current_tail_idx; A_UINT32 num_htt_msgs_sent; - /* + /** * Time in milliseconds for which the ring has been in * its current backpressure condition */ A_UINT32 backpressure_time_ms; - /* backpressure_hist - histogram showing how many times different degrees - * of backpressure duration occurred: + /** backpressure_hist - + * histogram showing how many times different degrees of backpressure + * duration occurred: * Index 0 indicates the number of times ring was * continously in backpressure state for 100 - 200ms. * Index 1 indicates the number of times ring was @@ -5377,7 +5775,7 @@ typedef struct { #define HTT_INTERRUPTS_LATENCY_PROFILE_MAX_HIST 3 typedef struct { htt_tlv_hdr_t tlv_hdr; - /* print_header: + /** print_header: * This field suggests whether the host should print a header when * displaying the TLV (because this is the first latency_prof_stats * TLV within a series), or if only the TLV contents should be displayed @@ -5385,13 +5783,18 @@ typedef struct { */ A_UINT32 print_header; A_UINT8 latency_prof_name[HTT_STATS_MAX_PROF_STATS_NAME_LEN]; - A_UINT32 cnt; /* number of data values included in the tot sum */ - A_UINT32 min; /* time in us */ - A_UINT32 max; /* time in us */ + /** number of data values included in the tot sum */ + A_UINT32 cnt; + /** time in us */ + A_UINT32 min; + /** time in us */ + A_UINT32 max; A_UINT32 last; - A_UINT32 tot; /* time in us */ - A_UINT32 avg; /* time in us */ - /* hist_intvl: + /** time in us */ + A_UINT32 tot; + /** time in us */ + A_UINT32 avg; + /** hist_intvl: * Histogram interval, i.e. the latency range covered by each * bin of the histogram, in microsecond units. * hist[0] counts how many latencies were between 0 to hist_intvl @@ -5400,15 +5803,17 @@ typedef struct { */ A_UINT32 hist_intvl; A_UINT32 hist[HTT_LATENCY_PROFILE_MAX_HIST]; - A_UINT32 page_fault_max; /* max page faults in any 1 sampling window */ - A_UINT32 page_fault_total; /* summed over all sampling windows */ - /* ignored_latency_count: + /** max page faults in any 1 sampling window */ + A_UINT32 page_fault_max; + /** summed over all sampling windows */ + A_UINT32 page_fault_total; + /** ignored_latency_count: * ignore some of profile latency to avoid avg skewing */ A_UINT32 ignored_latency_count; - /* interrupts_max: max interrupts within any single sampling window */ + /** interrupts_max: max interrupts within any single sampling window */ A_UINT32 interrupts_max; - /* interrupts_hist: histogram of interrupt rate + /** interrupts_hist: histogram of interrupt rate * bin0 contains the number of sampling windows that had 0 interrupts, * bin1 contains the number of sampling windows that had 1-4 interrupts, * bin2 contains the number of sampling windows that had > 4 interrupts @@ -5418,7 +5823,7 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* duration: + /** duration: * Time period over which counts were gathered, units = microseconds. */ A_UINT32 duration; @@ -5431,7 +5836,8 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 prof_enable_cnt; /* count of enabled profiles */ + /** count of enabled profiles */ + A_UINT32 prof_enable_cnt; } htt_latency_prof_cnt_tlv; /* STATS_TYPE : HTT_DBG_EXT_STATS_LATENCY_PROF_STATS @@ -5463,19 +5869,19 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* + /** * Number of times host requested for fse enable/disable */ A_UINT32 fse_enable_cnt; A_UINT32 fse_disable_cnt; - /* + /** * Number of times host requested for fse cache invalidation * individual entries or full cache */ A_UINT32 fse_cache_invalidate_entry_cnt; A_UINT32 fse_full_cache_invalidate_cnt; - /* + /** * Cache hits count will increase if there is a matching flow in the cache * There is no register for cache miss but the number of cache misses can * be calculated as @@ -5520,7 +5926,7 @@ typedef struct { **/ A_UINT32 fse_cache_occupancy_peak_cnt[HTT_RX_MAX_PEAK_OCCUPANCY_INDEX]; A_UINT32 fse_cache_occupancy_curr_cnt[HTT_RX_MAX_CURRENT_OCCUPANCY_INDEX]; - /* + /** * Square stat is sum of squares of cache occupancy to better understand * any variation/deviation within each cache set, over a given time-window. * @@ -5582,31 +5988,31 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* SU TxBF TX MCS stats */ + /** SU TxBF TX MCS stats */ A_UINT32 tx_su_txbf_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; - /* Implicit BF TX MCS stats */ + /** Implicit BF TX MCS stats */ A_UINT32 tx_su_ibf_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; - /* Open loop TX MCS stats */ + /** Open loop TX MCS stats */ A_UINT32 tx_su_ol_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; - /* SU TxBF TX NSS stats */ + /** SU TxBF TX NSS stats */ A_UINT32 tx_su_txbf_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; - /* Implicit BF TX NSS stats */ + /** Implicit BF TX NSS stats */ A_UINT32 tx_su_ibf_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; - /* Open loop TX NSS stats */ + /** Open loop TX NSS stats */ A_UINT32 tx_su_ol_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; - /* SU TxBF TX BW stats */ + /** SU TxBF TX BW stats */ A_UINT32 tx_su_txbf_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; - /* Implicit BF TX BW stats */ + /** Implicit BF TX BW stats */ A_UINT32 tx_su_ibf_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; - /* Open loop TX BW stats */ + /** Open loop TX BW stats */ A_UINT32 tx_su_ol_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; - /* Legacy and OFDM TX rate stats */ + /** Legacy and OFDM TX rate stats */ A_UINT32 tx_legacy_ofdm_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; - /* SU TxBF TX BW stats */ + /** SU TxBF TX BW stats */ A_UINT32 reduced_tx_su_txbf_bw[HTT_TX_TXBF_RATE_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; - /* Implicit BF TX BW stats */ + /** Implicit BF TX BW stats */ A_UINT32 reduced_tx_su_ibf_bw[HTT_TX_TXBF_RATE_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; - /* Open loop TX BW stats */ + /** Open loop TX BW stats */ A_UINT32 reduced_tx_su_ol_bw[HTT_TX_TXBF_RATE_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; } htt_tx_pdev_txbf_rate_stats_tlv; @@ -5625,7 +6031,8 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 rc_mode; /* HTT_STATS_RC_MODE_XX */ + /** HTT_STATS_RC_MODE_XX */ + A_UINT32 rc_mode; A_UINT32 last_probed_mcs; @@ -5654,33 +6061,33 @@ typedef struct { } htt_tx_pdev_per_stats_t; typedef enum { - HTT_ULTRIG_QBOOST_TRIGGER = 0, - HTT_ULTRIG_PSPOLL_TRIGGER, - HTT_ULTRIG_UAPSD_TRIGGER, - HTT_ULTRIG_11AX_TRIGGER, - HTT_ULTRIG_11AX_WILDCARD_TRIGGER, - HTT_ULTRIG_11AX_UNASSOC_WILDCARD_TRIGGER, - HTT_STA_UL_OFDMA_NUM_TRIG_TYPE, + HTT_ULTRIG_QBOOST_TRIGGER = 0, + HTT_ULTRIG_PSPOLL_TRIGGER, + HTT_ULTRIG_UAPSD_TRIGGER, + HTT_ULTRIG_11AX_TRIGGER, + HTT_ULTRIG_11AX_WILDCARD_TRIGGER, + HTT_ULTRIG_11AX_UNASSOC_WILDCARD_TRIGGER, + HTT_STA_UL_OFDMA_NUM_TRIG_TYPE, } HTT_STA_UL_OFDMA_RX_TRIG_TYPE; typedef enum { - HTT_11AX_TRIGGER_BASIC_E = 0, - HTT_11AX_TRIGGER_BRPOLL_E = 1, - HTT_11AX_TRIGGER_MU_BAR_E = 2, - HTT_11AX_TRIGGER_MU_RTS_E = 3, - HTT_11AX_TRIGGER_BUFFER_SIZE_E = 4, - HTT_11AX_TRIGGER_GCR_MU_BAR_E = 5, - HTT_11AX_TRIGGER_BQRP_E = 6, - HTT_11AX_TRIGGER_NDP_FB_REPORT_POLL_E = 7, - HTT_11AX_TRIGGER_RESERVED_8_E = 8, - HTT_11AX_TRIGGER_RESERVED_9_E = 9, - HTT_11AX_TRIGGER_RESERVED_10_E = 10, - HTT_11AX_TRIGGER_RESERVED_11_E = 11, - HTT_11AX_TRIGGER_RESERVED_12_E = 12, - HTT_11AX_TRIGGER_RESERVED_13_E = 13, - HTT_11AX_TRIGGER_RESERVED_14_E = 14, - HTT_11AX_TRIGGER_RESERVED_15_E = 15, - HTT_STA_UL_OFDMA_NUM_11AX_TRIG_TYPE, + HTT_11AX_TRIGGER_BASIC_E = 0, + HTT_11AX_TRIGGER_BRPOLL_E = 1, + HTT_11AX_TRIGGER_MU_BAR_E = 2, + HTT_11AX_TRIGGER_MU_RTS_E = 3, + HTT_11AX_TRIGGER_BUFFER_SIZE_E = 4, + HTT_11AX_TRIGGER_GCR_MU_BAR_E = 5, + HTT_11AX_TRIGGER_BQRP_E = 6, + HTT_11AX_TRIGGER_NDP_FB_REPORT_POLL_E = 7, + HTT_11AX_TRIGGER_RESERVED_8_E = 8, + HTT_11AX_TRIGGER_RESERVED_9_E = 9, + HTT_11AX_TRIGGER_RESERVED_10_E = 10, + HTT_11AX_TRIGGER_RESERVED_11_E = 11, + HTT_11AX_TRIGGER_RESERVED_12_E = 12, + HTT_11AX_TRIGGER_RESERVED_13_E = 13, + HTT_11AX_TRIGGER_RESERVED_14_E = 14, + HTT_11AX_TRIGGER_RESERVED_15_E = 15, + HTT_STA_UL_OFDMA_NUM_11AX_TRIG_TYPE, } HTT_STA_UL_OFDMA_11AX_TRIG_TYPE; /* UL RESP Queues 0 - HIPRI, 1 - LOPRI & 2 - BSR */ @@ -5703,48 +6110,61 @@ typedef struct { A_UINT32 pdev_id; - /* Trigger Type reported by HWSCH on RX reception - * Each index populate enum HTT_STA_UL_OFDMA_RX_TRIG_TYPE */ + /** + * Trigger Type reported by HWSCH on RX reception + * Each index populate enum HTT_STA_UL_OFDMA_RX_TRIG_TYPE + */ A_UINT32 rx_trigger_type[HTT_STA_UL_OFDMA_NUM_TRIG_TYPE]; - /* 11AX Trigger Type on RX reception - * Each index populate enum HTT_STA_UL_OFDMA_11AX_TRIG_TYPE */ + /** + * 11AX Trigger Type on RX reception + * Each index populate enum HTT_STA_UL_OFDMA_11AX_TRIG_TYPE + */ A_UINT32 ax_trigger_type[HTT_STA_UL_OFDMA_NUM_11AX_TRIG_TYPE]; - /* Num data PPDUs/Delims responded to trigs. per HWQ for UL RESP */ + /** Num data PPDUs/Delims responded to trigs. per HWQ for UL RESP */ A_UINT32 num_data_ppdu_responded_per_hwq[HTT_STA_UL_OFDMA_NUM_UL_QUEUES]; A_UINT32 num_null_delimiters_responded_per_hwq[HTT_STA_UL_OFDMA_NUM_UL_QUEUES]; - /* Overall UL STA RESP Status 0 - HE TB PPDU, 1 - NULL Delimiter - * Super set of num_data_ppdu_responded_per_hwq, num_null_delimiters_responded_per_hwq */ + /** + * Overall UL STA RESP Status 0 - HE TB PPDU, 1 - NULL Delimiter + * Super set of num_data_ppdu_responded_per_hwq, + * num_null_delimiters_responded_per_hwq + */ A_UINT32 num_total_trig_responses[HTT_STA_UL_OFDMA_NUM_RESP_END_TYPE]; - /* Time interval between current time ms and last successful trigger RX - * 0xFFFFFFFF denotes no trig received / timestamp roll back */ + /** + * Time interval between current time ms and last successful trigger RX + * 0xFFFFFFFF denotes no trig received / timestamp roll back + */ A_UINT32 last_trig_rx_time_delta_ms; - /* Rate Statistics for UL OFDMA - * UL TB PPDU TX MCS, NSS, GI, BW from STA HWQ */ + /** + * Rate Statistics for UL OFDMA + * UL TB PPDU TX MCS, NSS, GI, BW from STA HWQ + */ A_UINT32 ul_ofdma_tx_mcs[HTT_STA_UL_OFDMA_NUM_MCS_COUNTERS]; A_UINT32 ul_ofdma_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; A_UINT32 ul_ofdma_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_STA_UL_OFDMA_NUM_MCS_COUNTERS]; A_UINT32 ul_ofdma_tx_ldpc; A_UINT32 ul_ofdma_tx_bw[HTT_STA_UL_OFDMA_NUM_BW_COUNTERS]; - /* Trig based PPDU TX/ RBO based PPDU TX Count */ + /** Trig based PPDU TX/ RBO based PPDU TX Count */ A_UINT32 trig_based_ppdu_tx; A_UINT32 rbo_based_ppdu_tx; - /* Switch MU EDCA to SU EDCA Count */ + /** Switch MU EDCA to SU EDCA Count */ A_UINT32 mu_edca_to_su_edca_switch_count; - /* Num MU EDCA applied Count */ + /** Num MU EDCA applied Count */ A_UINT32 num_mu_edca_param_apply_count; - /* Current MU EDCA Parameters for WMM ACs - * Mode - 0 - SU EDCA, 1- MU EDCA */ + /** + * Current MU EDCA Parameters for WMM ACs + * Mode - 0 - SU EDCA, 1- MU EDCA + */ A_UINT32 current_edca_hwq_mode[HTT_NUM_AC_WMM]; - /* Contention Window minimum. Range: 1 - 10 */ + /** Contention Window minimum. Range: 1 - 10 */ A_UINT32 current_cw_min[HTT_NUM_AC_WMM]; - /* Contention Window maximum. Range: 1 - 10 */ + /** Contention Window maximum. Range: 1 - 10 */ A_UINT32 current_cw_max[HTT_NUM_AC_WMM]; - /* AIFS value - 0 -255 */ + /** AIFS value - 0 -255 */ A_UINT32 current_aifs[HTT_NUM_AC_WMM]; A_UINT32 reduced_ul_ofdma_tx_bw[HTT_STA_UL_OFDMA_NUM_REDUCED_CHAN_TYPES][HTT_STA_UL_OFDMA_NUM_BW_COUNTERS]; } htt_sta_ul_ofdma_stats_tlv; @@ -5759,23 +6179,34 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* No of Fine Timing Measurement frames transmitted successfully */ + /** No of Fine Timing Measurement frames transmitted successfully */ A_UINT32 tx_ftm_suc; - /* No of Fine Timing Measurement frames transmitted successfully after retry */ + /** + * No of Fine Timing Measurement frames transmitted successfully + * after retry + */ A_UINT32 tx_ftm_suc_retry; - /* No of Fine Timing Measurement frames not transmitted successfully */ + /** No of Fine Timing Measurement frames not transmitted successfully */ A_UINT32 tx_ftm_fail; - /* No of Fine Timing Measurement Request frames received, including initial, non-initial, and duplicates */ + /** + * No of Fine Timing Measurement Request frames received, + * including initial, non-initial, and duplicates + */ A_UINT32 rx_ftmr_cnt; - /* No of duplicate Fine Timing Measurement Request frames received, including both initial and non-initial */ + /** + * No of duplicate Fine Timing Measurement Request frames received, + * including both initial and non-initial + */ A_UINT32 rx_ftmr_dup_cnt; - /* No of initial Fine Timing Measurement Request frames received */ + /** No of initial Fine Timing Measurement Request frames received */ A_UINT32 rx_iftmr_cnt; - /* No of duplicate initial Fine Timing Measurement Request frames received */ + /** + * No of duplicate initial Fine Timing Measurement Request frames received + */ A_UINT32 rx_iftmr_dup_cnt; - /* No of responder sessions rejected when initiator was active */ + /** No of responder sessions rejected when initiator was active */ A_UINT32 initiator_active_responder_rejected_cnt; - /* Responder terminate count */ + /** Responder terminate count */ A_UINT32 responder_terminate_cnt; A_UINT32 vdev_id; } htt_vdev_rtt_resp_stats_tlv; @@ -5788,15 +6219,25 @@ typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 vdev_id; - /* No of Fine Timing Measurement request frames transmitted successfully */ + /** + * No of Fine Timing Measurement request frames transmitted successfully + */ A_UINT32 tx_ftmr_cnt; - /* No of Fine Timing Measurement request frames not transmitted successfully */ + /** + * No of Fine Timing Measurement request frames not transmitted successfully + */ A_UINT32 tx_ftmr_fail; - /* No of Fine Timing Measurement request frames transmitted successfully after retry */ + /** + * No of Fine Timing Measurement request frames transmitted successfully + * after retry + */ A_UINT32 tx_ftmr_suc_retry; - /* No of Fine Timing Measurement frames received, including initial, non-initial, and duplicates */ + /** + * No of Fine Timing Measurement frames received, including initial, + * non-initial, and duplicates + */ A_UINT32 rx_ftm_cnt; - /* Initiator Terminate count */ + /** Initiator Terminate count */ A_UINT32 initiator_terminate_cnt; } htt_vdev_rtt_init_stats_tlv; @@ -5815,15 +6256,15 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* No of pktlog payloads that were dropped in htt_ppdu_stats path */ + /** No of pktlog payloads that were dropped in htt_ppdu_stats path */ A_UINT32 pktlog_lite_drop_cnt; - /* No of pktlog payloads that were dropped in TQM path */ + /** No of pktlog payloads that were dropped in TQM path */ A_UINT32 pktlog_tqm_drop_cnt; - /* No of pktlog ppdu stats payloads that were dropped */ + /** No of pktlog ppdu stats payloads that were dropped */ A_UINT32 pktlog_ppdu_stats_drop_cnt; - /* No of pktlog ppdu ctrl payloads that were dropped */ + /** No of pktlog ppdu ctrl payloads that were dropped */ A_UINT32 pktlog_ppdu_ctrl_drop_cnt; - /* No of pktlog sw events payloads that were dropped */ + /** No of pktlog sw events payloads that were dropped */ A_UINT32 pktlog_sw_events_drop_cnt; } htt_pktlog_and_htt_ring_stats_tlv; @@ -5916,18 +6357,18 @@ enum { /* dlPagerStats structure * Number of lock/unlock pages with last 10 lock/unlock occurrences are recorded */ typedef struct{ - /* msg_dword_1 bitfields: + /** msg_dword_1 bitfields: * async_lock : 8, * sync_lock : 8, * reserved : 16; */ A_UINT32 msg_dword_1; - /* mst_dword_2 bitfields: + /** mst_dword_2 bitfields: * total_locked_pages : 16, * total_free_pages : 16; */ A_UINT32 msg_dword_2; - /* msg_dword_3 bitfields: + /** msg_dword_3 bitfields: * last_locked_page_idx : 16, * last_unlocked_page_idx : 16; */ @@ -5936,7 +6377,7 @@ typedef struct{ struct { A_UINT32 page_num; A_UINT32 num_of_pages; - /* timestamp is in microsecond units, from SoC timer clock */ + /** timestamp is in microsecond units, from SoC timer clock */ A_UINT32 timestamp_lsbs; A_UINT32 timestamp_msbs; } last_pages_info[HTT_STATS_NUM_PAGE_LOCK_STATES][HTT_DLPAGER_STATS_MAX_HIST]; @@ -6026,40 +6467,40 @@ typedef enum { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* number of RXTD OFDMA OTA error counts except power surge and drop */ + /** number of RXTD OFDMA OTA error counts except power surge and drop */ A_UINT32 rx_ofdma_timing_err_cnt; - /* rx_cck_fail_cnt: + /** rx_cck_fail_cnt: * number of cck error counts due to rx reception failure because of * timing error in cck */ A_UINT32 rx_cck_fail_cnt; - /* number of times tx abort initiated by mac */ + /** number of times tx abort initiated by mac */ A_UINT32 mactx_abort_cnt; - /* number of times rx abort initiated by mac */ + /** number of times rx abort initiated by mac */ A_UINT32 macrx_abort_cnt; - /* number of times tx abort initiated by phy */ + /** number of times tx abort initiated by phy */ A_UINT32 phytx_abort_cnt; - /* number of times rx abort initiated by phy */ + /** number of times rx abort initiated by phy */ A_UINT32 phyrx_abort_cnt; - /* number of rx defered count initiated by phy */ + /** number of rx defered count initiated by phy */ A_UINT32 phyrx_defer_abort_cnt; - /* number of sizing events generated at LSTF */ + /** number of sizing events generated at LSTF */ A_UINT32 rx_gain_adj_lstf_event_cnt; /* a.k.a sizing1 */ - /* number of sizing events generated at non-legacy LTF */ + /** number of sizing events generated at non-legacy LTF */ A_UINT32 rx_gain_adj_non_legacy_cnt; /* a.k.a sizing2 */ - /* rx_pkt_cnt - + /** rx_pkt_cnt - * Received EOP (end-of-packet) count per packet type; * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax; [5] = GF * [6-7]=RSVD */ A_UINT32 rx_pkt_cnt[HTT_MAX_RX_PKT_CNT]; - /* rx_pkt_crc_pass_cnt - + /** rx_pkt_crc_pass_cnt - * Received EOP (end-of-packet) count per packet type; * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax; [5] = GF * [6-7]=RSVD */ A_UINT32 rx_pkt_crc_pass_cnt[HTT_MAX_RX_PKT_CRC_PASS_CNT]; - /* per_blk_err_cnt - + /** per_blk_err_cnt - * Error count per error source; * [0] = unknown; [1] = LSIG; [2] = HTSIG; [3] = VHTSIG; [4] = HESIG; * [5] = RXTD_OTA; [6] = RXTD_FATAL; [7] = DEMF; [8] = ROBE; @@ -6067,7 +6508,7 @@ typedef struct { * [13-19]=RSVD */ A_UINT32 per_blk_err_cnt[HTT_MAX_PER_BLK_ERR_CNT]; - /* rx_ota_err_cnt - + /** rx_ota_err_cnt - * RXTD OTA (over-the-air) error count per error reason; * [0] = voting fail; [1] = weak det fail; [2] = strong sig fail; * [3] = cck fail; [4] = power surge; [5] = power drop; @@ -6080,76 +6521,76 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* per chain hw noise floor values in dBm */ + /** per chain hw noise floor values in dBm */ A_INT32 nf_chain[HTT_STATS_MAX_CHAINS]; - /* number of false radars detected */ + /** number of false radars detected */ A_UINT32 false_radar_cnt; - /* number of channel switches happened due to radar detection */ + /** number of channel switches happened due to radar detection */ A_UINT32 radar_cs_cnt; - /* ani_level - + /** ani_level - * ANI level (noise interference) corresponds to the channel * the desense levels range from -5 to 15 in dB units, * higher values indicating more noise interference. */ A_INT32 ani_level; - /* running time in minutes since FW boot */ + /** running time in minutes since FW boot */ A_UINT32 fw_run_time; - /* per chain runtime noise floor values in dBm */ + /** per chain runtime noise floor values in dBm */ A_INT32 runTime_nf_chain[HTT_STATS_MAX_CHAINS]; } htt_phy_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - /* current pdev_id */ + /** current pdev_id */ A_UINT32 pdev_id; - /* current channel information */ + /** current channel information */ A_UINT32 chan_mhz; - /* center_freq1, center_freq2 in mhz */ + /** center_freq1, center_freq2 in mhz */ A_UINT32 chan_band_center_freq1; A_UINT32 chan_band_center_freq2; - /* chan_phy_mode - WLAN_PHY_MODE enum type */ + /** chan_phy_mode - WLAN_PHY_MODE enum type */ A_UINT32 chan_phy_mode; - /* chan_flags follows HTT_STATS_CHANNEL_FLAGS enum */ + /** chan_flags follows HTT_STATS_CHANNEL_FLAGS enum */ A_UINT32 chan_flags; - /* channel Num updated to virtual phybase */ + /** channel Num updated to virtual phybase */ A_UINT32 chan_num; - /* Cause for the phy reset - HTT_STATS_RESET_CAUSE */ + /** Cause for the phy reset - HTT_STATS_RESET_CAUSE */ A_UINT32 reset_cause; - /* Cause for the previous phy reset */ + /** Cause for the previous phy reset */ A_UINT32 prev_reset_cause; - /* source for the phywarm reset - HTT_STATS_RESET_CAUSE */ + /** source for the phywarm reset - HTT_STATS_RESET_CAUSE */ A_UINT32 phy_warm_reset_src; - /* rxGain Table selection mode - register settings + /** rxGain Table selection mode - register settings * 0 - Auto, 1/2 - Forced with and without BT override respectively */ A_UINT32 rx_gain_tbl_mode; - /* current xbar value - perchain analog to digital idx mapping */ + /** current xbar value - perchain analog to digital idx mapping */ A_UINT32 xbar_val; - /* Flag to indicate forced calibration */ + /** Flag to indicate forced calibration */ A_UINT32 force_calibration; - /* current RF mode (e.g. SBS/DBS) - follows HTT_STATS_RF_MODE enum */ + /** current RF mode (e.g. SBS/DBS) - follows HTT_STATS_RF_MODE enum */ A_UINT32 phyrf_mode; /* PDL phyInput stats */ - /* homechannel flag + /** homechannel flag * 1- Homechan, 0 - scan channel */ A_UINT32 phy_homechan; - /* Tx and Rx chainmask */ + /** Tx and Rx chainmask */ A_UINT32 phy_tx_ch_mask; A_UINT32 phy_rx_ch_mask; - /* INI masks - to decide the INI registers to be loaded on a reset */ + /** INI masks - to decide the INI registers to be loaded on a reset */ A_UINT32 phybb_ini_mask; A_UINT32 phyrf_ini_mask; - /* DFS,ADFS/Spectral scan enable masks */ + /** DFS,ADFS/Spectral scan enable masks */ A_UINT32 phy_dfs_en_mask; A_UINT32 phy_sscan_en_mask; A_UINT32 phy_synth_sel_mask; A_UINT32 phy_adfs_freq; - /* CCK FIR settings + /** CCK FIR settings * register settings - filter coefficients for Iqs conversion * [31:24] = FIR_COEFF_3_0 * [23:16] = FIR_COEFF_2_0 @@ -6157,21 +6598,23 @@ typedef struct { * [7:0] = FIR_COEFF_0_0 */ A_UINT32 cck_fir_settings; - /* dynamic primary channel index + /** dynamic primary channel index * primary 20MHz channel index on the current channel BW */ A_UINT32 phy_dyn_pri_chan; - /* Current CCA detection threshold + /** + * Current CCA detection threshold * dB above noisefloor req for CCA * Register settings for all subbands */ A_UINT32 cca_thresh; - /* status for dynamic CCA adjustment + /** + * status for dynamic CCA adjustment * 0-disabled, 1-enabled */ A_UINT32 dyn_cca_status; - /* RXDEAF Register value + /** RXDEAF Register value * rxdesense_thresh_sw - VREG Register * rxdesense_thresh_hw - PHY Register */ @@ -6182,19 +6625,19 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; - /* current pdev_id */ + /** current pdev_id */ A_UINT32 pdev_id; - /* ucode PHYOFF pass/failure count */ + /** ucode PHYOFF pass/failure count */ A_UINT32 cf_active_low_fail_cnt; A_UINT32 cf_active_low_pass_cnt; - /* PHYOFF count attempted through ucode VREG */ + /** PHYOFF count attempted through ucode VREG */ A_UINT32 phy_off_through_vreg_cnt; - /* Force calibration count */ + /** Force calibration count */ A_UINT32 force_calibration_cnt; - /* phyoff count during rfmode switch */ + /** phyoff count during rfmode switch */ A_UINT32 rf_mode_switch_phy_off_cnt; } htt_phy_reset_counters_tlv; -- GitLab From 0cf22b44395c5384d19b4f87cc858423afbfa568 Mon Sep 17 00:00:00 2001 From: Kiran Venkatappa Date: Thu, 25 Nov 2021 23:35:01 +0530 Subject: [PATCH 10/42] fw-api: Add headers for qcn9224 Add qcn9224 HW headers corresponding. Change-Id: Iaf2dfc04009ffa82b6dd4a40e796148fa99a5744 CRs-Fixed: 3103719 --- hw/qcn9224/HALcomdef.h | 62 + hw/qcn9224/HALhwio.h | 351 + hw/qcn9224/buffer_addr_info.h | 82 + hw/qcn9224/ce_src_desc.h | 192 + hw/qcn9224/ce_stat_desc.h | 182 + hw/qcn9224/com_dtypes.h | 213 + hw/qcn9224/he_sig_a_mu_dl_info.h | 262 + hw/qcn9224/he_sig_a_su_info.h | 312 + hw/qcn9224/he_sig_b1_mu_info.h | 72 + hw/qcn9224/he_sig_b2_mu_info.h | 152 + hw/qcn9224/he_sig_b2_ofdma_info.h | 152 + hw/qcn9224/ht_sig_info.h | 202 + hw/qcn9224/l_sig_a_info.h | 132 + hw/qcn9224/l_sig_b_info.h | 82 + hw/qcn9224/macrx_abort_request_info.h | 62 + hw/qcn9224/phyrx_abort_request_info.h | 92 + hw/qcn9224/phyrx_he_sig_a_mu_dl.h | 226 + hw/qcn9224/phyrx_he_sig_a_su.h | 266 + hw/qcn9224/phyrx_he_sig_b1_mu.h | 84 + hw/qcn9224/phyrx_he_sig_b2_mu.h | 138 + hw/qcn9224/phyrx_he_sig_b2_ofdma.h | 138 + hw/qcn9224/phyrx_ht_sig.h | 178 + hw/qcn9224/phyrx_l_sig_a.h | 132 + hw/qcn9224/phyrx_l_sig_b.h | 92 + hw/qcn9224/phyrx_location.h | 554 + .../phyrx_other_receive_info_ru_details.h | 84 + hw/qcn9224/phyrx_pkt_end.h | 704 + hw/qcn9224/phyrx_pkt_end_info.h | 732 + hw/qcn9224/phyrx_rssi_legacy.h | 1299 + hw/qcn9224/phyrx_vht_sig_a.h | 194 + hw/qcn9224/receive_rssi_info.h | 682 + hw/qcn9224/receive_user_info.h | 392 + .../reo_descriptor_threshold_reached_status.h | 390 + hw/qcn9224/reo_destination_ring.h | 434 + hw/qcn9224/reo_entrance_ring.h | 382 + hw/qcn9224/reo_flush_cache.h | 244 + hw/qcn9224/reo_flush_cache_status.h | 430 + hw/qcn9224/reo_flush_queue.h | 194 + hw/qcn9224/reo_flush_queue_status.h | 350 + hw/qcn9224/reo_flush_timeout_list.h | 184 + hw/qcn9224/reo_flush_timeout_list_status.h | 370 + hw/qcn9224/reo_get_queue_stats.h | 184 + hw/qcn9224/reo_get_queue_stats_status.h | 460 + hw/qcn9224/reo_unblock_cache.h | 184 + hw/qcn9224/reo_unblock_cache_status.h | 360 + hw/qcn9224/reo_update_rx_reo_queue.h | 624 + hw/qcn9224/reo_update_rx_reo_queue_status.h | 340 + hw/qcn9224/rx_attention.h | 554 + hw/qcn9224/rx_flow_search_entry.h | 322 + hw/qcn9224/rx_location_info.h | 672 + hw/qcn9224/rx_mpdu_desc_info.h | 162 + hw/qcn9224/rx_mpdu_details.h | 182 + hw/qcn9224/rx_mpdu_end.h | 284 + hw/qcn9224/rx_mpdu_info.h | 1250 + hw/qcn9224/rx_mpdu_link_ptr.h | 80 + hw/qcn9224/rx_mpdu_start.h | 1037 + hw/qcn9224/rx_msdu_desc_info.h | 212 + hw/qcn9224/rx_msdu_details.h | 276 + hw/qcn9224/rx_msdu_end.h | 1574 ++ hw/qcn9224/rx_msdu_ext_desc_info.h | 102 + hw/qcn9224/rx_msdu_link.h | 1561 ++ hw/qcn9224/rx_msdu_start.h | 444 + hw/qcn9224/rx_ppdu_end_user_stats.h | 858 + hw/qcn9224/rx_ppdu_end_user_stats_ext.h | 218 + hw/qcn9224/rx_ppdu_start.h | 124 + hw/qcn9224/rx_ppdu_start_user_info.h | 330 + hw/qcn9224/rx_reo_queue.h | 732 + hw/qcn9224/rx_reo_queue_ext.h | 683 + hw/qcn9224/rx_reo_queue_reference.h | 82 + hw/qcn9224/rx_rxpcu_classification_overview.h | 152 + hw/qcn9224/rx_timing_offset_info.h | 62 + hw/qcn9224/rxpcu_ppdu_end_info.h | 1180 + hw/qcn9224/rxpcu_ppdu_end_layout_info.h | 482 + hw/qcn9224/rxpt_classify_info.h | 182 + hw/qcn9224/seq_hwio.h | 90 + hw/qcn9224/sw_monitor_ring.h | 330 + hw/qcn9224/tcl_data_cmd.h | 420 + hw/qcn9224/tcl_entrance_from_ppe_ring.h | 382 + hw/qcn9224/tcl_gse_cmd.h | 222 + hw/qcn9224/tcl_status_ring.h | 202 + hw/qcn9224/tlv_hdr.h | 632 + hw/qcn9224/tlv_tag_def.h | 506 + hw/qcn9224/tx_msdu_extension.h | 532 + hw/qcn9224/tx_rate_stats_info.h | 152 + hw/qcn9224/uniform_descriptor_header.h | 72 + hw/qcn9224/uniform_reo_cmd_header.h | 72 + hw/qcn9224/uniform_reo_status_header.h | 92 + hw/qcn9224/vht_sig_a_info.h | 222 + hw/qcn9224/wbm2sw_completion_ring_rx.h | 466 + hw/qcn9224/wbm2sw_completion_ring_tx.h | 376 + hw/qcn9224/wbm_buffer_ring.h | 80 + hw/qcn9224/wbm_link_descriptor_ring.h | 80 + hw/qcn9224/wbm_release_ring.h | 190 + hw/qcn9224/wbm_release_ring_rx.h | 484 + hw/qcn9224/wbm_release_ring_tx.h | 404 + hw/qcn9224/wcss_seq_hwiobase.h | 162 + hw/qcn9224/wcss_seq_hwioreg_umac.h | 16031 ++++++++++++ hw/qcn9224/wcss_version.h | 17 + hw/qcn9224/wfss_ce_reg_seq_hwioreg.h | 20509 ++++++++++++++++ 99 files changed, 70149 insertions(+) create mode 100644 hw/qcn9224/HALcomdef.h create mode 100644 hw/qcn9224/HALhwio.h create mode 100644 hw/qcn9224/buffer_addr_info.h create mode 100644 hw/qcn9224/ce_src_desc.h create mode 100644 hw/qcn9224/ce_stat_desc.h create mode 100644 hw/qcn9224/com_dtypes.h create mode 100644 hw/qcn9224/he_sig_a_mu_dl_info.h create mode 100644 hw/qcn9224/he_sig_a_su_info.h create mode 100644 hw/qcn9224/he_sig_b1_mu_info.h create mode 100644 hw/qcn9224/he_sig_b2_mu_info.h create mode 100644 hw/qcn9224/he_sig_b2_ofdma_info.h create mode 100644 hw/qcn9224/ht_sig_info.h create mode 100644 hw/qcn9224/l_sig_a_info.h create mode 100644 hw/qcn9224/l_sig_b_info.h create mode 100644 hw/qcn9224/macrx_abort_request_info.h create mode 100644 hw/qcn9224/phyrx_abort_request_info.h create mode 100644 hw/qcn9224/phyrx_he_sig_a_mu_dl.h create mode 100644 hw/qcn9224/phyrx_he_sig_a_su.h create mode 100644 hw/qcn9224/phyrx_he_sig_b1_mu.h create mode 100644 hw/qcn9224/phyrx_he_sig_b2_mu.h create mode 100644 hw/qcn9224/phyrx_he_sig_b2_ofdma.h create mode 100644 hw/qcn9224/phyrx_ht_sig.h create mode 100644 hw/qcn9224/phyrx_l_sig_a.h create mode 100644 hw/qcn9224/phyrx_l_sig_b.h create mode 100644 hw/qcn9224/phyrx_location.h create mode 100644 hw/qcn9224/phyrx_other_receive_info_ru_details.h create mode 100644 hw/qcn9224/phyrx_pkt_end.h create mode 100644 hw/qcn9224/phyrx_pkt_end_info.h create mode 100644 hw/qcn9224/phyrx_rssi_legacy.h create mode 100644 hw/qcn9224/phyrx_vht_sig_a.h create mode 100644 hw/qcn9224/receive_rssi_info.h create mode 100644 hw/qcn9224/receive_user_info.h create mode 100644 hw/qcn9224/reo_descriptor_threshold_reached_status.h create mode 100644 hw/qcn9224/reo_destination_ring.h create mode 100644 hw/qcn9224/reo_entrance_ring.h create mode 100644 hw/qcn9224/reo_flush_cache.h create mode 100644 hw/qcn9224/reo_flush_cache_status.h create mode 100644 hw/qcn9224/reo_flush_queue.h create mode 100644 hw/qcn9224/reo_flush_queue_status.h create mode 100644 hw/qcn9224/reo_flush_timeout_list.h create mode 100644 hw/qcn9224/reo_flush_timeout_list_status.h create mode 100644 hw/qcn9224/reo_get_queue_stats.h create mode 100644 hw/qcn9224/reo_get_queue_stats_status.h create mode 100644 hw/qcn9224/reo_unblock_cache.h create mode 100644 hw/qcn9224/reo_unblock_cache_status.h create mode 100644 hw/qcn9224/reo_update_rx_reo_queue.h create mode 100644 hw/qcn9224/reo_update_rx_reo_queue_status.h create mode 100644 hw/qcn9224/rx_attention.h create mode 100644 hw/qcn9224/rx_flow_search_entry.h create mode 100644 hw/qcn9224/rx_location_info.h create mode 100644 hw/qcn9224/rx_mpdu_desc_info.h create mode 100644 hw/qcn9224/rx_mpdu_details.h create mode 100644 hw/qcn9224/rx_mpdu_end.h create mode 100644 hw/qcn9224/rx_mpdu_info.h create mode 100644 hw/qcn9224/rx_mpdu_link_ptr.h create mode 100644 hw/qcn9224/rx_mpdu_start.h create mode 100644 hw/qcn9224/rx_msdu_desc_info.h create mode 100644 hw/qcn9224/rx_msdu_details.h create mode 100644 hw/qcn9224/rx_msdu_end.h create mode 100644 hw/qcn9224/rx_msdu_ext_desc_info.h create mode 100644 hw/qcn9224/rx_msdu_link.h create mode 100644 hw/qcn9224/rx_msdu_start.h create mode 100644 hw/qcn9224/rx_ppdu_end_user_stats.h create mode 100644 hw/qcn9224/rx_ppdu_end_user_stats_ext.h create mode 100644 hw/qcn9224/rx_ppdu_start.h create mode 100644 hw/qcn9224/rx_ppdu_start_user_info.h create mode 100644 hw/qcn9224/rx_reo_queue.h create mode 100644 hw/qcn9224/rx_reo_queue_ext.h create mode 100644 hw/qcn9224/rx_reo_queue_reference.h create mode 100644 hw/qcn9224/rx_rxpcu_classification_overview.h create mode 100644 hw/qcn9224/rx_timing_offset_info.h create mode 100644 hw/qcn9224/rxpcu_ppdu_end_info.h create mode 100644 hw/qcn9224/rxpcu_ppdu_end_layout_info.h create mode 100644 hw/qcn9224/rxpt_classify_info.h create mode 100644 hw/qcn9224/seq_hwio.h create mode 100644 hw/qcn9224/sw_monitor_ring.h create mode 100644 hw/qcn9224/tcl_data_cmd.h create mode 100644 hw/qcn9224/tcl_entrance_from_ppe_ring.h create mode 100644 hw/qcn9224/tcl_gse_cmd.h create mode 100644 hw/qcn9224/tcl_status_ring.h create mode 100644 hw/qcn9224/tlv_hdr.h create mode 100644 hw/qcn9224/tlv_tag_def.h create mode 100644 hw/qcn9224/tx_msdu_extension.h create mode 100644 hw/qcn9224/tx_rate_stats_info.h create mode 100644 hw/qcn9224/uniform_descriptor_header.h create mode 100644 hw/qcn9224/uniform_reo_cmd_header.h create mode 100644 hw/qcn9224/uniform_reo_status_header.h create mode 100644 hw/qcn9224/vht_sig_a_info.h create mode 100644 hw/qcn9224/wbm2sw_completion_ring_rx.h create mode 100644 hw/qcn9224/wbm2sw_completion_ring_tx.h create mode 100644 hw/qcn9224/wbm_buffer_ring.h create mode 100644 hw/qcn9224/wbm_link_descriptor_ring.h create mode 100644 hw/qcn9224/wbm_release_ring.h create mode 100644 hw/qcn9224/wbm_release_ring_rx.h create mode 100644 hw/qcn9224/wbm_release_ring_tx.h create mode 100644 hw/qcn9224/wcss_seq_hwiobase.h create mode 100644 hw/qcn9224/wcss_seq_hwioreg_umac.h create mode 100644 hw/qcn9224/wcss_version.h create mode 100755 hw/qcn9224/wfss_ce_reg_seq_hwioreg.h diff --git a/hw/qcn9224/HALcomdef.h b/hw/qcn9224/HALcomdef.h new file mode 100644 index 000000000000..1192f6429d72 --- /dev/null +++ b/hw/qcn9224/HALcomdef.h @@ -0,0 +1,62 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef HAL_COMDEF_H +#define HAL_COMDEF_H + + + + +#ifndef _ARM_ASM_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#include "com_dtypes.h" + + + + +#ifndef _BOOL32_DEFINED +typedef unsigned long int bool32; +#define _BOOL32_DEFINED +#endif + + +#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF + + + + + + #define inp(port) (*((volatile byte *) (port))) + #define inpw(port) (*((volatile word *) (port))) + #define inpdw(port) (*((volatile dword *)(port))) + + #define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val))) + #define outpw(port, val) (*((volatile word *) (port)) = ((word) (val))) + #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val))) + +#ifdef __cplusplus +} +#endif + +#endif + +#endif + diff --git a/hw/qcn9224/HALhwio.h b/hw/qcn9224/HALhwio.h new file mode 100644 index 000000000000..edf301f4b72b --- /dev/null +++ b/hw/qcn9224/HALhwio.h @@ -0,0 +1,351 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef HAL_HWIO_H +#define HAL_HWIO_H + + + + + + + + +#include "HALcomdef.h" + + + + + + + + +#define HWIO_BASE_PTR(base) base##_BASE_PTR + + + +#ifdef __ARMCC_VERSION + #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base) +#else + #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base) +#endif + + + +#ifdef CONFIG_WHAL_MM +#define SEQ_WCSS_WCMN_OFFSET SEQ_WCSS_TOP_CMN_OFFSET +#define SEQ_WCSS_PMM_OFFSET SEQ_WCSS_PMM_TOP_OFFSET +#endif + + + + + +#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym) +#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index) +#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2) +#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3) + +#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym) +#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index) +#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2) +#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym) +#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index) +#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2) +#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3) + +#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym) +#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index) +#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2) +#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym) +#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index) +#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2) +#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3) + + + +#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym) +#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index) +#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2) +#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3) + +#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask) +#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask) +#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask) +#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) + +#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) + +#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym) +#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index) +#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2) +#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask) +#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask) +#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) +#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) + +#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) + + + +#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val) +#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val) +#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val) +#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val) + +#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val) +#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val) +#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val) +#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val) + +#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) + +#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) + +#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val) +#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val) +#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val) +#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) + +#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val) +#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) +#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) +#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) +#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val) +#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val) +#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val) + +#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2)) +#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) ) +#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) ) + +#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) + +#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) + + + +#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym) +#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index) +#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym) +#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym) +#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym) +#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val) +#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) +#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) + + + +#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym) +#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index) + + + + + + + + +#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN +#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index) +#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2) +#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3) +#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask) +#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask) +#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask) +#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask) +#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val) +#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val) +#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val) +#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val) +#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val) +#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val) +#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val) +#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val) +#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR +#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index) +#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2) +#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3) +#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS +#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index) +#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2) +#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3) +#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS +#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index) +#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2) +#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3) +#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK +#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index) +#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK +#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT +#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT +#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow +#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index) +#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL + +#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base) +#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index) +#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2) +#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3) +#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask) +#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask) +#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask) +#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask) +#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val) +#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val) +#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val) +#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val) +#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val) +#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + } +#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + HWIO_##hwiosym##_OUTM(base, mask3, val3); \ + } +#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + HWIO_##hwiosym##_OUTM(base, mask3, val3); \ + HWIO_##hwiosym##_OUTM(base, mask4, val4); \ + } + + +#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val) +#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val) +#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val) +#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base) +#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index) +#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2) +#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3) +#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base) +#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index) +#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2) +#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3) + + + +#define HWIO_INTLOCK() +#define HWIO_INTFREE() + + + +#define __inp(port) (*((volatile uint8 *) (port))) +#define __inpw(port) (*((volatile uint16 *) (port))) +#define __inpdw(port) (*((volatile uint32 *) (port))) +#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val))) +#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val))) +#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val))) + + +#ifdef HAL_HWIO_EXTERNAL + + +#undef __inp +#undef __inpw +#undef __inpdw +#undef __outp +#undef __outpw +#undef __outpdw + +#define __inp(port) __inp_extern((uint32) (port)) +#define __inpw(port) __inpw_extern((uint32) (port)) +#define __inpdw(port) __inpdw_extern((uint32) (port)) +#define __outp(port, val) __outp_extern((uint32) (port), val) +#define __outpw(port, val) __outpw_extern((uint32) (port), val) +#define __outpdw(port, val) __outpdw_extern((uint32) (port), val) + +extern uint8 __inp_extern ( uint32 nAddr ); +extern uint16 __inpw_extern ( uint32 nAddr ); +extern uint32 __inpdw_extern ( uint32 nAddr ); +extern void __outp_extern ( uint32 nAddr, uint8 nData ); +extern void __outpw_extern ( uint32 nAddr, uint16 nData ); +extern void __outpdw_extern ( uint32 nAddr, uint32 nData ); + +#endif + + + +#define in_byte(addr) (__inp(addr)) +#define in_byte_masked(addr, mask) (__inp(addr) & (mask)) +#define out_byte(addr, val) __outp(addr,val) +#define out_byte_masked(io, mask, val, shadow) \ + HWIO_INTLOCK(); \ + out_byte( io, shadow); \ + shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ + HWIO_INTFREE() +#define out_byte_masked_ns(io, mask, val, current_reg_content) \ + out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \ + ((uint16)((val) & (mask)))) ) + + + +#define in_word(addr) (__inpw(addr)) +#define in_word_masked(addr, mask) (__inpw(addr) & (mask)) +#define out_word(addr, val) __outpw(addr,val) +#define out_word_masked(io, mask, val, shadow) \ + HWIO_INTLOCK( ); \ + shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ + out_word( io, shadow); \ + HWIO_INTFREE( ) +#define out_word_masked_ns(io, mask, val, current_reg_content) \ + out_word( io, ((current_reg_content & (uint16)(~(mask))) | \ + ((uint16)((val) & (mask)))) ) + + + +#define in_dword(addr) (__inpdw(addr)) +#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask)) +#define out_dword(addr, val) __outpdw(addr,val) +#define out_dword_masked(io, mask, val, shadow) \ + HWIO_INTLOCK(); \ + shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \ + out_dword( io, shadow); \ + HWIO_INTFREE() +#define out_dword_masked_ns(io, mask, val, current_reg_content) \ + out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \ + ((uint32)((val) & (mask)))) ) + + + +#endif + diff --git a/hw/qcn9224/buffer_addr_info.h b/hw/qcn9224/buffer_addr_info.h new file mode 100644 index 000000000000..39a95cb79389 --- /dev/null +++ b/hw/qcn9224/buffer_addr_info.h @@ -0,0 +1,82 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _BUFFER_ADDR_INFO_H_ +#define _BUFFER_ADDR_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 + + +struct buffer_addr_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_addr_31_0 : 32; + uint32_t buffer_addr_39_32 : 8, + return_buffer_manager : 4, + sw_buffer_cookie : 20; +#else + uint32_t buffer_addr_31_0 : 32; + uint32_t sw_buffer_cookie : 20, + return_buffer_manager : 4, + buffer_addr_39_32 : 8; +#endif +}; + + + + +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + +#endif diff --git a/hw/qcn9224/ce_src_desc.h b/hw/qcn9224/ce_src_desc.h new file mode 100644 index 000000000000..1a83b7d520ca --- /dev/null +++ b/hw/qcn9224/ce_src_desc.h @@ -0,0 +1,192 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _CE_SRC_DESC_H_ +#define _CE_SRC_DESC_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_CE_SRC_DESC 4 + + +struct ce_src_desc { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t src_buffer_low : 32; + uint32_t src_buffer_high : 8, + toeplitz_en : 1, + src_swap : 1, + dest_swap : 1, + gather : 1, + ce_res_0 : 1, + barrier_read : 1, + ce_res_1 : 2, + length : 16; + uint32_t fw_metadata : 16, + ce_res_2 : 16; + uint32_t ce_res_3 : 20, + ring_id : 8, + looping_count : 4; +#else + uint32_t src_buffer_low : 32; + uint32_t length : 16, + ce_res_1 : 2, + barrier_read : 1, + ce_res_0 : 1, + gather : 1, + dest_swap : 1, + src_swap : 1, + toeplitz_en : 1, + src_buffer_high : 8; + uint32_t ce_res_2 : 16, + fw_metadata : 16; + uint32_t looping_count : 4, + ring_id : 8, + ce_res_3 : 20; +#endif +}; + + + + +#define CE_SRC_DESC_SRC_BUFFER_LOW_OFFSET 0x00000000 +#define CE_SRC_DESC_SRC_BUFFER_LOW_LSB 0 +#define CE_SRC_DESC_SRC_BUFFER_LOW_MSB 31 +#define CE_SRC_DESC_SRC_BUFFER_LOW_MASK 0xffffffff + + + + +#define CE_SRC_DESC_SRC_BUFFER_HIGH_OFFSET 0x00000004 +#define CE_SRC_DESC_SRC_BUFFER_HIGH_LSB 0 +#define CE_SRC_DESC_SRC_BUFFER_HIGH_MSB 7 +#define CE_SRC_DESC_SRC_BUFFER_HIGH_MASK 0x000000ff + + + + +#define CE_SRC_DESC_TOEPLITZ_EN_OFFSET 0x00000004 +#define CE_SRC_DESC_TOEPLITZ_EN_LSB 8 +#define CE_SRC_DESC_TOEPLITZ_EN_MSB 8 +#define CE_SRC_DESC_TOEPLITZ_EN_MASK 0x00000100 + + + + +#define CE_SRC_DESC_SRC_SWAP_OFFSET 0x00000004 +#define CE_SRC_DESC_SRC_SWAP_LSB 9 +#define CE_SRC_DESC_SRC_SWAP_MSB 9 +#define CE_SRC_DESC_SRC_SWAP_MASK 0x00000200 + + + + +#define CE_SRC_DESC_DEST_SWAP_OFFSET 0x00000004 +#define CE_SRC_DESC_DEST_SWAP_LSB 10 +#define CE_SRC_DESC_DEST_SWAP_MSB 10 +#define CE_SRC_DESC_DEST_SWAP_MASK 0x00000400 + + + + +#define CE_SRC_DESC_GATHER_OFFSET 0x00000004 +#define CE_SRC_DESC_GATHER_LSB 11 +#define CE_SRC_DESC_GATHER_MSB 11 +#define CE_SRC_DESC_GATHER_MASK 0x00000800 + + + + +#define CE_SRC_DESC_CE_RES_0_OFFSET 0x00000004 +#define CE_SRC_DESC_CE_RES_0_LSB 12 +#define CE_SRC_DESC_CE_RES_0_MSB 12 +#define CE_SRC_DESC_CE_RES_0_MASK 0x00001000 + + + + +#define CE_SRC_DESC_BARRIER_READ_OFFSET 0x00000004 +#define CE_SRC_DESC_BARRIER_READ_LSB 13 +#define CE_SRC_DESC_BARRIER_READ_MSB 13 +#define CE_SRC_DESC_BARRIER_READ_MASK 0x00002000 + + + + +#define CE_SRC_DESC_CE_RES_1_OFFSET 0x00000004 +#define CE_SRC_DESC_CE_RES_1_LSB 14 +#define CE_SRC_DESC_CE_RES_1_MSB 15 +#define CE_SRC_DESC_CE_RES_1_MASK 0x0000c000 + + + + +#define CE_SRC_DESC_LENGTH_OFFSET 0x00000004 +#define CE_SRC_DESC_LENGTH_LSB 16 +#define CE_SRC_DESC_LENGTH_MSB 31 +#define CE_SRC_DESC_LENGTH_MASK 0xffff0000 + + + + +#define CE_SRC_DESC_FW_METADATA_OFFSET 0x00000008 +#define CE_SRC_DESC_FW_METADATA_LSB 0 +#define CE_SRC_DESC_FW_METADATA_MSB 15 +#define CE_SRC_DESC_FW_METADATA_MASK 0x0000ffff + + + + +#define CE_SRC_DESC_CE_RES_2_OFFSET 0x00000008 +#define CE_SRC_DESC_CE_RES_2_LSB 16 +#define CE_SRC_DESC_CE_RES_2_MSB 31 +#define CE_SRC_DESC_CE_RES_2_MASK 0xffff0000 + + + + +#define CE_SRC_DESC_CE_RES_3_OFFSET 0x0000000c +#define CE_SRC_DESC_CE_RES_3_LSB 0 +#define CE_SRC_DESC_CE_RES_3_MSB 19 +#define CE_SRC_DESC_CE_RES_3_MASK 0x000fffff + + + + +#define CE_SRC_DESC_RING_ID_OFFSET 0x0000000c +#define CE_SRC_DESC_RING_ID_LSB 20 +#define CE_SRC_DESC_RING_ID_MSB 27 +#define CE_SRC_DESC_RING_ID_MASK 0x0ff00000 + + + + +#define CE_SRC_DESC_LOOPING_COUNT_OFFSET 0x0000000c +#define CE_SRC_DESC_LOOPING_COUNT_LSB 28 +#define CE_SRC_DESC_LOOPING_COUNT_MSB 31 +#define CE_SRC_DESC_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif diff --git a/hw/qcn9224/ce_stat_desc.h b/hw/qcn9224/ce_stat_desc.h new file mode 100644 index 000000000000..47a6760db107 --- /dev/null +++ b/hw/qcn9224/ce_stat_desc.h @@ -0,0 +1,182 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _CE_STAT_DESC_H_ +#define _CE_STAT_DESC_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_CE_STAT_DESC 4 + + +struct ce_stat_desc { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ce_res_5 : 8, + toeplitz_en : 1, + src_swap : 1, + dest_swap : 1, + gather : 1, + barrier_read : 1, + ce_res_6 : 3, + length : 16; + uint32_t toeplitz_hash_0 : 32; + uint32_t toeplitz_hash_1 : 32; + uint32_t fw_metadata : 16, + ce_res_7 : 4, + ring_id : 8, + looping_count : 4; +#else + uint32_t length : 16, + ce_res_6 : 3, + barrier_read : 1, + gather : 1, + dest_swap : 1, + src_swap : 1, + toeplitz_en : 1, + ce_res_5 : 8; + uint32_t toeplitz_hash_0 : 32; + uint32_t toeplitz_hash_1 : 32; + uint32_t looping_count : 4, + ring_id : 8, + ce_res_7 : 4, + fw_metadata : 16; +#endif +}; + + + + +#define CE_STAT_DESC_CE_RES_5_OFFSET 0x00000000 +#define CE_STAT_DESC_CE_RES_5_LSB 0 +#define CE_STAT_DESC_CE_RES_5_MSB 7 +#define CE_STAT_DESC_CE_RES_5_MASK 0x000000ff + + + + +#define CE_STAT_DESC_TOEPLITZ_EN_OFFSET 0x00000000 +#define CE_STAT_DESC_TOEPLITZ_EN_LSB 8 +#define CE_STAT_DESC_TOEPLITZ_EN_MSB 8 +#define CE_STAT_DESC_TOEPLITZ_EN_MASK 0x00000100 + + + + +#define CE_STAT_DESC_SRC_SWAP_OFFSET 0x00000000 +#define CE_STAT_DESC_SRC_SWAP_LSB 9 +#define CE_STAT_DESC_SRC_SWAP_MSB 9 +#define CE_STAT_DESC_SRC_SWAP_MASK 0x00000200 + + + + +#define CE_STAT_DESC_DEST_SWAP_OFFSET 0x00000000 +#define CE_STAT_DESC_DEST_SWAP_LSB 10 +#define CE_STAT_DESC_DEST_SWAP_MSB 10 +#define CE_STAT_DESC_DEST_SWAP_MASK 0x00000400 + + + + +#define CE_STAT_DESC_GATHER_OFFSET 0x00000000 +#define CE_STAT_DESC_GATHER_LSB 11 +#define CE_STAT_DESC_GATHER_MSB 11 +#define CE_STAT_DESC_GATHER_MASK 0x00000800 + + + + +#define CE_STAT_DESC_BARRIER_READ_OFFSET 0x00000000 +#define CE_STAT_DESC_BARRIER_READ_LSB 12 +#define CE_STAT_DESC_BARRIER_READ_MSB 12 +#define CE_STAT_DESC_BARRIER_READ_MASK 0x00001000 + + + + +#define CE_STAT_DESC_CE_RES_6_OFFSET 0x00000000 +#define CE_STAT_DESC_CE_RES_6_LSB 13 +#define CE_STAT_DESC_CE_RES_6_MSB 15 +#define CE_STAT_DESC_CE_RES_6_MASK 0x0000e000 + + + + +#define CE_STAT_DESC_LENGTH_OFFSET 0x00000000 +#define CE_STAT_DESC_LENGTH_LSB 16 +#define CE_STAT_DESC_LENGTH_MSB 31 +#define CE_STAT_DESC_LENGTH_MASK 0xffff0000 + + + + +#define CE_STAT_DESC_TOEPLITZ_HASH_0_OFFSET 0x00000004 +#define CE_STAT_DESC_TOEPLITZ_HASH_0_LSB 0 +#define CE_STAT_DESC_TOEPLITZ_HASH_0_MSB 31 +#define CE_STAT_DESC_TOEPLITZ_HASH_0_MASK 0xffffffff + + + + +#define CE_STAT_DESC_TOEPLITZ_HASH_1_OFFSET 0x00000008 +#define CE_STAT_DESC_TOEPLITZ_HASH_1_LSB 0 +#define CE_STAT_DESC_TOEPLITZ_HASH_1_MSB 31 +#define CE_STAT_DESC_TOEPLITZ_HASH_1_MASK 0xffffffff + + + + +#define CE_STAT_DESC_FW_METADATA_OFFSET 0x0000000c +#define CE_STAT_DESC_FW_METADATA_LSB 0 +#define CE_STAT_DESC_FW_METADATA_MSB 15 +#define CE_STAT_DESC_FW_METADATA_MASK 0x0000ffff + + + + +#define CE_STAT_DESC_CE_RES_7_OFFSET 0x0000000c +#define CE_STAT_DESC_CE_RES_7_LSB 16 +#define CE_STAT_DESC_CE_RES_7_MSB 19 +#define CE_STAT_DESC_CE_RES_7_MASK 0x000f0000 + + + + +#define CE_STAT_DESC_RING_ID_OFFSET 0x0000000c +#define CE_STAT_DESC_RING_ID_LSB 20 +#define CE_STAT_DESC_RING_ID_MSB 27 +#define CE_STAT_DESC_RING_ID_MASK 0x0ff00000 + + + + +#define CE_STAT_DESC_LOOPING_COUNT_OFFSET 0x0000000c +#define CE_STAT_DESC_LOOPING_COUNT_LSB 28 +#define CE_STAT_DESC_LOOPING_COUNT_MSB 31 +#define CE_STAT_DESC_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif diff --git a/hw/qcn9224/com_dtypes.h b/hw/qcn9224/com_dtypes.h new file mode 100644 index 000000000000..349b62371912 --- /dev/null +++ b/hw/qcn9224/com_dtypes.h @@ -0,0 +1,213 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef COM_DTYPES_H +#define COM_DTYPES_H + + + + + + + + + + + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef T_WINNT + #ifndef WIN32 + #define WIN32 + #endif + #include +#endif + + + +#ifdef TRUE +#undef TRUE +#endif + +#ifdef FALSE +#undef FALSE +#endif + + + + +#define TRUE 1 +#define FALSE 0 + +#define ON 1 +#define OFF 0 + +#ifndef NULL + #define NULL 0 +#endif + + + + + + + +#ifndef _ARM_ASM_ +#ifndef _BOOLEAN_DEFINED + + + +typedef unsigned char boolean; +#define _BOOLEAN_DEFINED +#endif + + +#if defined(DALSTDDEF_H) +#define _BOOLEAN_DEFINED +#define _UINT32_DEFINED +#define _UINT16_DEFINED +#define _UINT8_DEFINED +#define _INT32_DEFINED +#define _INT16_DEFINED +#define _INT8_DEFINED +#define _UINT64_DEFINED +#define _INT64_DEFINED +#define _BYTE_DEFINED +#endif + + +#ifndef _UINT32_DEFINED + +typedef unsigned long int uint32; +#define _UINT32_DEFINED +#endif + +#ifndef _UINT16_DEFINED + +typedef unsigned short uint16; +#define _UINT16_DEFINED +#endif + +#ifndef _UINT8_DEFINED + +typedef unsigned char uint8; +#define _UINT8_DEFINED +#endif + +#ifndef _INT32_DEFINED + +typedef signed long int int32; +#define _INT32_DEFINED +#endif + +#ifndef _INT16_DEFINED + +typedef signed short int16; +#define _INT16_DEFINED +#endif + +#ifndef _INT8_DEFINED + +typedef signed char int8; +#define _INT8_DEFINED +#endif + + + +#ifndef _BYTE_DEFINED + +typedef unsigned char byte; +#define _BYTE_DEFINED +#endif + + +typedef unsigned short word; + +typedef unsigned long dword; + + +typedef unsigned char uint1; + +typedef unsigned short uint2; + +typedef unsigned long uint4; + + +typedef signed char int1; + +typedef signed short int2; + +typedef long int int4; + + +typedef signed long sint31; + +typedef signed short sint15; + +typedef signed char sint7; + +typedef uint16 UWord16 ; +typedef uint32 UWord32 ; +typedef int32 Word32 ; +typedef int16 Word16 ; +typedef uint8 UWord8 ; +typedef int8 Word8 ; +typedef int32 Vect32 ; + + +#if (! defined T_WINNT) && (! defined __GNUC__) + + #ifndef _INT64_DEFINED + + typedef long long int64; + #define _INT64_DEFINED + #endif + #ifndef _UINT64_DEFINED + + typedef unsigned long long uint64; + #define _UINT64_DEFINED + #endif +#else + + #if (defined __GNUC__) + #ifndef _INT64_DEFINED + typedef long long int64; + #define _INT64_DEFINED + #endif + #ifndef _UINT64_DEFINED + typedef unsigned long long uint64; + #define _UINT64_DEFINED + #endif + #else + typedef __int64 int64; + #ifndef _UINT64_DEFINED + typedef unsigned __int64 uint64; + #define _UINT64_DEFINED + #endif + #endif +#endif + +#endif + +#ifdef __cplusplus +} +#endif + + +#endif diff --git a/hw/qcn9224/he_sig_a_mu_dl_info.h b/hw/qcn9224/he_sig_a_mu_dl_info.h new file mode 100644 index 000000000000..4c50a3d6bb98 --- /dev/null +++ b/hw/qcn9224/he_sig_a_mu_dl_info.h @@ -0,0 +1,262 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _HE_SIG_A_MU_DL_INFO_H_ +#define _HE_SIG_A_MU_DL_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2 + + +struct he_sig_a_mu_dl_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t dl_ul_flag : 1, + mcs_of_sig_b : 3, + dcm_of_sig_b : 1, + bss_color_id : 6, + spatial_reuse : 4, + transmit_bw : 3, + num_sig_b_symbols : 4, + comp_mode_sig_b : 1, + cp_ltf_size : 2, + doppler_indication : 1, + reserved_0a : 6; + uint32_t txop_duration : 7, + reserved_1a : 1, + num_ltf_symbols : 3, + ldpc_extra_symbol : 1, + stbc : 1, + packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + crc : 4, + tail : 6, + reserved_1b : 5, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0a : 6, + doppler_indication : 1, + cp_ltf_size : 2, + comp_mode_sig_b : 1, + num_sig_b_symbols : 4, + transmit_bw : 3, + spatial_reuse : 4, + bss_color_id : 6, + dcm_of_sig_b : 1, + mcs_of_sig_b : 3, + dl_ul_flag : 1; + uint32_t rx_integrity_check_passed : 1, + reserved_1b : 5, + tail : 6, + crc : 4, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2, + stbc : 1, + ldpc_extra_symbol : 1, + num_ltf_symbols : 3, + reserved_1a : 1, + txop_duration : 7; +#endif +}; + + + + +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_LSB 0 +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MSB 0 +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MASK 0x00000001 + + + + +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_LSB 1 +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MSB 3 +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MASK 0x0000000e + + + + +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_LSB 4 +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MSB 4 +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MASK 0x00000010 + + + + +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_LSB 5 +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MSB 10 +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MASK 0x000007e0 + + + + +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_LSB 11 +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MSB 14 +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MASK 0x00007800 + + + + +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_LSB 15 +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MSB 17 +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MASK 0x00038000 + + + + +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_LSB 18 +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MSB 21 +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 + + + + +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_LSB 22 +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MSB 22 +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MASK 0x00400000 + + + + +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_LSB 23 +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MSB 24 +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MASK 0x01800000 + + + + +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_LSB 25 +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MSB 25 +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MASK 0x02000000 + + + + +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_LSB 26 +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MSB 31 +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MASK 0xfc000000 + + + + +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_LSB 0 +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MSB 6 +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MASK 0x0000007f + + + + +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_LSB 7 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MSB 7 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MASK 0x00000080 + + + + +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_LSB 8 +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MSB 10 +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MASK 0x00000700 + + + + +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_LSB 11 +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MSB 11 +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000800 + + + + +#define HE_SIG_A_MU_DL_INFO_STBC_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_STBC_LSB 12 +#define HE_SIG_A_MU_DL_INFO_STBC_MSB 12 +#define HE_SIG_A_MU_DL_INFO_STBC_MASK 0x00001000 + + + + +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_LSB 13 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MSB 14 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 + + + + +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 + + + + +#define HE_SIG_A_MU_DL_INFO_CRC_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_CRC_LSB 16 +#define HE_SIG_A_MU_DL_INFO_CRC_MSB 19 +#define HE_SIG_A_MU_DL_INFO_CRC_MASK 0x000f0000 + + + + +#define HE_SIG_A_MU_DL_INFO_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_TAIL_LSB 20 +#define HE_SIG_A_MU_DL_INFO_TAIL_MSB 25 +#define HE_SIG_A_MU_DL_INFO_TAIL_MASK 0x03f00000 + + + + +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_LSB 26 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MSB 30 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MASK 0x7c000000 + + + + +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif diff --git a/hw/qcn9224/he_sig_a_su_info.h b/hw/qcn9224/he_sig_a_su_info.h new file mode 100644 index 000000000000..de0238dab73b --- /dev/null +++ b/hw/qcn9224/he_sig_a_su_info.h @@ -0,0 +1,312 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _HE_SIG_A_SU_INFO_H_ +#define _HE_SIG_A_SU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2 + + +struct he_sig_a_su_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t format_indication : 1, + beam_change : 1, + dl_ul_flag : 1, + transmit_mcs : 4, + dcm : 1, + bss_color_id : 6, + reserved_0a : 1, + spatial_reuse : 4, + transmit_bw : 2, + cp_ltf_size : 2, + nsts : 3, + reserved_0b : 6; + uint32_t txop_duration : 7, + coding : 1, + ldpc_extra_symbol : 1, + stbc : 1, + txbf : 1, + packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + reserved_1a : 1, + doppler_indication : 1, + crc : 4, + tail : 6, + dot11ax_su_extended : 1, + dot11ax_ext_ru_size : 3, + rx_ndp : 1, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0b : 6, + nsts : 3, + cp_ltf_size : 2, + transmit_bw : 2, + spatial_reuse : 4, + reserved_0a : 1, + bss_color_id : 6, + dcm : 1, + transmit_mcs : 4, + dl_ul_flag : 1, + beam_change : 1, + format_indication : 1; + uint32_t rx_integrity_check_passed : 1, + rx_ndp : 1, + dot11ax_ext_ru_size : 3, + dot11ax_su_extended : 1, + tail : 6, + crc : 4, + doppler_indication : 1, + reserved_1a : 1, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2, + txbf : 1, + stbc : 1, + ldpc_extra_symbol : 1, + coding : 1, + txop_duration : 7; +#endif +}; + + + + +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_LSB 0 +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MSB 0 +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MASK 0x00000001 + + + + +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_LSB 1 +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MSB 1 +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MASK 0x00000002 + + + + +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_LSB 2 +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MSB 2 +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MASK 0x00000004 + + + + +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_LSB 3 +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MSB 6 +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MASK 0x00000078 + + + + +#define HE_SIG_A_SU_INFO_DCM_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_DCM_LSB 7 +#define HE_SIG_A_SU_INFO_DCM_MSB 7 +#define HE_SIG_A_SU_INFO_DCM_MASK 0x00000080 + + + + +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_LSB 8 +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MSB 13 +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MASK 0x00003f00 + + + + +#define HE_SIG_A_SU_INFO_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_RESERVED_0A_LSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_0A_MSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_0A_MASK 0x00004000 + + + + +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_LSB 15 +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MSB 18 +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MASK 0x00078000 + + + + +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_LSB 19 +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MSB 20 +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MASK 0x00180000 + + + + +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_LSB 21 +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MSB 22 +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MASK 0x00600000 + + + + +#define HE_SIG_A_SU_INFO_NSTS_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_NSTS_LSB 23 +#define HE_SIG_A_SU_INFO_NSTS_MSB 25 +#define HE_SIG_A_SU_INFO_NSTS_MASK 0x03800000 + + + + +#define HE_SIG_A_SU_INFO_RESERVED_0B_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_RESERVED_0B_LSB 26 +#define HE_SIG_A_SU_INFO_RESERVED_0B_MSB 31 +#define HE_SIG_A_SU_INFO_RESERVED_0B_MASK 0xfc000000 + + + + +#define HE_SIG_A_SU_INFO_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_TXOP_DURATION_LSB 0 +#define HE_SIG_A_SU_INFO_TXOP_DURATION_MSB 6 +#define HE_SIG_A_SU_INFO_TXOP_DURATION_MASK 0x0000007f + + + + +#define HE_SIG_A_SU_INFO_CODING_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_CODING_LSB 7 +#define HE_SIG_A_SU_INFO_CODING_MSB 7 +#define HE_SIG_A_SU_INFO_CODING_MASK 0x00000080 + + + + +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_LSB 8 +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MSB 8 +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000100 + + + + +#define HE_SIG_A_SU_INFO_STBC_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_STBC_LSB 9 +#define HE_SIG_A_SU_INFO_STBC_MSB 9 +#define HE_SIG_A_SU_INFO_STBC_MASK 0x00000200 + + + + +#define HE_SIG_A_SU_INFO_TXBF_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_TXBF_LSB 10 +#define HE_SIG_A_SU_INFO_TXBF_MSB 10 +#define HE_SIG_A_SU_INFO_TXBF_MASK 0x00000400 + + + + +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_LSB 11 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MSB 12 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800 + + + + +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000 + + + + +#define HE_SIG_A_SU_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_RESERVED_1A_LSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_1A_MSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_1A_MASK 0x00004000 + + + + +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_LSB 15 +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MSB 15 +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MASK 0x00008000 + + + + +#define HE_SIG_A_SU_INFO_CRC_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_CRC_LSB 16 +#define HE_SIG_A_SU_INFO_CRC_MSB 19 +#define HE_SIG_A_SU_INFO_CRC_MASK 0x000f0000 + + + + +#define HE_SIG_A_SU_INFO_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_TAIL_LSB 20 +#define HE_SIG_A_SU_INFO_TAIL_MSB 25 +#define HE_SIG_A_SU_INFO_TAIL_MASK 0x03f00000 + + + + +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_LSB 26 +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MSB 26 +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 + + + + +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_LSB 27 +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MSB 29 +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x38000000 + + + + +#define HE_SIG_A_SU_INFO_RX_NDP_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_RX_NDP_LSB 30 +#define HE_SIG_A_SU_INFO_RX_NDP_MSB 30 +#define HE_SIG_A_SU_INFO_RX_NDP_MASK 0x40000000 + + + + +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif diff --git a/hw/qcn9224/he_sig_b1_mu_info.h b/hw/qcn9224/he_sig_b1_mu_info.h new file mode 100644 index 000000000000..a64a92e26bf0 --- /dev/null +++ b/hw/qcn9224/he_sig_b1_mu_info.h @@ -0,0 +1,72 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _HE_SIG_B1_MU_INFO_H_ +#define _HE_SIG_B1_MU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1 + + +struct he_sig_b1_mu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ru_allocation : 8, + reserved_0 : 23, + rx_integrity_check_passed : 1; +#else + uint32_t rx_integrity_check_passed : 1, + reserved_0 : 23, + ru_allocation : 8; +#endif +}; + + + + +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_LSB 0 +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MSB 7 +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MASK 0x000000ff + + + + +#define HE_SIG_B1_MU_INFO_RESERVED_0_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_RESERVED_0_LSB 8 +#define HE_SIG_B1_MU_INFO_RESERVED_0_MSB 30 +#define HE_SIG_B1_MU_INFO_RESERVED_0_MASK 0x7fffff00 + + + + +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif diff --git a/hw/qcn9224/he_sig_b2_mu_info.h b/hw/qcn9224/he_sig_b2_mu_info.h new file mode 100644 index 000000000000..01a0550dc9cc --- /dev/null +++ b/hw/qcn9224/he_sig_b2_mu_info.h @@ -0,0 +1,152 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _HE_SIG_B2_MU_INFO_H_ +#define _HE_SIG_B2_MU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 2 + + +struct he_sig_b2_mu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + sta_spatial_config : 4, + sta_mcs : 4, + reserved_set_to_1 : 1, + sta_coding : 1, + reserved_0a : 7, + nsts : 3, + rx_integrity_check_passed : 1; + uint32_t user_order : 8, + cc_mask : 8, + reserved_1a : 16; +#else + uint32_t rx_integrity_check_passed : 1, + nsts : 3, + reserved_0a : 7, + sta_coding : 1, + reserved_set_to_1 : 1, + sta_mcs : 4, + sta_spatial_config : 4, + sta_id : 11; + uint32_t reserved_1a : 16, + cc_mask : 8, + user_order : 8; +#endif +}; + + + + +#define HE_SIG_B2_MU_INFO_STA_ID_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_ID_LSB 0 +#define HE_SIG_B2_MU_INFO_STA_ID_MSB 10 +#define HE_SIG_B2_MU_INFO_STA_ID_MASK 0x000007ff + + + + +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_LSB 11 +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MSB 14 +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MASK 0x00007800 + + + + +#define HE_SIG_B2_MU_INFO_STA_MCS_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_MCS_LSB 15 +#define HE_SIG_B2_MU_INFO_STA_MCS_MSB 18 +#define HE_SIG_B2_MU_INFO_STA_MCS_MASK 0x00078000 + + + + +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_LSB 19 +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MSB 19 +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MASK 0x00080000 + + + + +#define HE_SIG_B2_MU_INFO_STA_CODING_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_CODING_LSB 20 +#define HE_SIG_B2_MU_INFO_STA_CODING_MSB 20 +#define HE_SIG_B2_MU_INFO_STA_CODING_MASK 0x00100000 + + + + +#define HE_SIG_B2_MU_INFO_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_RESERVED_0A_LSB 21 +#define HE_SIG_B2_MU_INFO_RESERVED_0A_MSB 27 +#define HE_SIG_B2_MU_INFO_RESERVED_0A_MASK 0x0fe00000 + + + + +#define HE_SIG_B2_MU_INFO_NSTS_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_NSTS_LSB 28 +#define HE_SIG_B2_MU_INFO_NSTS_MSB 30 +#define HE_SIG_B2_MU_INFO_NSTS_MASK 0x70000000 + + + + +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + + +#define HE_SIG_B2_MU_INFO_USER_ORDER_OFFSET 0x00000004 +#define HE_SIG_B2_MU_INFO_USER_ORDER_LSB 0 +#define HE_SIG_B2_MU_INFO_USER_ORDER_MSB 7 +#define HE_SIG_B2_MU_INFO_USER_ORDER_MASK 0x000000ff + + + + +#define HE_SIG_B2_MU_INFO_CC_MASK_OFFSET 0x00000004 +#define HE_SIG_B2_MU_INFO_CC_MASK_LSB 8 +#define HE_SIG_B2_MU_INFO_CC_MASK_MSB 15 +#define HE_SIG_B2_MU_INFO_CC_MASK_MASK 0x0000ff00 + + + + +#define HE_SIG_B2_MU_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_B2_MU_INFO_RESERVED_1A_LSB 16 +#define HE_SIG_B2_MU_INFO_RESERVED_1A_MSB 31 +#define HE_SIG_B2_MU_INFO_RESERVED_1A_MASK 0xffff0000 + + + +#endif diff --git a/hw/qcn9224/he_sig_b2_ofdma_info.h b/hw/qcn9224/he_sig_b2_ofdma_info.h new file mode 100644 index 000000000000..dab736419211 --- /dev/null +++ b/hw/qcn9224/he_sig_b2_ofdma_info.h @@ -0,0 +1,152 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _HE_SIG_B2_OFDMA_INFO_H_ +#define _HE_SIG_B2_OFDMA_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 2 + + +struct he_sig_b2_ofdma_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + nsts : 3, + txbf : 1, + sta_mcs : 4, + sta_dcm : 1, + sta_coding : 1, + reserved_0 : 10, + rx_integrity_check_passed : 1; + uint32_t user_order : 8, + cc_mask : 8, + reserved_1a : 16; +#else + uint32_t rx_integrity_check_passed : 1, + reserved_0 : 10, + sta_coding : 1, + sta_dcm : 1, + sta_mcs : 4, + txbf : 1, + nsts : 3, + sta_id : 11; + uint32_t reserved_1a : 16, + cc_mask : 8, + user_order : 8; +#endif +}; + + + + +#define HE_SIG_B2_OFDMA_INFO_STA_ID_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_ID_LSB 0 +#define HE_SIG_B2_OFDMA_INFO_STA_ID_MSB 10 +#define HE_SIG_B2_OFDMA_INFO_STA_ID_MASK 0x000007ff + + + + +#define HE_SIG_B2_OFDMA_INFO_NSTS_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_NSTS_LSB 11 +#define HE_SIG_B2_OFDMA_INFO_NSTS_MSB 13 +#define HE_SIG_B2_OFDMA_INFO_NSTS_MASK 0x00003800 + + + + +#define HE_SIG_B2_OFDMA_INFO_TXBF_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_TXBF_LSB 14 +#define HE_SIG_B2_OFDMA_INFO_TXBF_MSB 14 +#define HE_SIG_B2_OFDMA_INFO_TXBF_MASK 0x00004000 + + + + +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_LSB 15 +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MSB 18 +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MASK 0x00078000 + + + + +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_LSB 19 +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MSB 19 +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MASK 0x00080000 + + + + +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_LSB 20 +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MSB 20 +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MASK 0x00100000 + + + + +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_LSB 21 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MSB 30 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MASK 0x7fe00000 + + + + +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + + +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_OFFSET 0x00000004 +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_LSB 0 +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MSB 7 +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MASK 0x000000ff + + + + +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_OFFSET 0x00000004 +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_LSB 8 +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MSB 15 +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MASK 0x0000ff00 + + + + +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_LSB 16 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MSB 31 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MASK 0xffff0000 + + + +#endif diff --git a/hw/qcn9224/ht_sig_info.h b/hw/qcn9224/ht_sig_info.h new file mode 100644 index 000000000000..430c5bbbbf64 --- /dev/null +++ b/hw/qcn9224/ht_sig_info.h @@ -0,0 +1,202 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _HT_SIG_INFO_H_ +#define _HT_SIG_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HT_SIG_INFO 2 + + +struct ht_sig_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mcs : 7, + cbw : 1, + length : 16, + reserved_0 : 8; + uint32_t smoothing : 1, + not_sounding : 1, + ht_reserved : 1, + aggregation : 1, + stbc : 2, + fec_coding : 1, + short_gi : 1, + num_ext_sp_str : 2, + crc : 8, + signal_tail : 6, + reserved_1 : 7, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0 : 8, + length : 16, + cbw : 1, + mcs : 7; + uint32_t rx_integrity_check_passed : 1, + reserved_1 : 7, + signal_tail : 6, + crc : 8, + num_ext_sp_str : 2, + short_gi : 1, + fec_coding : 1, + stbc : 2, + aggregation : 1, + ht_reserved : 1, + not_sounding : 1, + smoothing : 1; +#endif +}; + + + + +#define HT_SIG_INFO_MCS_OFFSET 0x00000000 +#define HT_SIG_INFO_MCS_LSB 0 +#define HT_SIG_INFO_MCS_MSB 6 +#define HT_SIG_INFO_MCS_MASK 0x0000007f + + + + +#define HT_SIG_INFO_CBW_OFFSET 0x00000000 +#define HT_SIG_INFO_CBW_LSB 7 +#define HT_SIG_INFO_CBW_MSB 7 +#define HT_SIG_INFO_CBW_MASK 0x00000080 + + + + +#define HT_SIG_INFO_LENGTH_OFFSET 0x00000000 +#define HT_SIG_INFO_LENGTH_LSB 8 +#define HT_SIG_INFO_LENGTH_MSB 23 +#define HT_SIG_INFO_LENGTH_MASK 0x00ffff00 + + + + +#define HT_SIG_INFO_RESERVED_0_OFFSET 0x00000000 +#define HT_SIG_INFO_RESERVED_0_LSB 24 +#define HT_SIG_INFO_RESERVED_0_MSB 31 +#define HT_SIG_INFO_RESERVED_0_MASK 0xff000000 + + + + +#define HT_SIG_INFO_SMOOTHING_OFFSET 0x00000004 +#define HT_SIG_INFO_SMOOTHING_LSB 0 +#define HT_SIG_INFO_SMOOTHING_MSB 0 +#define HT_SIG_INFO_SMOOTHING_MASK 0x00000001 + + + + +#define HT_SIG_INFO_NOT_SOUNDING_OFFSET 0x00000004 +#define HT_SIG_INFO_NOT_SOUNDING_LSB 1 +#define HT_SIG_INFO_NOT_SOUNDING_MSB 1 +#define HT_SIG_INFO_NOT_SOUNDING_MASK 0x00000002 + + + + +#define HT_SIG_INFO_HT_RESERVED_OFFSET 0x00000004 +#define HT_SIG_INFO_HT_RESERVED_LSB 2 +#define HT_SIG_INFO_HT_RESERVED_MSB 2 +#define HT_SIG_INFO_HT_RESERVED_MASK 0x00000004 + + + + +#define HT_SIG_INFO_AGGREGATION_OFFSET 0x00000004 +#define HT_SIG_INFO_AGGREGATION_LSB 3 +#define HT_SIG_INFO_AGGREGATION_MSB 3 +#define HT_SIG_INFO_AGGREGATION_MASK 0x00000008 + + + + +#define HT_SIG_INFO_STBC_OFFSET 0x00000004 +#define HT_SIG_INFO_STBC_LSB 4 +#define HT_SIG_INFO_STBC_MSB 5 +#define HT_SIG_INFO_STBC_MASK 0x00000030 + + + + +#define HT_SIG_INFO_FEC_CODING_OFFSET 0x00000004 +#define HT_SIG_INFO_FEC_CODING_LSB 6 +#define HT_SIG_INFO_FEC_CODING_MSB 6 +#define HT_SIG_INFO_FEC_CODING_MASK 0x00000040 + + + + +#define HT_SIG_INFO_SHORT_GI_OFFSET 0x00000004 +#define HT_SIG_INFO_SHORT_GI_LSB 7 +#define HT_SIG_INFO_SHORT_GI_MSB 7 +#define HT_SIG_INFO_SHORT_GI_MASK 0x00000080 + + + + +#define HT_SIG_INFO_NUM_EXT_SP_STR_OFFSET 0x00000004 +#define HT_SIG_INFO_NUM_EXT_SP_STR_LSB 8 +#define HT_SIG_INFO_NUM_EXT_SP_STR_MSB 9 +#define HT_SIG_INFO_NUM_EXT_SP_STR_MASK 0x00000300 + + + + +#define HT_SIG_INFO_CRC_OFFSET 0x00000004 +#define HT_SIG_INFO_CRC_LSB 10 +#define HT_SIG_INFO_CRC_MSB 17 +#define HT_SIG_INFO_CRC_MASK 0x0003fc00 + + + + +#define HT_SIG_INFO_SIGNAL_TAIL_OFFSET 0x00000004 +#define HT_SIG_INFO_SIGNAL_TAIL_LSB 18 +#define HT_SIG_INFO_SIGNAL_TAIL_MSB 23 +#define HT_SIG_INFO_SIGNAL_TAIL_MASK 0x00fc0000 + + + + +#define HT_SIG_INFO_RESERVED_1_OFFSET 0x00000004 +#define HT_SIG_INFO_RESERVED_1_LSB 24 +#define HT_SIG_INFO_RESERVED_1_MSB 30 +#define HT_SIG_INFO_RESERVED_1_MASK 0x7f000000 + + + + +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif diff --git a/hw/qcn9224/l_sig_a_info.h b/hw/qcn9224/l_sig_a_info.h new file mode 100644 index 000000000000..e5009874243e --- /dev/null +++ b/hw/qcn9224/l_sig_a_info.h @@ -0,0 +1,132 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _L_SIG_A_INFO_H_ +#define _L_SIG_A_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_L_SIG_A_INFO 1 + + +struct l_sig_a_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rate : 4, + lsig_reserved : 1, + length : 12, + parity : 1, + tail : 6, + pkt_type : 4, + captured_implicit_sounding : 1, + reserved : 2, + rx_integrity_check_passed : 1; +#else + uint32_t rx_integrity_check_passed : 1, + reserved : 2, + captured_implicit_sounding : 1, + pkt_type : 4, + tail : 6, + parity : 1, + length : 12, + lsig_reserved : 1, + rate : 4; +#endif +}; + + + + +#define L_SIG_A_INFO_RATE_OFFSET 0x00000000 +#define L_SIG_A_INFO_RATE_LSB 0 +#define L_SIG_A_INFO_RATE_MSB 3 +#define L_SIG_A_INFO_RATE_MASK 0x0000000f + + + + +#define L_SIG_A_INFO_LSIG_RESERVED_OFFSET 0x00000000 +#define L_SIG_A_INFO_LSIG_RESERVED_LSB 4 +#define L_SIG_A_INFO_LSIG_RESERVED_MSB 4 +#define L_SIG_A_INFO_LSIG_RESERVED_MASK 0x00000010 + + + + +#define L_SIG_A_INFO_LENGTH_OFFSET 0x00000000 +#define L_SIG_A_INFO_LENGTH_LSB 5 +#define L_SIG_A_INFO_LENGTH_MSB 16 +#define L_SIG_A_INFO_LENGTH_MASK 0x0001ffe0 + + + + +#define L_SIG_A_INFO_PARITY_OFFSET 0x00000000 +#define L_SIG_A_INFO_PARITY_LSB 17 +#define L_SIG_A_INFO_PARITY_MSB 17 +#define L_SIG_A_INFO_PARITY_MASK 0x00020000 + + + + +#define L_SIG_A_INFO_TAIL_OFFSET 0x00000000 +#define L_SIG_A_INFO_TAIL_LSB 18 +#define L_SIG_A_INFO_TAIL_MSB 23 +#define L_SIG_A_INFO_TAIL_MASK 0x00fc0000 + + + + +#define L_SIG_A_INFO_PKT_TYPE_OFFSET 0x00000000 +#define L_SIG_A_INFO_PKT_TYPE_LSB 24 +#define L_SIG_A_INFO_PKT_TYPE_MSB 27 +#define L_SIG_A_INFO_PKT_TYPE_MASK 0x0f000000 + + + + +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000 +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MSB 28 +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000 + + + + +#define L_SIG_A_INFO_RESERVED_OFFSET 0x00000000 +#define L_SIG_A_INFO_RESERVED_LSB 29 +#define L_SIG_A_INFO_RESERVED_MSB 30 +#define L_SIG_A_INFO_RESERVED_MASK 0x60000000 + + + + +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif diff --git a/hw/qcn9224/l_sig_b_info.h b/hw/qcn9224/l_sig_b_info.h new file mode 100644 index 000000000000..4a17dafbd334 --- /dev/null +++ b/hw/qcn9224/l_sig_b_info.h @@ -0,0 +1,82 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _L_SIG_B_INFO_H_ +#define _L_SIG_B_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_L_SIG_B_INFO 1 + + +struct l_sig_b_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rate : 4, + length : 12, + reserved : 15, + rx_integrity_check_passed : 1; +#else + uint32_t rx_integrity_check_passed : 1, + reserved : 15, + length : 12, + rate : 4; +#endif +}; + + + + +#define L_SIG_B_INFO_RATE_OFFSET 0x00000000 +#define L_SIG_B_INFO_RATE_LSB 0 +#define L_SIG_B_INFO_RATE_MSB 3 +#define L_SIG_B_INFO_RATE_MASK 0x0000000f + + + + +#define L_SIG_B_INFO_LENGTH_OFFSET 0x00000000 +#define L_SIG_B_INFO_LENGTH_LSB 4 +#define L_SIG_B_INFO_LENGTH_MSB 15 +#define L_SIG_B_INFO_LENGTH_MASK 0x0000fff0 + + + + +#define L_SIG_B_INFO_RESERVED_OFFSET 0x00000000 +#define L_SIG_B_INFO_RESERVED_LSB 16 +#define L_SIG_B_INFO_RESERVED_MSB 30 +#define L_SIG_B_INFO_RESERVED_MASK 0x7fff0000 + + + + +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif diff --git a/hw/qcn9224/macrx_abort_request_info.h b/hw/qcn9224/macrx_abort_request_info.h new file mode 100644 index 000000000000..07d47e225d58 --- /dev/null +++ b/hw/qcn9224/macrx_abort_request_info.h @@ -0,0 +1,62 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _MACRX_ABORT_REQUEST_INFO_H_ +#define _MACRX_ABORT_REQUEST_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1 + + +struct macrx_abort_request_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t macrx_abort_reason : 8, + reserved_0 : 8; +#else + uint16_t reserved_0 : 8, + macrx_abort_reason : 8; +#endif +}; + + + + +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_OFFSET 0x00000000 +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_LSB 0 +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MSB 7 +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MASK 0x000000ff + + + + +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 8 +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000ff00 + + + +#endif diff --git a/hw/qcn9224/phyrx_abort_request_info.h b/hw/qcn9224/phyrx_abort_request_info.h new file mode 100644 index 000000000000..a2bc146ee63c --- /dev/null +++ b/hw/qcn9224/phyrx_abort_request_info.h @@ -0,0 +1,92 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _PHYRX_ABORT_REQUEST_INFO_H_ +#define _PHYRX_ABORT_REQUEST_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1 + + +struct phyrx_abort_request_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phyrx_abort_reason : 8, + phy_enters_nap_state : 1, + phy_enters_defer_state : 1, + reserved_0 : 6, + receive_duration : 16; +#else + uint32_t receive_duration : 16, + reserved_0 : 6, + phy_enters_defer_state : 1, + phy_enters_nap_state : 1, + phyrx_abort_reason : 8; +#endif +}; + + + + +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_LSB 0 +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MSB 7 +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MASK 0x000000ff + + + + +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_LSB 8 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MSB 8 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MASK 0x00000100 + + + + +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_LSB 9 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MSB 9 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 + + + + +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 10 +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000fc00 + + + + +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_LSB 16 +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MSB 31 +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MASK 0xffff0000 + + + +#endif diff --git a/hw/qcn9224/phyrx_he_sig_a_mu_dl.h b/hw/qcn9224/phyrx_he_sig_a_mu_dl.h new file mode 100644 index 000000000000..ce4ad561bb51 --- /dev/null +++ b/hw/qcn9224/phyrx_he_sig_a_mu_dl.h @@ -0,0 +1,226 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _PHYRX_HE_SIG_A_MU_DL_H_ +#define _PHYRX_HE_SIG_A_MU_DL_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_mu_dl_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2 + +#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_DL 1 + + +struct phyrx_he_sig_a_mu_dl { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; +#else + struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; +#endif +}; + + + + + + + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001 + + + + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e + + + + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010 + + + + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0 + + + + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800 + + + + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000 + + + + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000 + + + + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000 + + + + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000 + + + + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000 + + + + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000 + + + + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 + + + + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000 + + + + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000 + + + + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000 + + + + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000 + + + + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000 + + + + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000 + + + + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000 + + + + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + + + + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 + + + + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif diff --git a/hw/qcn9224/phyrx_he_sig_a_su.h b/hw/qcn9224/phyrx_he_sig_a_su.h new file mode 100644 index 000000000000..e3cb6b6146cd --- /dev/null +++ b/hw/qcn9224/phyrx_he_sig_a_su.h @@ -0,0 +1,266 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _PHYRX_HE_SIG_A_SU_H_ +#define _PHYRX_HE_SIG_A_SU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_su_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2 + +#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_SU 1 + + +struct phyrx_he_sig_a_su { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; +#else + struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; +#endif +}; + + + + + + + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 + + + + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002 + + + + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004 + + + + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078 + + + + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080 + + + + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00 + + + + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000 + + + + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000 + + + + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000 + + + + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000 + + + + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000 + + + + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 + + + + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 + + + + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000 + + + + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000 + + + + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000 + + + + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000 + + + + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000 + + + + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000 + + + + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000 + + + + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000 + + + + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000 + + + + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + + + + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 + + + + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000 + + + + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 + + + + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif diff --git a/hw/qcn9224/phyrx_he_sig_b1_mu.h b/hw/qcn9224/phyrx_he_sig_b1_mu.h new file mode 100644 index 000000000000..df2c8b41b5aa --- /dev/null +++ b/hw/qcn9224/phyrx_he_sig_b1_mu.h @@ -0,0 +1,84 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _PHYRX_HE_SIG_B1_MU_H_ +#define _PHYRX_HE_SIG_B1_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b1_mu_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 2 + +#define NUM_OF_QWORDS_PHYRX_HE_SIG_B1_MU 1 + + +struct phyrx_he_sig_b1_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; + uint32_t tlv64_padding : 32; +#else + struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; + uint32_t tlv64_padding : 32; +#endif +}; + + + + + + + +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff + + + + +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00 + + + + +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + + + + +#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32 +#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63 +#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif diff --git a/hw/qcn9224/phyrx_he_sig_b2_mu.h b/hw/qcn9224/phyrx_he_sig_b2_mu.h new file mode 100644 index 000000000000..e42e51e0e547 --- /dev/null +++ b/hw/qcn9224/phyrx_he_sig_b2_mu.h @@ -0,0 +1,138 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _PHYRX_HE_SIG_B2_MU_H_ +#define _PHYRX_HE_SIG_B2_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b2_mu_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 2 + +#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_MU 1 + + +struct phyrx_he_sig_b2_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; +#else + struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; +#endif +}; + + + + + + + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + + + + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800 + + + + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 + + + + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000 + + + + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 + + + + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000 + + + + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000 + + + + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + + + + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 + + + + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 40 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 47 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 + + + + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 48 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 + + + +#endif diff --git a/hw/qcn9224/phyrx_he_sig_b2_ofdma.h b/hw/qcn9224/phyrx_he_sig_b2_ofdma.h new file mode 100644 index 000000000000..1b11b117f97a --- /dev/null +++ b/hw/qcn9224/phyrx_he_sig_b2_ofdma.h @@ -0,0 +1,138 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_ +#define _PHYRX_HE_SIG_B2_OFDMA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b2_ofdma_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 2 + +#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_OFDMA 1 + + +struct phyrx_he_sig_b2_ofdma { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; +#else + struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; +#endif +}; + + + + + + + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + + + + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800 + + + + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000 + + + + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 + + + + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000 + + + + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 + + + + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000 + + + + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + + + + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 + + + + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 40 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 47 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 + + + + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 48 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 + + + +#endif diff --git a/hw/qcn9224/phyrx_ht_sig.h b/hw/qcn9224/phyrx_ht_sig.h new file mode 100644 index 000000000000..79ca60b7df04 --- /dev/null +++ b/hw/qcn9224/phyrx_ht_sig.h @@ -0,0 +1,178 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _PHYRX_HT_SIG_H_ +#define _PHYRX_HT_SIG_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "ht_sig_info.h" +#define NUM_OF_DWORDS_PHYRX_HT_SIG 2 + +#define NUM_OF_QWORDS_PHYRX_HT_SIG 1 + + +struct phyrx_ht_sig { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct ht_sig_info phyrx_ht_sig_info_details; +#else + struct ht_sig_info phyrx_ht_sig_info_details; +#endif +}; + + + + + + + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB 0 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MSB 6 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f + + + + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB 7 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MSB 7 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080 + + + + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00 + + + + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 + + + + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000 + + + + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000 + + + + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000 + + + + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000 + + + + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB 36 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MSB 37 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000 + + + + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000 + + + + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000 + + + + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000 + + + + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB 42 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MSB 49 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 + + + + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000 + + + + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 + + + + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif diff --git a/hw/qcn9224/phyrx_l_sig_a.h b/hw/qcn9224/phyrx_l_sig_a.h new file mode 100644 index 000000000000..6c26a5433d33 --- /dev/null +++ b/hw/qcn9224/phyrx_l_sig_a.h @@ -0,0 +1,132 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _PHYRX_L_SIG_A_H_ +#define _PHYRX_L_SIG_A_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "l_sig_a_info.h" +#define NUM_OF_DWORDS_PHYRX_L_SIG_A 2 + +#define NUM_OF_QWORDS_PHYRX_L_SIG_A 1 + + +struct phyrx_l_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_a_info phyrx_l_sig_a_info_details; + uint32_t tlv64_padding : 32; +#else + struct l_sig_a_info phyrx_l_sig_a_info_details; + uint32_t tlv64_padding : 32; +#endif +}; + + + + + + + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MSB 3 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f + + + + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010 + + + + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0 + + + + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000 + + + + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000 + + + + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 + + + + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000 + + + + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000 + + + + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + + + + +#define PHYRX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_TLV64_PADDING_LSB 32 +#define PHYRX_L_SIG_A_TLV64_PADDING_MSB 63 +#define PHYRX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif diff --git a/hw/qcn9224/phyrx_l_sig_b.h b/hw/qcn9224/phyrx_l_sig_b.h new file mode 100644 index 000000000000..31fe35e4669b --- /dev/null +++ b/hw/qcn9224/phyrx_l_sig_b.h @@ -0,0 +1,92 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _PHYRX_L_SIG_B_H_ +#define _PHYRX_L_SIG_B_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "l_sig_b_info.h" +#define NUM_OF_DWORDS_PHYRX_L_SIG_B 2 + +#define NUM_OF_QWORDS_PHYRX_L_SIG_B 1 + + +struct phyrx_l_sig_b { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_b_info phyrx_l_sig_b_info_details; + uint32_t tlv64_padding : 32; +#else + struct l_sig_b_info phyrx_l_sig_b_info_details; + uint32_t tlv64_padding : 32; +#endif +}; + + + + + + + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f + + + + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0 + + + + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000 + + + + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + + + + +#define PHYRX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_B_TLV64_PADDING_LSB 32 +#define PHYRX_L_SIG_B_TLV64_PADDING_MSB 63 +#define PHYRX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif diff --git a/hw/qcn9224/phyrx_location.h b/hw/qcn9224/phyrx_location.h new file mode 100644 index 000000000000..7a949e1b159c --- /dev/null +++ b/hw/qcn9224/phyrx_location.h @@ -0,0 +1,554 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _PHYRX_LOCATION_H_ +#define _PHYRX_LOCATION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_location_info.h" +#define NUM_OF_DWORDS_PHYRX_LOCATION 28 + +#define NUM_OF_QWORDS_PHYRX_LOCATION 14 + + +struct phyrx_location { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_location_info rx_location_info_details; +#else + struct rx_location_info rx_location_info_details; +#endif +}; + + + + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x0000000000000001 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 1 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MSB 1 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x0000000000000002 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_LSB 2 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_MSB 3 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_MASK 0x000000000000000c + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_LSB 4 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MSB 7 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MASK 0x00000000000000f0 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_LSB 8 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MASK 0x000000000000ff00 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MSB 23 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x0000000000ff0000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_LSB 24 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MASK 0x00000000ff000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MSB 39 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff00000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_LSB 40 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff0000000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MSB 55 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00ff000000000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 56 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0xff00000000000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x0000000000000008 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0x00000000ffffffff + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000000000008 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 39 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff00000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 40 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x0000ff0000000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x0000000000000008 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MSB 51 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x000f000000000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x0000000000000008 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 52 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MSB 55 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x00f0000000000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x0000000000000008 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 56 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0xff00000000000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x0000000000000010 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x000000000000ffff + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x0000000000000010 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MSB 23 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000000000ff0000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x0000000000000010 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 24 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000000ff000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x0000000000000010 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff00000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_OFFSET 0x0000000000000018 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MASK 0x00000000ffffffff + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x0000000000000018 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff00000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MASK 0x000000000000ffff + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_OFFSET 0x0000000000000020 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MASK 0x00000000ffff0000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_OFFSET 0x0000000000000020 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MASK 0x0000ffff00000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_OFFSET 0x0000000000000020 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MASK 0xffff000000000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_OFFSET 0x0000000000000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MSB 7 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MASK 0x00000000000000ff + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x0000000000000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 8 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x000000000000ff00 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_OFFSET 0x0000000000000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MASK 0x00000000ffff0000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_OFFSET 0x0000000000000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MASK 0x0000ffff00000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_OFFSET 0x0000000000000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MASK 0xffff000000000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_OFFSET 0x0000000000000030 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MASK 0x000000000000ffff + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_OFFSET 0x0000000000000030 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MASK 0x00000000ffff0000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_OFFSET 0x0000000000000030 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MASK 0x0000ffff00000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_OFFSET 0x0000000000000030 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MASK 0xffff000000000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_OFFSET 0x0000000000000038 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MASK 0x000000000000ffff + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_OFFSET 0x0000000000000038 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MASK 0x00000000ffff0000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_OFFSET 0x0000000000000038 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MASK 0x0000ffff00000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_OFFSET 0x0000000000000038 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MASK 0xffff000000000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_OFFSET 0x0000000000000040 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MASK 0x000000000000ffff + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_OFFSET 0x0000000000000040 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MASK 0x00000000ffff0000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_OFFSET 0x0000000000000040 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MASK 0x0000ffff00000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_OFFSET 0x0000000000000040 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MASK 0xffff000000000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_OFFSET 0x0000000000000048 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MASK 0x000000000000ffff + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_OFFSET 0x0000000000000048 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MASK 0x00000000ffff0000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_OFFSET 0x0000000000000048 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MASK 0x0000ffff00000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_OFFSET 0x0000000000000048 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MASK 0xffff000000000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_OFFSET 0x0000000000000050 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MASK 0x000000000000ffff + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_OFFSET 0x0000000000000050 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MASK 0x00000000ffff0000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_OFFSET 0x0000000000000050 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MASK 0x0000ffff00000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_OFFSET 0x0000000000000050 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MASK 0xffff000000000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_OFFSET 0x0000000000000058 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MASK 0x000000000000ffff + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_OFFSET 0x0000000000000058 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MASK 0x00000000ffff0000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_OFFSET 0x0000000000000058 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MASK 0x0000ffff00000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_OFFSET 0x0000000000000058 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MASK 0xffff000000000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_OFFSET 0x0000000000000060 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MASK 0x000000000000ffff + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_OFFSET 0x0000000000000060 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MASK 0x00000000ffff0000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_OFFSET 0x0000000000000060 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MASK 0x0000ffff00000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_OFFSET 0x0000000000000060 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MASK 0xffff000000000000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_OFFSET 0x0000000000000068 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MASK 0x000000000000ffff + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_OFFSET 0x0000000000000068 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MASK 0x00000000ffff0000 + + + + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000000000000068 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MASK 0xffffffff00000000 + + + +#endif diff --git a/hw/qcn9224/phyrx_other_receive_info_ru_details.h b/hw/qcn9224/phyrx_other_receive_info_ru_details.h new file mode 100644 index 000000000000..c1aae2844103 --- /dev/null +++ b/hw/qcn9224/phyrx_other_receive_info_ru_details.h @@ -0,0 +1,84 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ +#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 4 + +#define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 2 + + +struct phyrx_other_receive_info_ru_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ru_details_channel_0 : 32; + uint32_t ru_details_channel_1 : 32; + uint32_t spare : 32; + uint32_t tlv64_padding : 32; +#else + uint32_t ru_details_channel_0 : 32; + uint32_t ru_details_channel_1 : 32; + uint32_t spare : 32; + uint32_t tlv64_padding : 32; +#endif +}; + + + + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_OFFSET 0x0000000000000008 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_OFFSET 0x0000000000000008 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif diff --git a/hw/qcn9224/phyrx_pkt_end.h b/hw/qcn9224/phyrx_pkt_end.h new file mode 100644 index 000000000000..f171a2390f7d --- /dev/null +++ b/hw/qcn9224/phyrx_pkt_end.h @@ -0,0 +1,704 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _PHYRX_PKT_END_H_ +#define _PHYRX_PKT_END_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phyrx_pkt_end_info.h" +#define NUM_OF_DWORDS_PHYRX_PKT_END 24 + +#define NUM_OF_QWORDS_PHYRX_PKT_END 12 + + +struct phyrx_pkt_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct phyrx_pkt_end_info rx_pkt_end_details; +#else + struct phyrx_pkt_end_info rx_pkt_end_details; +#endif +}; + + + + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_MSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_MASK 0x0000000000000001 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB 1 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MSB 1 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK 0x0000000000000002 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB 2 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MSB 2 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK 0x0000000000000004 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB 3 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MSB 3 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK 0x0000000000000008 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_LSB 4 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MSB 4 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MASK 0x0000000000000010 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MSB 5 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x0000000000000020 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_LSB 6 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MASK 0x00000000000000c0 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MASK 0x000000000000ff00 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MASK 0x00000000ffff0000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff00000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x0000000000000008 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0x00000000ffffffff + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000000000008 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff00000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000000000010 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0x00000000ffffffff + + + + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x0000000000000010 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 43 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff00000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000010 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 44 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff00000000000 + + + + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x0000000000000058 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK 0x00000000ffffffff + + + + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x0000000000000058 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff00000000 + + + +#endif diff --git a/hw/qcn9224/phyrx_pkt_end_info.h b/hw/qcn9224/phyrx_pkt_end_info.h new file mode 100644 index 000000000000..ea7cb254258c --- /dev/null +++ b/hw/qcn9224/phyrx_pkt_end_info.h @@ -0,0 +1,732 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _PHYRX_PKT_END_INFO_H_ +#define _PHYRX_PKT_END_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "receive_rssi_info.h" +#include "rx_timing_offset_info.h" +#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 24 + + +struct phyrx_pkt_end_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_internal_nap : 1, + location_info_valid : 1, + timing_info_valid : 1, + rssi_info_valid : 1, + reserved_0a : 1, + frameless_frame_received : 1, + reserved_0b : 2, + rssi_comb : 8, + reserved_0c : 16; + uint32_t phy_timestamp_1_lower_32 : 32; + uint32_t phy_timestamp_1_upper_32 : 32; + uint32_t phy_timestamp_2_lower_32 : 32; + uint32_t phy_timestamp_2_upper_32 : 32; + struct rx_timing_offset_info rx_timing_offset_info_details; + struct receive_rssi_info post_rssi_info_details; + uint32_t phy_sw_status_31_0 : 32; + uint32_t phy_sw_status_63_32 : 32; +#else + uint32_t reserved_0c : 16, + rssi_comb : 8, + reserved_0b : 2, + frameless_frame_received : 1, + reserved_0a : 1, + rssi_info_valid : 1, + timing_info_valid : 1, + location_info_valid : 1, + phy_internal_nap : 1; + uint32_t phy_timestamp_1_lower_32 : 32; + uint32_t phy_timestamp_1_upper_32 : 32; + uint32_t phy_timestamp_2_lower_32 : 32; + uint32_t phy_timestamp_2_upper_32 : 32; + struct rx_timing_offset_info rx_timing_offset_info_details; + struct receive_rssi_info post_rssi_info_details; + uint32_t phy_sw_status_31_0 : 32; + uint32_t phy_sw_status_63_32 : 32; +#endif +}; + + + + +#define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_MSB 0 +#define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_MASK 0x00000001 + + + + +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_LSB 1 +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MSB 1 +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MASK 0x00000002 + + + + +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_LSB 2 +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MSB 2 +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MASK 0x00000004 + + + + +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_LSB 3 +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MSB 3 +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MASK 0x00000008 + + + + +#define PHYRX_PKT_END_INFO_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RESERVED_0A_LSB 4 +#define PHYRX_PKT_END_INFO_RESERVED_0A_MSB 4 +#define PHYRX_PKT_END_INFO_RESERVED_0A_MASK 0x00000010 + + + + +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_LSB 5 +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MSB 5 +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 + + + + +#define PHYRX_PKT_END_INFO_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RESERVED_0B_LSB 6 +#define PHYRX_PKT_END_INFO_RESERVED_0B_MSB 7 +#define PHYRX_PKT_END_INFO_RESERVED_0B_MASK 0x000000c0 + + + + +#define PHYRX_PKT_END_INFO_RSSI_COMB_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RSSI_COMB_LSB 8 +#define PHYRX_PKT_END_INFO_RSSI_COMB_MSB 15 +#define PHYRX_PKT_END_INFO_RSSI_COMB_MASK 0x0000ff00 + + + + +#define PHYRX_PKT_END_INFO_RESERVED_0C_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RESERVED_0C_LSB 16 +#define PHYRX_PKT_END_INFO_RESERVED_0C_MSB 31 +#define PHYRX_PKT_END_INFO_RESERVED_0C_MASK 0xffff0000 + + + + +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff + + + + +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff + + + + +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff + + + + +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff + + + + + + + +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000014 +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 11 +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + + + + +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000014 +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12 +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MSB 31 +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000 + + + + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 + + + + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 + + + + +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_OFFSET 0x00000058 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MASK 0xffffffff + + + + +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_OFFSET 0x0000005c +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MASK 0xffffffff + + + +#endif diff --git a/hw/qcn9224/phyrx_rssi_legacy.h b/hw/qcn9224/phyrx_rssi_legacy.h new file mode 100644 index 000000000000..cb5734ba7a65 --- /dev/null +++ b/hw/qcn9224/phyrx_rssi_legacy.h @@ -0,0 +1,1299 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _PHYRX_RSSI_LEGACY_H_ +#define _PHYRX_RSSI_LEGACY_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "receive_rssi_info.h" +#define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 42 + +#define NUM_OF_QWORDS_PHYRX_RSSI_LEGACY 21 + + +struct phyrx_rssi_legacy { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reception_type : 4, + rx_chain_mask_type : 1, + receive_bandwidth : 3, + rx_chain_mask : 8, + phy_ppdu_id : 16; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t reserved_4a : 32; + uint32_t preamble_time_to_rxframe : 8, + standalone_snifer_mode : 1, + reserved_5a : 23; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + struct receive_rssi_info pre_rssi_info_details; + struct receive_rssi_info preamble_rssi_info_details; + uint32_t pre_rssi_comb : 8, + rssi_comb : 8, + normalized_pre_rssi_comb : 8, + normalized_rssi_comb : 8; + uint32_t rssi_comb_ppdu : 8, + rssi_db_to_dbm_offset : 8, + rssi_for_spatial_reuse : 8, + rssi_for_trigger_resp : 8; +#else + uint32_t phy_ppdu_id : 16, + rx_chain_mask : 8, + receive_bandwidth : 3, + rx_chain_mask_type : 1, + reception_type : 4; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 23, + standalone_snifer_mode : 1, + preamble_time_to_rxframe : 8; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + struct receive_rssi_info pre_rssi_info_details; + struct receive_rssi_info preamble_rssi_info_details; + uint32_t normalized_rssi_comb : 8, + normalized_pre_rssi_comb : 8, + rssi_comb : 8, + pre_rssi_comb : 8; + uint32_t rssi_for_trigger_resp : 8, + rssi_for_spatial_reuse : 8, + rssi_db_to_dbm_offset : 8, + rssi_comb_ppdu : 8; +#endif +}; + + + + +#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_OFFSET 0x0000000000000000 +#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_LSB 0 +#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_MSB 3 +#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_MASK 0x000000000000000f + + + + +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000000 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_LSB 4 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_MSB 4 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_MASK 0x0000000000000010 + + + + +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_LSB 5 +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MSB 7 +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MASK 0x00000000000000e0 + + + + +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_OFFSET 0x0000000000000000 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_LSB 8 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_MSB 15 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_MASK 0x000000000000ff00 + + + + +#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_LSB 16 +#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_MSB 31 +#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_MASK 0x00000000ffff0000 + + + + +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_OFFSET 0x0000000000000000 +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_LSB 32 +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MSB 63 +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MASK 0xffffffff00000000 + + + + +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000008 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff + + + + +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_LSB 32 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_MSB 63 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 + + + + +#define PHYRX_RSSI_LEGACY_RESERVED_4A_OFFSET 0x0000000000000010 +#define PHYRX_RSSI_LEGACY_RESERVED_4A_LSB 0 +#define PHYRX_RSSI_LEGACY_RESERVED_4A_MSB 31 +#define PHYRX_RSSI_LEGACY_RESERVED_4A_MASK 0x00000000ffffffff + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000010 +#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff00000000 + + + + +#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFER_MODE_OFFSET 0x0000000000000010 +#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFER_MODE_LSB 40 +#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFER_MODE_MSB 40 +#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFER_MODE_MASK 0x0000010000000000 + + + + +#define PHYRX_RSSI_LEGACY_RESERVED_5A_OFFSET 0x0000000000000010 +#define PHYRX_RSSI_LEGACY_RESERVED_5A_LSB 41 +#define PHYRX_RSSI_LEGACY_RESERVED_5A_MSB 63 +#define PHYRX_RSSI_LEGACY_RESERVED_5A_MASK 0xfffffe0000000000 + + + + +#define PHYRX_RSSI_LEGACY_RESERVED_6A_OFFSET 0x0000000000000018 +#define PHYRX_RSSI_LEGACY_RESERVED_6A_LSB 0 +#define PHYRX_RSSI_LEGACY_RESERVED_6A_MSB 31 +#define PHYRX_RSSI_LEGACY_RESERVED_6A_MASK 0x00000000ffffffff + + + + +#define PHYRX_RSSI_LEGACY_RESERVED_7A_OFFSET 0x0000000000000018 +#define PHYRX_RSSI_LEGACY_RESERVED_7A_LSB 32 +#define PHYRX_RSSI_LEGACY_RESERVED_7A_MSB 63 +#define PHYRX_RSSI_LEGACY_RESERVED_7A_MASK 0xffffffff00000000 + + + + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 + + + + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 + + + + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MASK 0x00000000000000ff + + + + +#define PHYRX_RSSI_LEGACY_RSSI_COMB_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_LSB 8 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_MSB 15 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_MASK 0x000000000000ff00 + + + + +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_LSB 16 +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MSB 23 +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000 + + + + +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_LSB 24 +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MSB 31 +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000 + + + + +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_LSB 32 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MSB 39 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MASK 0x000000ff00000000 + + + + +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_LSB 40 +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MSB 47 +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MASK 0x0000ff0000000000 + + + + +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_LSB 48 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MSB 55 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MASK 0x00ff000000000000 + + + + +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_LSB 56 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MSB 63 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MASK 0xff00000000000000 + + + +#endif diff --git a/hw/qcn9224/phyrx_vht_sig_a.h b/hw/qcn9224/phyrx_vht_sig_a.h new file mode 100644 index 000000000000..b07a288f3441 --- /dev/null +++ b/hw/qcn9224/phyrx_vht_sig_a.h @@ -0,0 +1,194 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _PHYRX_VHT_SIG_A_H_ +#define _PHYRX_VHT_SIG_A_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_a_info.h" +#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2 + +#define NUM_OF_QWORDS_PHYRX_VHT_SIG_A 1 + + +struct phyrx_vht_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_a_info phyrx_vht_sig_a_info_details; +#else + struct vht_sig_a_info phyrx_vht_sig_a_info_details; +#endif +}; + + + + + + + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003 + + + + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004 + + + + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008 + + + + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0 + + + + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00 + + + + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000 + + + + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000 + + + + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 + + + + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000 + + + + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000 + + + + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000 + + + + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000 + + + + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000 + + + + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000 + + + + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 + + + + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000 + + + + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 + + + + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif diff --git a/hw/qcn9224/receive_rssi_info.h b/hw/qcn9224/receive_rssi_info.h new file mode 100644 index 000000000000..fbac37d995b2 --- /dev/null +++ b/hw/qcn9224/receive_rssi_info.h @@ -0,0 +1,682 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RECEIVE_RSSI_INFO_H_ +#define _RECEIVE_RSSI_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16 + + +struct receive_rssi_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rssi_pri20_chain0 : 8, + rssi_ext20_chain0 : 8, + rssi_ext40_low20_chain0 : 8, + rssi_ext40_high20_chain0 : 8; + uint32_t rssi_ext80_low20_chain0 : 8, + rssi_ext80_low_high20_chain0 : 8, + rssi_ext80_high_low20_chain0 : 8, + rssi_ext80_high20_chain0 : 8; + uint32_t rssi_ext160_0_chain0 : 8, + rssi_ext160_1_chain0 : 8, + rssi_ext160_2_chain0 : 8, + rssi_ext160_3_chain0 : 8; + uint32_t rssi_ext160_4_chain0 : 8, + rssi_ext160_5_chain0 : 8, + rssi_ext160_6_chain0 : 8, + rssi_ext160_7_chain0 : 8; + uint32_t rssi_pri20_chain1 : 8, + rssi_ext20_chain1 : 8, + rssi_ext40_low20_chain1 : 8, + rssi_ext40_high20_chain1 : 8; + uint32_t rssi_ext80_low20_chain1 : 8, + rssi_ext80_low_high20_chain1 : 8, + rssi_ext80_high_low20_chain1 : 8, + rssi_ext80_high20_chain1 : 8; + uint32_t rssi_ext160_0_chain1 : 8, + rssi_ext160_1_chain1 : 8, + rssi_ext160_2_chain1 : 8, + rssi_ext160_3_chain1 : 8; + uint32_t rssi_ext160_4_chain1 : 8, + rssi_ext160_5_chain1 : 8, + rssi_ext160_6_chain1 : 8, + rssi_ext160_7_chain1 : 8; + uint32_t rssi_pri20_chain2 : 8, + rssi_ext20_chain2 : 8, + rssi_ext40_low20_chain2 : 8, + rssi_ext40_high20_chain2 : 8; + uint32_t rssi_ext80_low20_chain2 : 8, + rssi_ext80_low_high20_chain2 : 8, + rssi_ext80_high_low20_chain2 : 8, + rssi_ext80_high20_chain2 : 8; + uint32_t rssi_ext160_0_chain2 : 8, + rssi_ext160_1_chain2 : 8, + rssi_ext160_2_chain2 : 8, + rssi_ext160_3_chain2 : 8; + uint32_t rssi_ext160_4_chain2 : 8, + rssi_ext160_5_chain2 : 8, + rssi_ext160_6_chain2 : 8, + rssi_ext160_7_chain2 : 8; + uint32_t rssi_pri20_chain3 : 8, + rssi_ext20_chain3 : 8, + rssi_ext40_low20_chain3 : 8, + rssi_ext40_high20_chain3 : 8; + uint32_t rssi_ext80_low20_chain3 : 8, + rssi_ext80_low_high20_chain3 : 8, + rssi_ext80_high_low20_chain3 : 8, + rssi_ext80_high20_chain3 : 8; + uint32_t rssi_ext160_0_chain3 : 8, + rssi_ext160_1_chain3 : 8, + rssi_ext160_2_chain3 : 8, + rssi_ext160_3_chain3 : 8; + uint32_t rssi_ext160_4_chain3 : 8, + rssi_ext160_5_chain3 : 8, + rssi_ext160_6_chain3 : 8, + rssi_ext160_7_chain3 : 8; +#else + uint32_t rssi_ext40_high20_chain0 : 8, + rssi_ext40_low20_chain0 : 8, + rssi_ext20_chain0 : 8, + rssi_pri20_chain0 : 8; + uint32_t rssi_ext80_high20_chain0 : 8, + rssi_ext80_high_low20_chain0 : 8, + rssi_ext80_low_high20_chain0 : 8, + rssi_ext80_low20_chain0 : 8; + uint32_t rssi_ext160_3_chain0 : 8, + rssi_ext160_2_chain0 : 8, + rssi_ext160_1_chain0 : 8, + rssi_ext160_0_chain0 : 8; + uint32_t rssi_ext160_7_chain0 : 8, + rssi_ext160_6_chain0 : 8, + rssi_ext160_5_chain0 : 8, + rssi_ext160_4_chain0 : 8; + uint32_t rssi_ext40_high20_chain1 : 8, + rssi_ext40_low20_chain1 : 8, + rssi_ext20_chain1 : 8, + rssi_pri20_chain1 : 8; + uint32_t rssi_ext80_high20_chain1 : 8, + rssi_ext80_high_low20_chain1 : 8, + rssi_ext80_low_high20_chain1 : 8, + rssi_ext80_low20_chain1 : 8; + uint32_t rssi_ext160_3_chain1 : 8, + rssi_ext160_2_chain1 : 8, + rssi_ext160_1_chain1 : 8, + rssi_ext160_0_chain1 : 8; + uint32_t rssi_ext160_7_chain1 : 8, + rssi_ext160_6_chain1 : 8, + rssi_ext160_5_chain1 : 8, + rssi_ext160_4_chain1 : 8; + uint32_t rssi_ext40_high20_chain2 : 8, + rssi_ext40_low20_chain2 : 8, + rssi_ext20_chain2 : 8, + rssi_pri20_chain2 : 8; + uint32_t rssi_ext80_high20_chain2 : 8, + rssi_ext80_high_low20_chain2 : 8, + rssi_ext80_low_high20_chain2 : 8, + rssi_ext80_low20_chain2 : 8; + uint32_t rssi_ext160_3_chain2 : 8, + rssi_ext160_2_chain2 : 8, + rssi_ext160_1_chain2 : 8, + rssi_ext160_0_chain2 : 8; + uint32_t rssi_ext160_7_chain2 : 8, + rssi_ext160_6_chain2 : 8, + rssi_ext160_5_chain2 : 8, + rssi_ext160_4_chain2 : 8; + uint32_t rssi_ext40_high20_chain3 : 8, + rssi_ext40_low20_chain3 : 8, + rssi_ext20_chain3 : 8, + rssi_pri20_chain3 : 8; + uint32_t rssi_ext80_high20_chain3 : 8, + rssi_ext80_high_low20_chain3 : 8, + rssi_ext80_low_high20_chain3 : 8, + rssi_ext80_low20_chain3 : 8; + uint32_t rssi_ext160_3_chain3 : 8, + rssi_ext160_2_chain3 : 8, + rssi_ext160_1_chain3 : 8, + rssi_ext160_0_chain3 : 8; + uint32_t rssi_ext160_7_chain3 : 8, + rssi_ext160_6_chain3 : 8, + rssi_ext160_5_chain3 : 8, + rssi_ext160_4_chain3 : 8; +#endif +}; + + + + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MASK 0x000000ff + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MASK 0x000000ff + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MASK 0x000000ff + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MASK 0x000000ff + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 + + + + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 + + + +#endif diff --git a/hw/qcn9224/receive_user_info.h b/hw/qcn9224/receive_user_info.h new file mode 100644 index 000000000000..a657967f2fe4 --- /dev/null +++ b/hw/qcn9224/receive_user_info.h @@ -0,0 +1,392 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RECEIVE_USER_INFO_H_ +#define _RECEIVE_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RECEIVE_USER_INFO 8 + + +struct receive_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_ppdu_id : 16, + user_rssi : 8, + pkt_type : 4, + stbc : 1, + reception_type : 3; + uint32_t rate_mcs : 4, + sgi : 2, + he_ranging_ndp : 1, + reserved_1a : 1, + mimo_ss_bitmap : 8, + receive_bandwidth : 3, + reserved_1b : 5, + dl_ofdma_user_index : 8; + uint32_t dl_ofdma_content_channel : 1, + reserved_2a : 7, + nss : 3, + stream_offset : 3, + sta_dcm : 1, + ldpc : 1, + ru_type_80_0 : 4, + ru_type_80_1 : 4, + ru_type_80_2 : 4, + ru_type_80_3 : 4; + uint32_t ru_start_index_80_0 : 6, + reserved_3a : 2, + ru_start_index_80_1 : 6, + reserved_3b : 2, + ru_start_index_80_2 : 6, + reserved_3c : 2, + ru_start_index_80_3 : 6, + reserved_3d : 2; + uint32_t user_fd_rssi_seg0 : 32; + uint32_t user_fd_rssi_seg1 : 32; + uint32_t user_fd_rssi_seg2 : 32; + uint32_t user_fd_rssi_seg3 : 32; +#else + uint32_t reception_type : 3, + stbc : 1, + pkt_type : 4, + user_rssi : 8, + phy_ppdu_id : 16; + uint32_t dl_ofdma_user_index : 8, + reserved_1b : 5, + receive_bandwidth : 3, + mimo_ss_bitmap : 8, + reserved_1a : 1, + he_ranging_ndp : 1, + sgi : 2, + rate_mcs : 4; + uint32_t ru_type_80_3 : 4, + ru_type_80_2 : 4, + ru_type_80_1 : 4, + ru_type_80_0 : 4, + ldpc : 1, + sta_dcm : 1, + stream_offset : 3, + nss : 3, + reserved_2a : 7, + dl_ofdma_content_channel : 1; + uint32_t reserved_3d : 2, + ru_start_index_80_3 : 6, + reserved_3c : 2, + ru_start_index_80_2 : 6, + reserved_3b : 2, + ru_start_index_80_1 : 6, + reserved_3a : 2, + ru_start_index_80_0 : 6; + uint32_t user_fd_rssi_seg0 : 32; + uint32_t user_fd_rssi_seg1 : 32; + uint32_t user_fd_rssi_seg2 : 32; + uint32_t user_fd_rssi_seg3 : 32; +#endif +}; + + + + +#define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB 0 +#define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB 15 +#define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK 0x0000ffff + + + + +#define RECEIVE_USER_INFO_USER_RSSI_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_USER_RSSI_LSB 16 +#define RECEIVE_USER_INFO_USER_RSSI_MSB 23 +#define RECEIVE_USER_INFO_USER_RSSI_MASK 0x00ff0000 + + + + +#define RECEIVE_USER_INFO_PKT_TYPE_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_PKT_TYPE_LSB 24 +#define RECEIVE_USER_INFO_PKT_TYPE_MSB 27 +#define RECEIVE_USER_INFO_PKT_TYPE_MASK 0x0f000000 + + + + +#define RECEIVE_USER_INFO_STBC_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_STBC_LSB 28 +#define RECEIVE_USER_INFO_STBC_MSB 28 +#define RECEIVE_USER_INFO_STBC_MASK 0x10000000 + + + + +#define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB 29 +#define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB 31 +#define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK 0xe0000000 + + + + +#define RECEIVE_USER_INFO_RATE_MCS_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RATE_MCS_LSB 0 +#define RECEIVE_USER_INFO_RATE_MCS_MSB 3 +#define RECEIVE_USER_INFO_RATE_MCS_MASK 0x0000000f + + + + +#define RECEIVE_USER_INFO_SGI_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_SGI_LSB 4 +#define RECEIVE_USER_INFO_SGI_MSB 5 +#define RECEIVE_USER_INFO_SGI_MASK 0x00000030 + + + + +#define RECEIVE_USER_INFO_HE_RANGING_NDP_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_HE_RANGING_NDP_LSB 6 +#define RECEIVE_USER_INFO_HE_RANGING_NDP_MSB 6 +#define RECEIVE_USER_INFO_HE_RANGING_NDP_MASK 0x00000040 + + + + +#define RECEIVE_USER_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RESERVED_1A_LSB 7 +#define RECEIVE_USER_INFO_RESERVED_1A_MSB 7 +#define RECEIVE_USER_INFO_RESERVED_1A_MASK 0x00000080 + + + + +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB 8 +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB 15 +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK 0x0000ff00 + + + + +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB 16 +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB 18 +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK 0x00070000 + + + + +#define RECEIVE_USER_INFO_RESERVED_1B_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RESERVED_1B_LSB 19 +#define RECEIVE_USER_INFO_RESERVED_1B_MSB 23 +#define RECEIVE_USER_INFO_RESERVED_1B_MASK 0x00f80000 + + + + +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB 24 +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB 31 +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK 0xff000000 + + + + +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB 0 +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB 0 +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001 + + + + +#define RECEIVE_USER_INFO_RESERVED_2A_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RESERVED_2A_LSB 1 +#define RECEIVE_USER_INFO_RESERVED_2A_MSB 7 +#define RECEIVE_USER_INFO_RESERVED_2A_MASK 0x000000fe + + + + +#define RECEIVE_USER_INFO_NSS_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_NSS_LSB 8 +#define RECEIVE_USER_INFO_NSS_MSB 10 +#define RECEIVE_USER_INFO_NSS_MASK 0x00000700 + + + + +#define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_STREAM_OFFSET_LSB 11 +#define RECEIVE_USER_INFO_STREAM_OFFSET_MSB 13 +#define RECEIVE_USER_INFO_STREAM_OFFSET_MASK 0x00003800 + + + + +#define RECEIVE_USER_INFO_STA_DCM_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_STA_DCM_LSB 14 +#define RECEIVE_USER_INFO_STA_DCM_MSB 14 +#define RECEIVE_USER_INFO_STA_DCM_MASK 0x00004000 + + + + +#define RECEIVE_USER_INFO_LDPC_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_LDPC_LSB 15 +#define RECEIVE_USER_INFO_LDPC_MSB 15 +#define RECEIVE_USER_INFO_LDPC_MASK 0x00008000 + + + + +#define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB 16 +#define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB 19 +#define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK 0x000f0000 + + + + +#define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB 20 +#define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB 23 +#define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK 0x00f00000 + + + + +#define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB 24 +#define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB 27 +#define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK 0x0f000000 + + + + +#define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB 28 +#define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB 31 +#define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK 0xf0000000 + + + + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB 0 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB 5 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK 0x0000003f + + + + +#define RECEIVE_USER_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3A_LSB 6 +#define RECEIVE_USER_INFO_RESERVED_3A_MSB 7 +#define RECEIVE_USER_INFO_RESERVED_3A_MASK 0x000000c0 + + + + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB 8 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB 13 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK 0x00003f00 + + + + +#define RECEIVE_USER_INFO_RESERVED_3B_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3B_LSB 14 +#define RECEIVE_USER_INFO_RESERVED_3B_MSB 15 +#define RECEIVE_USER_INFO_RESERVED_3B_MASK 0x0000c000 + + + + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB 16 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB 21 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK 0x003f0000 + + + + +#define RECEIVE_USER_INFO_RESERVED_3C_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3C_LSB 22 +#define RECEIVE_USER_INFO_RESERVED_3C_MSB 23 +#define RECEIVE_USER_INFO_RESERVED_3C_MASK 0x00c00000 + + + + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB 24 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB 29 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK 0x3f000000 + + + + +#define RECEIVE_USER_INFO_RESERVED_3D_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3D_LSB 30 +#define RECEIVE_USER_INFO_RESERVED_3D_MSB 31 +#define RECEIVE_USER_INFO_RESERVED_3D_MASK 0xc0000000 + + + + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_OFFSET 0x00000010 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MASK 0xffffffff + + + + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_OFFSET 0x00000014 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MASK 0xffffffff + + + + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_OFFSET 0x00000018 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MASK 0xffffffff + + + + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_OFFSET 0x0000001c +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MASK 0xffffffff + + + +#endif diff --git a/hw/qcn9224/reo_descriptor_threshold_reached_status.h b/hw/qcn9224/reo_descriptor_threshold_reached_status.h new file mode 100644 index 000000000000..39219cce53a4 --- /dev/null +++ b/hw/qcn9224/reo_descriptor_threshold_reached_status.h @@ -0,0 +1,390 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ +#define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 26 + +#define NUM_OF_QWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 13 + + +struct reo_descriptor_threshold_reached_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t threshold_index : 2, + reserved_2 : 30; + uint32_t link_descriptor_counter0 : 24, + reserved_3 : 8; + uint32_t link_descriptor_counter1 : 24, + reserved_4 : 8; + uint32_t link_descriptor_counter2 : 24, + reserved_5 : 8; + uint32_t link_descriptor_counter_sum : 26, + reserved_6 : 6; + uint32_t reserved_7 : 32; + uint32_t reserved_8 : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2 : 30, + threshold_index : 2; + uint32_t reserved_3 : 8, + link_descriptor_counter0 : 24; + uint32_t reserved_4 : 8, + link_descriptor_counter1 : 24; + uint32_t reserved_5 : 8, + link_descriptor_counter2 : 24; + uint32_t reserved_6 : 6, + link_descriptor_counter_sum : 26; + uint32_t reserved_7 : 32; + uint32_t reserved_8 : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + + + + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_OFFSET 0x0000000000000008 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MSB 1 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MASK 0x0000000000000003 + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_OFFSET 0x0000000000000008 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_LSB 2 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MASK 0x00000000fffffffc + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x0000000000000008 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MSB 55 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff00000000 + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_OFFSET 0x0000000000000008 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_LSB 56 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MASK 0xff00000000000000 + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x0000000000000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MSB 23 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MASK 0x0000000000ffffff + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_OFFSET 0x0000000000000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_LSB 24 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MASK 0x00000000ff000000 + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x0000000000000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MSB 55 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff00000000 + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_OFFSET 0x0000000000000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_LSB 56 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MASK 0xff00000000000000 + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x0000000000000018 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MSB 25 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x0000000003ffffff + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_OFFSET 0x0000000000000018 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_LSB 26 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MASK 0x00000000fc000000 + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_OFFSET 0x0000000000000018 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MASK 0xffffffff00000000 + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_OFFSET 0x0000000000000020 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MASK 0x00000000ffffffff + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MASK 0xffffffff00000000 + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MASK 0x00000000ffffffff + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MASK 0xffffffff00000000 + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MASK 0x00000000ffffffff + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MASK 0xffffffff00000000 + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MASK 0x00000000ffffffff + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MASK 0xffffffff00000000 + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MASK 0x00000000ffffffff + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MASK 0xffffffff00000000 + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MASK 0x00000000ffffffff + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MASK 0xffffffff00000000 + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MASK 0x00000000ffffffff + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MASK 0xffffffff00000000 + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MASK 0x00000000ffffffff + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MASK 0xffffffff00000000 + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MASK 0x00000000ffffffff + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MSB 59 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 + + + + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_LSB 60 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + + + +#endif diff --git a/hw/qcn9224/reo_destination_ring.h b/hw/qcn9224/reo_destination_ring.h new file mode 100644 index 000000000000..2480dceec4ed --- /dev/null +++ b/hw/qcn9224/reo_destination_ring.h @@ -0,0 +1,434 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _REO_DESTINATION_RING_H_ +#define _REO_DESTINATION_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_msdu_desc_info.h" +#include "rx_mpdu_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_REO_DESTINATION_RING 8 + + +struct reo_destination_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buf_or_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t reo_dest_buffer_type : 1, + reo_push_reason : 2, + reo_error_code : 5, + captured_msdu_data_size : 4, + sw_exception : 1, + src_link_id : 3, + reo_destination_struct_signature : 4, + ring_id : 8, + looping_count : 4; +#else + struct buffer_addr_info buf_or_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t looping_count : 4, + ring_id : 8, + reo_destination_struct_signature : 4, + src_link_id : 3, + sw_exception : 1, + captured_msdu_data_size : 4, + reo_error_code : 5, + reo_push_reason : 2, + reo_dest_buffer_type : 1; +#endif +}; + + + + + + + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + + + + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + + + + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + + + + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + + + + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + + + + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + + + + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + + + + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + + + + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + + + + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + + + + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + + + + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + + + + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + + + + + + + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + + + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + + + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + + + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + + + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + + + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + + + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + + + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + + + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + + + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + + + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + + + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + + + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + + + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + + + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + + + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + + + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000 + + + + +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000014 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + + + + +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000018 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + + + + +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_LSB 0 +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MSB 0 +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MASK 0x00000001 + + + + +#define REO_DESTINATION_RING_REO_PUSH_REASON_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_PUSH_REASON_LSB 1 +#define REO_DESTINATION_RING_REO_PUSH_REASON_MSB 2 +#define REO_DESTINATION_RING_REO_PUSH_REASON_MASK 0x00000006 + + + + +#define REO_DESTINATION_RING_REO_ERROR_CODE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_ERROR_CODE_LSB 3 +#define REO_DESTINATION_RING_REO_ERROR_CODE_MSB 7 +#define REO_DESTINATION_RING_REO_ERROR_CODE_MASK 0x000000f8 + + + + +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_LSB 8 +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MSB 11 +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00 + + + + +#define REO_DESTINATION_RING_SW_EXCEPTION_OFFSET 0x0000001c +#define REO_DESTINATION_RING_SW_EXCEPTION_LSB 12 +#define REO_DESTINATION_RING_SW_EXCEPTION_MSB 12 +#define REO_DESTINATION_RING_SW_EXCEPTION_MASK 0x00001000 + + + + +#define REO_DESTINATION_RING_SRC_LINK_ID_OFFSET 0x0000001c +#define REO_DESTINATION_RING_SRC_LINK_ID_LSB 13 +#define REO_DESTINATION_RING_SRC_LINK_ID_MSB 15 +#define REO_DESTINATION_RING_SRC_LINK_ID_MASK 0x0000e000 + + + + +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16 +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19 +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000 + + + + +#define REO_DESTINATION_RING_RING_ID_OFFSET 0x0000001c +#define REO_DESTINATION_RING_RING_ID_LSB 20 +#define REO_DESTINATION_RING_RING_ID_MSB 27 +#define REO_DESTINATION_RING_RING_ID_MASK 0x0ff00000 + + + + +#define REO_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define REO_DESTINATION_RING_LOOPING_COUNT_LSB 28 +#define REO_DESTINATION_RING_LOOPING_COUNT_MSB 31 +#define REO_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif diff --git a/hw/qcn9224/reo_entrance_ring.h b/hw/qcn9224/reo_entrance_ring.h new file mode 100644 index 000000000000..e82291a62fd8 --- /dev/null +++ b/hw/qcn9224/reo_entrance_ring.h @@ -0,0 +1,382 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _REO_ENTRANCE_RING_H_ +#define _REO_ENTRANCE_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_details.h" +#define NUM_OF_DWORDS_REO_ENTRANCE_RING 8 + + +struct reo_entrance_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_mpdu_details reo_level_mpdu_frame_info; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + rounded_mpdu_byte_count : 14, + reo_destination_indication : 5, + frameless_bar : 1, + reserved_5a : 4; + uint32_t rxdma_push_reason : 2, + rxdma_error_code : 5, + mpdu_fragment_number : 4, + sw_exception : 1, + sw_exception_mpdu_delink : 1, + sw_exception_destination_ring_valid : 1, + sw_exception_destination_ring : 5, + mpdu_sequence_number : 12, + reserved_6a : 1; + uint32_t phy_ppdu_id : 16, + src_link_id : 3, + reserved_7a : 1, + ring_id : 8, + looping_count : 4; +#else + struct rx_mpdu_details reo_level_mpdu_frame_info; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t reserved_5a : 4, + frameless_bar : 1, + reo_destination_indication : 5, + rounded_mpdu_byte_count : 14, + rx_reo_queue_desc_addr_39_32 : 8; + uint32_t reserved_6a : 1, + mpdu_sequence_number : 12, + sw_exception_destination_ring : 5, + sw_exception_destination_ring_valid : 1, + sw_exception_mpdu_delink : 1, + sw_exception : 1, + mpdu_fragment_number : 4, + rxdma_error_code : 5, + rxdma_push_reason : 2; + uint32_t looping_count : 4, + ring_id : 8, + reserved_7a : 1, + src_link_id : 3, + phy_ppdu_id : 16; +#endif +}; + + + + + + + + + + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + + + + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + + + + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + + + + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + + + + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + + + + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + + + + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + + + + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + + + + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + + + + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + + + + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + + + + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + + + + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + + + + +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + + + + +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + + + + +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_LSB 8 +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MSB 21 +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 + + + + +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_LSB 22 +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MSB 26 +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MASK 0x07c00000 + + + + +#define REO_ENTRANCE_RING_FRAMELESS_BAR_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_FRAMELESS_BAR_LSB 27 +#define REO_ENTRANCE_RING_FRAMELESS_BAR_MSB 27 +#define REO_ENTRANCE_RING_FRAMELESS_BAR_MASK 0x08000000 + + + + +#define REO_ENTRANCE_RING_RESERVED_5A_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_RESERVED_5A_LSB 28 +#define REO_ENTRANCE_RING_RESERVED_5A_MSB 31 +#define REO_ENTRANCE_RING_RESERVED_5A_MASK 0xf0000000 + + + + +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB 0 +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MSB 1 +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK 0x00000003 + + + + +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB 2 +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MSB 6 +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK 0x0000007c + + + + +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_LSB 7 +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MSB 10 +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 + + + + +#define REO_ENTRANCE_RING_SW_EXCEPTION_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_LSB 11 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MSB 11 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MASK 0x00000800 + + + + +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_LSB 12 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MSB 12 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000 + + + + +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MSB 13 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000 + + + + +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_LSB 14 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MSB 18 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000 + + + + +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_LSB 19 +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MSB 30 +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MASK 0x7ff80000 + + + + +#define REO_ENTRANCE_RING_RESERVED_6A_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_RESERVED_6A_LSB 31 +#define REO_ENTRANCE_RING_RESERVED_6A_MSB 31 +#define REO_ENTRANCE_RING_RESERVED_6A_MASK 0x80000000 + + + + +#define REO_ENTRANCE_RING_PHY_PPDU_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_PHY_PPDU_ID_LSB 0 +#define REO_ENTRANCE_RING_PHY_PPDU_ID_MSB 15 +#define REO_ENTRANCE_RING_PHY_PPDU_ID_MASK 0x0000ffff + + + + +#define REO_ENTRANCE_RING_SRC_LINK_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_SRC_LINK_ID_LSB 16 +#define REO_ENTRANCE_RING_SRC_LINK_ID_MSB 18 +#define REO_ENTRANCE_RING_SRC_LINK_ID_MASK 0x00070000 + + + + +#define REO_ENTRANCE_RING_RESERVED_7A_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_RESERVED_7A_LSB 19 +#define REO_ENTRANCE_RING_RESERVED_7A_MSB 19 +#define REO_ENTRANCE_RING_RESERVED_7A_MASK 0x00080000 + + + + +#define REO_ENTRANCE_RING_RING_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_RING_ID_LSB 20 +#define REO_ENTRANCE_RING_RING_ID_MSB 27 +#define REO_ENTRANCE_RING_RING_ID_MASK 0x0ff00000 + + + + +#define REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_LOOPING_COUNT_LSB 28 +#define REO_ENTRANCE_RING_LOOPING_COUNT_MSB 31 +#define REO_ENTRANCE_RING_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif diff --git a/hw/qcn9224/reo_flush_cache.h b/hw/qcn9224/reo_flush_cache.h new file mode 100644 index 000000000000..5616a53b79c3 --- /dev/null +++ b/hw/qcn9224/reo_flush_cache.h @@ -0,0 +1,244 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _REO_FLUSH_CACHE_H_ +#define _REO_FLUSH_CACHE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_CACHE 10 + +#define NUM_OF_QWORDS_REO_FLUSH_CACHE 5 + + +struct reo_flush_cache { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_addr_31_0 : 32; + uint32_t flush_addr_39_32 : 8, + forward_all_mpdus_in_queue : 1, + release_cache_block_index : 1, + cache_block_resource_index : 2, + flush_without_invalidate : 1, + block_cache_usage_after_flush : 1, + flush_entire_cache : 1, + flush_queue_1k_desc : 1, + reserved_2b : 16; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t tlv64_padding : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_addr_31_0 : 32; + uint32_t reserved_2b : 16, + flush_queue_1k_desc : 1, + flush_entire_cache : 1, + block_cache_usage_after_flush : 1, + flush_without_invalidate : 1, + cache_block_resource_index : 2, + release_cache_block_index : 1, + forward_all_mpdus_in_queue : 1, + flush_addr_39_32 : 8; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t tlv64_padding : 32; +#endif +}; + + + + + + + +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff + + + + +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 + + + + +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 + + + + +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_LSB 32 +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MSB 63 +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_LSB 0 +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MSB 7 +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MASK 0x00000000000000ff + + + + +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8 +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MSB 8 +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x0000000000000100 + + + + +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_LSB 9 +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MSB 9 +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MASK 0x0000000000000200 + + + + +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 10 +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 11 +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000c00 + + + + +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_LSB 12 +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MSB 12 +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MASK 0x0000000000001000 + + + + +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13 +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MSB 13 +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x0000000000002000 + + + + +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_LSB 14 +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MSB 14 +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MASK 0x0000000000004000 + + + + +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_LSB 15 +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MSB 15 +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MASK 0x0000000000008000 + + + + +#define REO_FLUSH_CACHE_RESERVED_2B_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_RESERVED_2B_LSB 16 +#define REO_FLUSH_CACHE_RESERVED_2B_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_2B_MASK 0x00000000ffff0000 + + + + +#define REO_FLUSH_CACHE_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_RESERVED_3A_LSB 32 +#define REO_FLUSH_CACHE_RESERVED_3A_MSB 63 +#define REO_FLUSH_CACHE_RESERVED_3A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_CACHE_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_FLUSH_CACHE_RESERVED_4A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_4A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_4A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_CACHE_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_FLUSH_CACHE_RESERVED_5A_LSB 32 +#define REO_FLUSH_CACHE_RESERVED_5A_MSB 63 +#define REO_FLUSH_CACHE_RESERVED_5A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_CACHE_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_FLUSH_CACHE_RESERVED_6A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_6A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_6A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_CACHE_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_FLUSH_CACHE_RESERVED_7A_LSB 32 +#define REO_FLUSH_CACHE_RESERVED_7A_MSB 63 +#define REO_FLUSH_CACHE_RESERVED_7A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_CACHE_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_FLUSH_CACHE_RESERVED_8A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_8A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_8A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020 +#define REO_FLUSH_CACHE_TLV64_PADDING_LSB 32 +#define REO_FLUSH_CACHE_TLV64_PADDING_MSB 63 +#define REO_FLUSH_CACHE_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif diff --git a/hw/qcn9224/reo_flush_cache_status.h b/hw/qcn9224/reo_flush_cache_status.h new file mode 100644 index 000000000000..c19ea8dd5dd2 --- /dev/null +++ b/hw/qcn9224/reo_flush_cache_status.h @@ -0,0 +1,430 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _REO_FLUSH_CACHE_STATUS_H_ +#define _REO_FLUSH_CACHE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 26 + +#define NUM_OF_QWORDS_REO_FLUSH_CACHE_STATUS 13 + + +struct reo_flush_cache_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + block_error_details : 2, + reserved_2a : 5, + cache_controller_flush_status_hit : 1, + cache_controller_flush_status_desc_type : 3, + cache_controller_flush_status_client_id : 4, + cache_controller_flush_status_error : 2, + cache_controller_flush_count : 8, + flush_queue_1k_desc : 1, + reserved_2b : 5; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2b : 5, + flush_queue_1k_desc : 1, + cache_controller_flush_count : 8, + cache_controller_flush_status_error : 2, + cache_controller_flush_status_client_id : 4, + cache_controller_flush_status_desc_type : 3, + cache_controller_flush_status_hit : 1, + reserved_2a : 5, + block_error_details : 2, + error_detected : 1; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + + + + + + + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + + + + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + + + + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + + + + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + + + + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MSB 0 +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 + + + + +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_LSB 1 +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MSB 2 +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MASK 0x0000000000000006 + + + + +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_LSB 3 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MSB 7 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MASK 0x00000000000000f8 + + + + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MSB 8 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x0000000000000100 + + + + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MSB 11 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x0000000000000e00 + + + + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MSB 15 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x000000000000f000 + + + + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MSB 17 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x0000000000030000 + + + + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MSB 25 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x0000000003fc0000 + + + + +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_LSB 26 +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MSB 26 +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MASK 0x0000000004000000 + + + + +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_LSB 27 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MASK 0x00000000f8000000 + + + + +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MSB 59 +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 + + + + +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_LSB 60 +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MSB 63 +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + + + +#endif diff --git a/hw/qcn9224/reo_flush_queue.h b/hw/qcn9224/reo_flush_queue.h new file mode 100644 index 000000000000..4c1014d48cfd --- /dev/null +++ b/hw/qcn9224/reo_flush_queue.h @@ -0,0 +1,194 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _REO_FLUSH_QUEUE_H_ +#define _REO_FLUSH_QUEUE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 10 + +#define NUM_OF_QWORDS_REO_FLUSH_QUEUE 5 + + +struct reo_flush_queue { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_desc_addr_31_0 : 32; + uint32_t flush_desc_addr_39_32 : 8, + block_desc_addr_usage_after_flush : 1, + block_resource_index : 2, + reserved_2a : 21; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t tlv64_padding : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_desc_addr_31_0 : 32; + uint32_t reserved_2a : 21, + block_resource_index : 2, + block_desc_addr_usage_after_flush : 1, + flush_desc_addr_39_32 : 8; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t tlv64_padding : 32; +#endif +}; + + + + + + + +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff + + + + +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 + + + + +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 + + + + +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB 32 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB 63 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB 0 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB 7 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK 0x00000000000000ff + + + + +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8 +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB 8 +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x0000000000000100 + + + + +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB 9 +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB 10 +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000600 + + + + +#define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_RESERVED_2A_LSB 11 +#define REO_FLUSH_QUEUE_RESERVED_2A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_2A_MASK 0x00000000fffff800 + + + + +#define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_RESERVED_3A_LSB 32 +#define REO_FLUSH_QUEUE_RESERVED_3A_MSB 63 +#define REO_FLUSH_QUEUE_RESERVED_3A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_FLUSH_QUEUE_RESERVED_4A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_4A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_4A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_FLUSH_QUEUE_RESERVED_5A_LSB 32 +#define REO_FLUSH_QUEUE_RESERVED_5A_MSB 63 +#define REO_FLUSH_QUEUE_RESERVED_5A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_FLUSH_QUEUE_RESERVED_6A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_6A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_6A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_FLUSH_QUEUE_RESERVED_7A_LSB 32 +#define REO_FLUSH_QUEUE_RESERVED_7A_MSB 63 +#define REO_FLUSH_QUEUE_RESERVED_7A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_FLUSH_QUEUE_RESERVED_8A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_8A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_8A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020 +#define REO_FLUSH_QUEUE_TLV64_PADDING_LSB 32 +#define REO_FLUSH_QUEUE_TLV64_PADDING_MSB 63 +#define REO_FLUSH_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif diff --git a/hw/qcn9224/reo_flush_queue_status.h b/hw/qcn9224/reo_flush_queue_status.h new file mode 100644 index 000000000000..fa20063aa7e2 --- /dev/null +++ b/hw/qcn9224/reo_flush_queue_status.h @@ -0,0 +1,350 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _REO_FLUSH_QUEUE_STATUS_H_ +#define _REO_FLUSH_QUEUE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 26 + +#define NUM_OF_QWORDS_REO_FLUSH_QUEUE_STATUS 13 + + +struct reo_flush_queue_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + reserved_2a : 31; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 31, + error_detected : 1; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + + + + + + + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + + + + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + + + + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + + + + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + + + + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MSB 0 +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 + + + + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_LSB 1 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MASK 0x00000000fffffffe + + + + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MSB 59 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 + + + + +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_LSB 60 +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + + + +#endif diff --git a/hw/qcn9224/reo_flush_timeout_list.h b/hw/qcn9224/reo_flush_timeout_list.h new file mode 100644 index 000000000000..0dcfb166aba0 --- /dev/null +++ b/hw/qcn9224/reo_flush_timeout_list.h @@ -0,0 +1,184 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _REO_FLUSH_TIMEOUT_LIST_H_ +#define _REO_FLUSH_TIMEOUT_LIST_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 10 + +#define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST 5 + + +struct reo_flush_timeout_list { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t ac_timout_list : 2, + reserved_1 : 30; + uint32_t minimum_release_desc_count : 16, + minimum_forward_buf_count : 16; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t tlv64_padding : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t reserved_1 : 30, + ac_timout_list : 2; + uint32_t minimum_forward_buf_count : 16, + minimum_release_desc_count : 16; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t tlv64_padding : 32; +#endif +}; + + + + + + + +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff + + + + +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 + + + + +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 + + + + +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MSB 33 +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MASK 0x0000000300000000 + + + + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_LSB 34 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MASK 0xfffffffc00000000 + + + + +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MSB 15 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MASK 0x000000000000ffff + + + + +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MASK 0x00000000ffff0000 + + + + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_OFFSET 0x0000000000000020 +#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif diff --git a/hw/qcn9224/reo_flush_timeout_list_status.h b/hw/qcn9224/reo_flush_timeout_list_status.h new file mode 100644 index 000000000000..511928561f0a --- /dev/null +++ b/hw/qcn9224/reo_flush_timeout_list_status.h @@ -0,0 +1,370 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ +#define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 26 + +#define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 13 + + +struct reo_flush_timeout_list_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + timout_list_empty : 1, + reserved_2a : 30; + uint32_t release_desc_count : 16, + forward_buf_count : 16; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 30, + timout_list_empty : 1, + error_detected : 1; + uint32_t forward_buf_count : 16, + release_desc_count : 16; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + + + + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_LSB 1 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MSB 1 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MASK 0x0000000000000002 + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_LSB 2 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MASK 0x00000000fffffffc + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MSB 47 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MASK 0x0000ffff00000000 + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_LSB 48 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MASK 0xffff000000000000 + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MASK 0xffffffff00000000 + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MASK 0x00000000ffffffff + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MSB 59 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 + + + + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_LSB 60 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + + + +#endif diff --git a/hw/qcn9224/reo_get_queue_stats.h b/hw/qcn9224/reo_get_queue_stats.h new file mode 100644 index 000000000000..9c84fbda34ae --- /dev/null +++ b/hw/qcn9224/reo_get_queue_stats.h @@ -0,0 +1,184 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _REO_GET_QUEUE_STATS_H_ +#define _REO_GET_QUEUE_STATS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 10 + +#define NUM_OF_QWORDS_REO_GET_QUEUE_STATS 5 + + +struct reo_get_queue_stats { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + clear_stats : 1, + reserved_2a : 23; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t tlv64_padding : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t reserved_2a : 23, + clear_stats : 1, + rx_reo_queue_desc_addr_39_32 : 8; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t tlv64_padding : 32; +#endif +}; + + + + + + + +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff + + + + +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 + + + + +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 + + + + +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000 + + + + +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff + + + + +#define REO_GET_QUEUE_STATS_CLEAR_STATS_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_CLEAR_STATS_LSB 8 +#define REO_GET_QUEUE_STATS_CLEAR_STATS_MSB 8 +#define REO_GET_QUEUE_STATS_CLEAR_STATS_MASK 0x0000000000000100 + + + + +#define REO_GET_QUEUE_STATS_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_RESERVED_2A_LSB 9 +#define REO_GET_QUEUE_STATS_RESERVED_2A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_2A_MASK 0x00000000fffffe00 + + + + +#define REO_GET_QUEUE_STATS_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_RESERVED_3A_LSB 32 +#define REO_GET_QUEUE_STATS_RESERVED_3A_MSB 63 +#define REO_GET_QUEUE_STATS_RESERVED_3A_MASK 0xffffffff00000000 + + + + +#define REO_GET_QUEUE_STATS_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_GET_QUEUE_STATS_RESERVED_4A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_4A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_4A_MASK 0x00000000ffffffff + + + + +#define REO_GET_QUEUE_STATS_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_GET_QUEUE_STATS_RESERVED_5A_LSB 32 +#define REO_GET_QUEUE_STATS_RESERVED_5A_MSB 63 +#define REO_GET_QUEUE_STATS_RESERVED_5A_MASK 0xffffffff00000000 + + + + +#define REO_GET_QUEUE_STATS_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_GET_QUEUE_STATS_RESERVED_6A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_6A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_6A_MASK 0x00000000ffffffff + + + + +#define REO_GET_QUEUE_STATS_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_GET_QUEUE_STATS_RESERVED_7A_LSB 32 +#define REO_GET_QUEUE_STATS_RESERVED_7A_MSB 63 +#define REO_GET_QUEUE_STATS_RESERVED_7A_MASK 0xffffffff00000000 + + + + +#define REO_GET_QUEUE_STATS_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_GET_QUEUE_STATS_RESERVED_8A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_8A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_8A_MASK 0x00000000ffffffff + + + + +#define REO_GET_QUEUE_STATS_TLV64_PADDING_OFFSET 0x0000000000000020 +#define REO_GET_QUEUE_STATS_TLV64_PADDING_LSB 32 +#define REO_GET_QUEUE_STATS_TLV64_PADDING_MSB 63 +#define REO_GET_QUEUE_STATS_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif diff --git a/hw/qcn9224/reo_get_queue_stats_status.h b/hw/qcn9224/reo_get_queue_stats_status.h new file mode 100644 index 000000000000..b4481d87755e --- /dev/null +++ b/hw/qcn9224/reo_get_queue_stats_status.h @@ -0,0 +1,460 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _REO_GET_QUEUE_STATS_STATUS_H_ +#define _REO_GET_QUEUE_STATS_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS_STATUS 26 + +#define NUM_OF_QWORDS_REO_GET_QUEUE_STATS_STATUS 13 + + +struct reo_get_queue_stats_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t ssn : 12, + current_index : 10, + reserved_2 : 10; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t last_rx_enqueue_timestamp : 32; + uint32_t last_rx_dequeue_timestamp : 32; + uint32_t rx_bitmap_31_0 : 32; + uint32_t rx_bitmap_63_32 : 32; + uint32_t rx_bitmap_95_64 : 32; + uint32_t rx_bitmap_127_96 : 32; + uint32_t rx_bitmap_159_128 : 32; + uint32_t rx_bitmap_191_160 : 32; + uint32_t rx_bitmap_223_192 : 32; + uint32_t rx_bitmap_255_224 : 32; + uint32_t rx_bitmap_287_256 : 32; + uint32_t current_mpdu_count : 7, + current_msdu_count : 25; + uint32_t window_jump_2k : 4, + timeout_count : 6, + forward_due_to_bar_count : 6, + duplicate_count : 16; + uint32_t frames_in_order_count : 24, + bar_received_count : 8; + uint32_t mpdu_frames_processed_count : 32; + uint32_t msdu_frames_processed_count : 32; + uint32_t total_processed_byte_count : 32; + uint32_t late_receive_mpdu_count : 12, + hole_count : 16, + get_queue_1k_stats_status_to_follow : 1, + reserved_24a : 3; + uint32_t aging_drop_mpdu_count : 16, + aging_drop_interval : 8, + reserved_25a : 4, + looping_count : 4; +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2 : 10, + current_index : 10, + ssn : 12; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t last_rx_enqueue_timestamp : 32; + uint32_t last_rx_dequeue_timestamp : 32; + uint32_t rx_bitmap_31_0 : 32; + uint32_t rx_bitmap_63_32 : 32; + uint32_t rx_bitmap_95_64 : 32; + uint32_t rx_bitmap_127_96 : 32; + uint32_t rx_bitmap_159_128 : 32; + uint32_t rx_bitmap_191_160 : 32; + uint32_t rx_bitmap_223_192 : 32; + uint32_t rx_bitmap_255_224 : 32; + uint32_t rx_bitmap_287_256 : 32; + uint32_t current_msdu_count : 25, + current_mpdu_count : 7; + uint32_t duplicate_count : 16, + forward_due_to_bar_count : 6, + timeout_count : 6, + window_jump_2k : 4; + uint32_t bar_received_count : 8, + frames_in_order_count : 24; + uint32_t mpdu_frames_processed_count : 32; + uint32_t msdu_frames_processed_count : 32; + uint32_t total_processed_byte_count : 32; + uint32_t reserved_24a : 3, + get_queue_1k_stats_status_to_follow : 1, + hole_count : 16, + late_receive_mpdu_count : 12; + uint32_t looping_count : 4, + reserved_25a : 4, + aging_drop_interval : 8, + aging_drop_mpdu_count : 16; +#endif +}; + + + + + + + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + + + + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + + + + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + + + + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + + + + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + + + + +#define REO_GET_QUEUE_STATS_STATUS_SSN_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_STATUS_SSN_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_SSN_MSB 11 +#define REO_GET_QUEUE_STATS_STATUS_SSN_MASK 0x0000000000000fff + + + + +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_LSB 12 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MSB 21 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MASK 0x00000000003ff000 + + + + +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_LSB 22 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MASK 0x00000000ffc00000 + + + + +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MASK 0xffffffff00000000 + + + + +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_OFFSET 0x0000000000000010 +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MASK 0x00000000ffffffff + + + + +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_OFFSET 0x0000000000000010 +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MASK 0xffffffff00000000 + + + + +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_OFFSET 0x0000000000000018 +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MASK 0x00000000ffffffff + + + + +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x0000000000000018 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff00000000 + + + + +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x0000000000000020 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0x00000000ffffffff + + + + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_OFFSET 0x0000000000000020 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MASK 0xffffffff00000000 + + + + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_OFFSET 0x0000000000000028 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MASK 0x00000000ffffffff + + + + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_OFFSET 0x0000000000000028 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MASK 0xffffffff00000000 + + + + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_OFFSET 0x0000000000000030 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MASK 0x00000000ffffffff + + + + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_OFFSET 0x0000000000000030 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MASK 0xffffffff00000000 + + + + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_OFFSET 0x0000000000000038 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MASK 0x00000000ffffffff + + + + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_OFFSET 0x0000000000000038 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MASK 0xffffffff00000000 + + + + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_OFFSET 0x0000000000000040 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MASK 0x00000000ffffffff + + + + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_OFFSET 0x0000000000000040 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MASK 0xffffffff00000000 + + + + +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_OFFSET 0x0000000000000048 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MSB 6 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MASK 0x000000000000007f + + + + +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_OFFSET 0x0000000000000048 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_LSB 7 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MASK 0x00000000ffffff80 + + + + +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_OFFSET 0x0000000000000048 +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MSB 35 +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MASK 0x0000000f00000000 + + + + +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_OFFSET 0x0000000000000048 +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_LSB 36 +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MSB 41 +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MASK 0x000003f000000000 + + + + +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x0000000000000048 +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_LSB 42 +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MSB 47 +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc0000000000 + + + + +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_OFFSET 0x0000000000000048 +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_LSB 48 +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MASK 0xffff000000000000 + + + + +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_OFFSET 0x0000000000000050 +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MSB 23 +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MASK 0x0000000000ffffff + + + + +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_OFFSET 0x0000000000000050 +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_LSB 24 +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MASK 0x00000000ff000000 + + + + +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000000000000050 +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff00000000 + + + + +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000000000000058 +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MASK 0x00000000ffffffff + + + + +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x0000000000000058 +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff00000000 + + + + +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MSB 11 +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MASK 0x0000000000000fff + + + + +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_LSB 12 +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MSB 27 +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MASK 0x000000000ffff000 + + + + +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MSB 28 +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MASK 0x0000000010000000 + + + + +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_LSB 29 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MASK 0x00000000e0000000 + + + + +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_MSB 47 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_MASK 0x0000ffff00000000 + + + + +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_LSB 48 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_MSB 55 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_MASK 0x00ff000000000000 + + + + +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_LSB 56 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MSB 59 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MASK 0x0f00000000000000 + + + + +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_LSB 60 +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + + + +#endif diff --git a/hw/qcn9224/reo_unblock_cache.h b/hw/qcn9224/reo_unblock_cache.h new file mode 100644 index 000000000000..7eed9fd76cab --- /dev/null +++ b/hw/qcn9224/reo_unblock_cache.h @@ -0,0 +1,184 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _REO_UNBLOCK_CACHE_H_ +#define _REO_UNBLOCK_CACHE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 10 + +#define NUM_OF_QWORDS_REO_UNBLOCK_CACHE 5 + + +struct reo_unblock_cache { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t unblock_type : 1, + cache_block_resource_index : 2, + reserved_1a : 29; + uint32_t reserved_2a : 32; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t tlv64_padding : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t reserved_1a : 29, + cache_block_resource_index : 2, + unblock_type : 1; + uint32_t reserved_2a : 32; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t tlv64_padding : 32; +#endif +}; + + + + + + + +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff + + + + +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 + + + + +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 + + + + +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_LSB 32 +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MSB 32 +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MASK 0x0000000100000000 + + + + +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 33 +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 34 +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000600000000 + + + + +#define REO_UNBLOCK_CACHE_RESERVED_1A_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_RESERVED_1A_LSB 35 +#define REO_UNBLOCK_CACHE_RESERVED_1A_MSB 63 +#define REO_UNBLOCK_CACHE_RESERVED_1A_MASK 0xfffffff800000000 + + + + +#define REO_UNBLOCK_CACHE_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_UNBLOCK_CACHE_RESERVED_2A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_2A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_2A_MASK 0x00000000ffffffff + + + + +#define REO_UNBLOCK_CACHE_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_UNBLOCK_CACHE_RESERVED_3A_LSB 32 +#define REO_UNBLOCK_CACHE_RESERVED_3A_MSB 63 +#define REO_UNBLOCK_CACHE_RESERVED_3A_MASK 0xffffffff00000000 + + + + +#define REO_UNBLOCK_CACHE_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_UNBLOCK_CACHE_RESERVED_4A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_4A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_4A_MASK 0x00000000ffffffff + + + + +#define REO_UNBLOCK_CACHE_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_UNBLOCK_CACHE_RESERVED_5A_LSB 32 +#define REO_UNBLOCK_CACHE_RESERVED_5A_MSB 63 +#define REO_UNBLOCK_CACHE_RESERVED_5A_MASK 0xffffffff00000000 + + + + +#define REO_UNBLOCK_CACHE_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_UNBLOCK_CACHE_RESERVED_6A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_6A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_6A_MASK 0x00000000ffffffff + + + + +#define REO_UNBLOCK_CACHE_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_UNBLOCK_CACHE_RESERVED_7A_LSB 32 +#define REO_UNBLOCK_CACHE_RESERVED_7A_MSB 63 +#define REO_UNBLOCK_CACHE_RESERVED_7A_MASK 0xffffffff00000000 + + + + +#define REO_UNBLOCK_CACHE_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_UNBLOCK_CACHE_RESERVED_8A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_8A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_8A_MASK 0x00000000ffffffff + + + + +#define REO_UNBLOCK_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020 +#define REO_UNBLOCK_CACHE_TLV64_PADDING_LSB 32 +#define REO_UNBLOCK_CACHE_TLV64_PADDING_MSB 63 +#define REO_UNBLOCK_CACHE_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif diff --git a/hw/qcn9224/reo_unblock_cache_status.h b/hw/qcn9224/reo_unblock_cache_status.h new file mode 100644 index 000000000000..e36bc906a061 --- /dev/null +++ b/hw/qcn9224/reo_unblock_cache_status.h @@ -0,0 +1,360 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _REO_UNBLOCK_CACHE_STATUS_H_ +#define _REO_UNBLOCK_CACHE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 26 + +#define NUM_OF_QWORDS_REO_UNBLOCK_CACHE_STATUS 13 + + +struct reo_unblock_cache_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + unblock_type : 1, + reserved_2a : 30; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 30, + unblock_type : 1, + error_detected : 1; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + + + + + + + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + + + + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + + + + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + + + + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + + + + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + + + + +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MSB 0 +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 + + + + +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_OFFSET 0x0000000000000008 +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_LSB 1 +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MSB 1 +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MASK 0x0000000000000002 + + + + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_LSB 2 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MASK 0x00000000fffffffc + + + + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 + + + + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff + + + + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 + + + + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff + + + + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 + + + + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff + + + + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 + + + + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff + + + + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 + + + + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff + + + + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 + + + + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff + + + + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 + + + + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff + + + + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 + + + + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff + + + + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 + + + + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff + + + + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 + + + + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff + + + + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 + + + + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff + + + + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MSB 59 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 + + + + +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_LSB 60 +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + + + +#endif diff --git a/hw/qcn9224/reo_update_rx_reo_queue.h b/hw/qcn9224/reo_update_rx_reo_queue.h new file mode 100644 index 000000000000..e37fa4df2c7e --- /dev/null +++ b/hw/qcn9224/reo_update_rx_reo_queue.h @@ -0,0 +1,624 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _REO_UPDATE_RX_REO_QUEUE_H_ +#define _REO_UPDATE_RX_REO_QUEUE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 10 + +#define NUM_OF_QWORDS_REO_UPDATE_RX_REO_QUEUE 5 + + +struct reo_update_rx_reo_queue { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + update_receive_queue_number : 1, + update_vld : 1, + update_associated_link_descriptor_counter : 1, + update_disable_duplicate_detection : 1, + update_soft_reorder_enable : 1, + update_ac : 1, + update_bar : 1, + update_rty : 1, + update_chk_2k_mode : 1, + update_oor_mode : 1, + update_ba_window_size : 1, + update_pn_check_needed : 1, + update_pn_shall_be_even : 1, + update_pn_shall_be_uneven : 1, + update_pn_handling_enable : 1, + update_pn_size : 1, + update_ignore_ampdu_flag : 1, + update_svld : 1, + update_ssn : 1, + update_seq_2k_error_detected_flag : 1, + update_pn_error_detected_flag : 1, + update_pn_valid : 1, + update_pn : 1, + clear_stat_counters : 1; + uint32_t receive_queue_number : 16, + vld : 1, + associated_link_descriptor_counter : 2, + disable_duplicate_detection : 1, + soft_reorder_enable : 1, + ac : 2, + bar : 1, + rty : 1, + chk_2k_mode : 1, + oor_mode : 1, + pn_check_needed : 1, + pn_shall_be_even : 1, + pn_shall_be_uneven : 1, + pn_handling_enable : 1, + ignore_ampdu_flag : 1; + uint32_t ba_window_size : 10, + pn_size : 2, + svld : 1, + ssn : 12, + seq_2k_error_detected_flag : 1, + pn_error_detected_flag : 1, + pn_valid : 1, + flush_from_cache : 1, + reserved_4a : 3; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t tlv64_padding : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t clear_stat_counters : 1, + update_pn : 1, + update_pn_valid : 1, + update_pn_error_detected_flag : 1, + update_seq_2k_error_detected_flag : 1, + update_ssn : 1, + update_svld : 1, + update_ignore_ampdu_flag : 1, + update_pn_size : 1, + update_pn_handling_enable : 1, + update_pn_shall_be_uneven : 1, + update_pn_shall_be_even : 1, + update_pn_check_needed : 1, + update_ba_window_size : 1, + update_oor_mode : 1, + update_chk_2k_mode : 1, + update_rty : 1, + update_bar : 1, + update_ac : 1, + update_soft_reorder_enable : 1, + update_disable_duplicate_detection : 1, + update_associated_link_descriptor_counter : 1, + update_vld : 1, + update_receive_queue_number : 1, + rx_reo_queue_desc_addr_39_32 : 8; + uint32_t ignore_ampdu_flag : 1, + pn_handling_enable : 1, + pn_shall_be_uneven : 1, + pn_shall_be_even : 1, + pn_check_needed : 1, + oor_mode : 1, + chk_2k_mode : 1, + rty : 1, + bar : 1, + ac : 2, + soft_reorder_enable : 1, + disable_duplicate_detection : 1, + associated_link_descriptor_counter : 2, + vld : 1, + receive_queue_number : 16; + uint32_t reserved_4a : 3, + flush_from_cache : 1, + pn_valid : 1, + pn_error_detected_flag : 1, + seq_2k_error_detected_flag : 1, + ssn : 12, + svld : 1, + pn_size : 2, + ba_window_size : 10; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t tlv64_padding : 32; +#endif +}; + + + + + + + +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff + + + + +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff + + + + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_LSB 8 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MSB 8 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MASK 0x0000000000000100 + + + + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_LSB 9 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MSB 9 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MASK 0x0000000000000200 + + + + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 10 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x0000000000000400 + + + + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MSB 11 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x0000000000000800 + + + + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_LSB 12 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MSB 12 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MASK 0x0000000000001000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_LSB 13 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MSB 13 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MASK 0x0000000000002000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_LSB 14 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MSB 14 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MASK 0x0000000000004000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_LSB 15 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MSB 15 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MASK 0x0000000000008000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MSB 16 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MASK 0x0000000000010000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MSB 17 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MASK 0x0000000000020000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_LSB 18 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MSB 18 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MASK 0x0000000000040000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_LSB 19 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MSB 19 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MASK 0x0000000000080000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_LSB 20 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MSB 20 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MASK 0x0000000000100000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_LSB 21 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MSB 21 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MASK 0x0000000000200000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_LSB 22 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MSB 22 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MASK 0x0000000000400000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_LSB 23 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MSB 23 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MASK 0x0000000000800000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_LSB 24 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MSB 24 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MASK 0x0000000001000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MSB 25 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MASK 0x0000000002000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MSB 26 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MASK 0x0000000004000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 27 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x0000000008000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MSB 28 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x0000000010000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_LSB 29 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MSB 29 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MASK 0x0000000020000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_LSB 30 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MSB 30 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MASK 0x0000000040000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_LSB 31 +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MASK 0x0000000080000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 47 +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff00000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_VLD_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_VLD_LSB 48 +#define REO_UPDATE_RX_REO_QUEUE_VLD_MSB 48 +#define REO_UPDATE_RX_REO_QUEUE_VLD_MASK 0x0001000000000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 49 +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 50 +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x0006000000000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 51 +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 51 +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x0008000000000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 52 +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 52 +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x0010000000000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_AC_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_AC_LSB 53 +#define REO_UPDATE_RX_REO_QUEUE_AC_MSB 54 +#define REO_UPDATE_RX_REO_QUEUE_AC_MASK 0x0060000000000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_BAR_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_BAR_LSB 55 +#define REO_UPDATE_RX_REO_QUEUE_BAR_MSB 55 +#define REO_UPDATE_RX_REO_QUEUE_BAR_MASK 0x0080000000000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_RTY_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_RTY_LSB 56 +#define REO_UPDATE_RX_REO_QUEUE_RTY_MSB 56 +#define REO_UPDATE_RX_REO_QUEUE_RTY_MASK 0x0100000000000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_LSB 57 +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MSB 57 +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MASK 0x0200000000000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_LSB 58 +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MSB 58 +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MASK 0x0400000000000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 59 +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 59 +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x0800000000000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 60 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 60 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x1000000000000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 61 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 61 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x2000000000000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 62 +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 62 +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x4000000000000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 63 +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x8000000000000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 9 +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x00000000000003ff + + + + +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_LSB 10 +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MSB 11 +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MASK 0x0000000000000c00 + + + + +#define REO_UPDATE_RX_REO_QUEUE_SVLD_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_SVLD_LSB 12 +#define REO_UPDATE_RX_REO_QUEUE_SVLD_MSB 12 +#define REO_UPDATE_RX_REO_QUEUE_SVLD_MASK 0x0000000000001000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_SSN_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_SSN_LSB 13 +#define REO_UPDATE_RX_REO_QUEUE_SSN_MSB 24 +#define REO_UPDATE_RX_REO_QUEUE_SSN_MASK 0x0000000001ffe000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 25 +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x0000000002000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 26 +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x0000000004000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MSB 27 +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MASK 0x0000000008000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MSB 28 +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MASK 0x0000000010000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_LSB 29 +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MASK 0x00000000e0000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MASK 0xffffffff00000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_OFFSET 0x0000000000000018 +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MASK 0x00000000ffffffff + + + + +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_OFFSET 0x0000000000000018 +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MASK 0xffffffff00000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_OFFSET 0x0000000000000020 +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MASK 0x00000000ffffffff + + + + +#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020 +#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif diff --git a/hw/qcn9224/reo_update_rx_reo_queue_status.h b/hw/qcn9224/reo_update_rx_reo_queue_status.h new file mode 100644 index 000000000000..b8e88e8b946c --- /dev/null +++ b/hw/qcn9224/reo_update_rx_reo_queue_status.h @@ -0,0 +1,340 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ +#define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 26 + +#define NUM_OF_QWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 13 + + +struct reo_update_rx_reo_queue_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 32; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 32; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + + + + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MASK 0x00000000ffffffff + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MSB 59 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 + + + + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_LSB 60 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + + + +#endif diff --git a/hw/qcn9224/rx_attention.h b/hw/qcn9224/rx_attention.h new file mode 100644 index 000000000000..e4d358287bc5 --- /dev/null +++ b/hw/qcn9224/rx_attention.h @@ -0,0 +1,554 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RX_ATTENTION_H_ +#define _RX_ATTENTION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_ATTENTION 4 + +#define NUM_OF_QWORDS_RX_ATTENTION 2 + + +struct rx_attention { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t first_mpdu : 1, + reserved_1a : 1, + mcast_bcast : 1, + ast_index_not_found : 1, + ast_index_timeout : 1, + power_mgmt : 1, + non_qos : 1, + null_data : 1, + mgmt_type : 1, + ctrl_type : 1, + more_data : 1, + eosp : 1, + a_msdu_error : 1, + fragment_flag : 1, + order : 1, + cce_match : 1, + overflow_err : 1, + msdu_length_err : 1, + tcp_udp_chksum_fail : 1, + ip_chksum_fail : 1, + sa_idx_invalid : 1, + da_idx_invalid : 1, + reserved_1b : 1, + rx_in_tx_decrypt_byp : 1, + encrypt_required : 1, + directed : 1, + buffer_fragment : 1, + mpdu_length_err : 1, + tkip_mic_err : 1, + decrypt_err : 1, + unencrypted_frame_err : 1, + fcs_err : 1; + uint32_t flow_idx_timeout : 1, + flow_idx_invalid : 1, + wifi_parser_error : 1, + amsdu_parser_error : 1, + sa_idx_timeout : 1, + da_idx_timeout : 1, + msdu_limit_error : 1, + da_is_valid : 1, + da_is_mcbc : 1, + sa_is_valid : 1, + decrypt_status_code : 3, + rx_bitmap_not_updated : 1, + reserved_2 : 17, + msdu_done : 1; + uint32_t tlv64_padding : 32; +#else + uint32_t phy_ppdu_id : 16, + reserved_0 : 7, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t fcs_err : 1, + unencrypted_frame_err : 1, + decrypt_err : 1, + tkip_mic_err : 1, + mpdu_length_err : 1, + buffer_fragment : 1, + directed : 1, + encrypt_required : 1, + rx_in_tx_decrypt_byp : 1, + reserved_1b : 1, + da_idx_invalid : 1, + sa_idx_invalid : 1, + ip_chksum_fail : 1, + tcp_udp_chksum_fail : 1, + msdu_length_err : 1, + overflow_err : 1, + cce_match : 1, + order : 1, + fragment_flag : 1, + a_msdu_error : 1, + eosp : 1, + more_data : 1, + ctrl_type : 1, + mgmt_type : 1, + null_data : 1, + non_qos : 1, + power_mgmt : 1, + ast_index_timeout : 1, + ast_index_not_found : 1, + mcast_bcast : 1, + reserved_1a : 1, + first_mpdu : 1; + uint32_t msdu_done : 1, + reserved_2 : 17, + rx_bitmap_not_updated : 1, + decrypt_status_code : 3, + sa_is_valid : 1, + da_is_mcbc : 1, + da_is_valid : 1, + msdu_limit_error : 1, + da_idx_timeout : 1, + sa_idx_timeout : 1, + amsdu_parser_error : 1, + wifi_parser_error : 1, + flow_idx_invalid : 1, + flow_idx_timeout : 1; + uint32_t tlv64_padding : 32; +#endif +}; + + + + +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 + + + + +#define RX_ATTENTION_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 +#define RX_ATTENTION_SW_FRAME_GROUP_ID_LSB 2 +#define RX_ATTENTION_SW_FRAME_GROUP_ID_MSB 8 +#define RX_ATTENTION_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc + + + + +#define RX_ATTENTION_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_ATTENTION_RESERVED_0_LSB 9 +#define RX_ATTENTION_RESERVED_0_MSB 15 +#define RX_ATTENTION_RESERVED_0_MASK 0x000000000000fe00 + + + + +#define RX_ATTENTION_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_ATTENTION_PHY_PPDU_ID_LSB 16 +#define RX_ATTENTION_PHY_PPDU_ID_MSB 31 +#define RX_ATTENTION_PHY_PPDU_ID_MASK 0x00000000ffff0000 + + + + +#define RX_ATTENTION_FIRST_MPDU_OFFSET 0x0000000000000000 +#define RX_ATTENTION_FIRST_MPDU_LSB 32 +#define RX_ATTENTION_FIRST_MPDU_MSB 32 +#define RX_ATTENTION_FIRST_MPDU_MASK 0x0000000100000000 + + + + +#define RX_ATTENTION_RESERVED_1A_OFFSET 0x0000000000000000 +#define RX_ATTENTION_RESERVED_1A_LSB 33 +#define RX_ATTENTION_RESERVED_1A_MSB 33 +#define RX_ATTENTION_RESERVED_1A_MASK 0x0000000200000000 + + + + +#define RX_ATTENTION_MCAST_BCAST_OFFSET 0x0000000000000000 +#define RX_ATTENTION_MCAST_BCAST_LSB 34 +#define RX_ATTENTION_MCAST_BCAST_MSB 34 +#define RX_ATTENTION_MCAST_BCAST_MASK 0x0000000400000000 + + + + +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000000 +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_LSB 35 +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MSB 35 +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MASK 0x0000000800000000 + + + + +#define RX_ATTENTION_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000000 +#define RX_ATTENTION_AST_INDEX_TIMEOUT_LSB 36 +#define RX_ATTENTION_AST_INDEX_TIMEOUT_MSB 36 +#define RX_ATTENTION_AST_INDEX_TIMEOUT_MASK 0x0000001000000000 + + + + +#define RX_ATTENTION_POWER_MGMT_OFFSET 0x0000000000000000 +#define RX_ATTENTION_POWER_MGMT_LSB 37 +#define RX_ATTENTION_POWER_MGMT_MSB 37 +#define RX_ATTENTION_POWER_MGMT_MASK 0x0000002000000000 + + + + +#define RX_ATTENTION_NON_QOS_OFFSET 0x0000000000000000 +#define RX_ATTENTION_NON_QOS_LSB 38 +#define RX_ATTENTION_NON_QOS_MSB 38 +#define RX_ATTENTION_NON_QOS_MASK 0x0000004000000000 + + + + +#define RX_ATTENTION_NULL_DATA_OFFSET 0x0000000000000000 +#define RX_ATTENTION_NULL_DATA_LSB 39 +#define RX_ATTENTION_NULL_DATA_MSB 39 +#define RX_ATTENTION_NULL_DATA_MASK 0x0000008000000000 + + + + +#define RX_ATTENTION_MGMT_TYPE_OFFSET 0x0000000000000000 +#define RX_ATTENTION_MGMT_TYPE_LSB 40 +#define RX_ATTENTION_MGMT_TYPE_MSB 40 +#define RX_ATTENTION_MGMT_TYPE_MASK 0x0000010000000000 + + + + +#define RX_ATTENTION_CTRL_TYPE_OFFSET 0x0000000000000000 +#define RX_ATTENTION_CTRL_TYPE_LSB 41 +#define RX_ATTENTION_CTRL_TYPE_MSB 41 +#define RX_ATTENTION_CTRL_TYPE_MASK 0x0000020000000000 + + + + +#define RX_ATTENTION_MORE_DATA_OFFSET 0x0000000000000000 +#define RX_ATTENTION_MORE_DATA_LSB 42 +#define RX_ATTENTION_MORE_DATA_MSB 42 +#define RX_ATTENTION_MORE_DATA_MASK 0x0000040000000000 + + + + +#define RX_ATTENTION_EOSP_OFFSET 0x0000000000000000 +#define RX_ATTENTION_EOSP_LSB 43 +#define RX_ATTENTION_EOSP_MSB 43 +#define RX_ATTENTION_EOSP_MASK 0x0000080000000000 + + + + +#define RX_ATTENTION_A_MSDU_ERROR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_A_MSDU_ERROR_LSB 44 +#define RX_ATTENTION_A_MSDU_ERROR_MSB 44 +#define RX_ATTENTION_A_MSDU_ERROR_MASK 0x0000100000000000 + + + + +#define RX_ATTENTION_FRAGMENT_FLAG_OFFSET 0x0000000000000000 +#define RX_ATTENTION_FRAGMENT_FLAG_LSB 45 +#define RX_ATTENTION_FRAGMENT_FLAG_MSB 45 +#define RX_ATTENTION_FRAGMENT_FLAG_MASK 0x0000200000000000 + + + + +#define RX_ATTENTION_ORDER_OFFSET 0x0000000000000000 +#define RX_ATTENTION_ORDER_LSB 46 +#define RX_ATTENTION_ORDER_MSB 46 +#define RX_ATTENTION_ORDER_MASK 0x0000400000000000 + + + + +#define RX_ATTENTION_CCE_MATCH_OFFSET 0x0000000000000000 +#define RX_ATTENTION_CCE_MATCH_LSB 47 +#define RX_ATTENTION_CCE_MATCH_MSB 47 +#define RX_ATTENTION_CCE_MATCH_MASK 0x0000800000000000 + + + + +#define RX_ATTENTION_OVERFLOW_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_OVERFLOW_ERR_LSB 48 +#define RX_ATTENTION_OVERFLOW_ERR_MSB 48 +#define RX_ATTENTION_OVERFLOW_ERR_MASK 0x0001000000000000 + + + + +#define RX_ATTENTION_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_MSDU_LENGTH_ERR_LSB 49 +#define RX_ATTENTION_MSDU_LENGTH_ERR_MSB 49 +#define RX_ATTENTION_MSDU_LENGTH_ERR_MASK 0x0002000000000000 + + + + +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000000 +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_LSB 50 +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MSB 50 +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MASK 0x0004000000000000 + + + + +#define RX_ATTENTION_IP_CHKSUM_FAIL_OFFSET 0x0000000000000000 +#define RX_ATTENTION_IP_CHKSUM_FAIL_LSB 51 +#define RX_ATTENTION_IP_CHKSUM_FAIL_MSB 51 +#define RX_ATTENTION_IP_CHKSUM_FAIL_MASK 0x0008000000000000 + + + + +#define RX_ATTENTION_SA_IDX_INVALID_OFFSET 0x0000000000000000 +#define RX_ATTENTION_SA_IDX_INVALID_LSB 52 +#define RX_ATTENTION_SA_IDX_INVALID_MSB 52 +#define RX_ATTENTION_SA_IDX_INVALID_MASK 0x0010000000000000 + + + + +#define RX_ATTENTION_DA_IDX_INVALID_OFFSET 0x0000000000000000 +#define RX_ATTENTION_DA_IDX_INVALID_LSB 53 +#define RX_ATTENTION_DA_IDX_INVALID_MSB 53 +#define RX_ATTENTION_DA_IDX_INVALID_MASK 0x0020000000000000 + + + + +#define RX_ATTENTION_RESERVED_1B_OFFSET 0x0000000000000000 +#define RX_ATTENTION_RESERVED_1B_LSB 54 +#define RX_ATTENTION_RESERVED_1B_MSB 54 +#define RX_ATTENTION_RESERVED_1B_MASK 0x0040000000000000 + + + + +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_LSB 55 +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MSB 55 +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MASK 0x0080000000000000 + + + + +#define RX_ATTENTION_ENCRYPT_REQUIRED_OFFSET 0x0000000000000000 +#define RX_ATTENTION_ENCRYPT_REQUIRED_LSB 56 +#define RX_ATTENTION_ENCRYPT_REQUIRED_MSB 56 +#define RX_ATTENTION_ENCRYPT_REQUIRED_MASK 0x0100000000000000 + + + + +#define RX_ATTENTION_DIRECTED_OFFSET 0x0000000000000000 +#define RX_ATTENTION_DIRECTED_LSB 57 +#define RX_ATTENTION_DIRECTED_MSB 57 +#define RX_ATTENTION_DIRECTED_MASK 0x0200000000000000 + + + + +#define RX_ATTENTION_BUFFER_FRAGMENT_OFFSET 0x0000000000000000 +#define RX_ATTENTION_BUFFER_FRAGMENT_LSB 58 +#define RX_ATTENTION_BUFFER_FRAGMENT_MSB 58 +#define RX_ATTENTION_BUFFER_FRAGMENT_MASK 0x0400000000000000 + + + + +#define RX_ATTENTION_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_MPDU_LENGTH_ERR_LSB 59 +#define RX_ATTENTION_MPDU_LENGTH_ERR_MSB 59 +#define RX_ATTENTION_MPDU_LENGTH_ERR_MASK 0x0800000000000000 + + + + +#define RX_ATTENTION_TKIP_MIC_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_TKIP_MIC_ERR_LSB 60 +#define RX_ATTENTION_TKIP_MIC_ERR_MSB 60 +#define RX_ATTENTION_TKIP_MIC_ERR_MASK 0x1000000000000000 + + + + +#define RX_ATTENTION_DECRYPT_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_DECRYPT_ERR_LSB 61 +#define RX_ATTENTION_DECRYPT_ERR_MSB 61 +#define RX_ATTENTION_DECRYPT_ERR_MASK 0x2000000000000000 + + + + +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_LSB 62 +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MSB 62 +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MASK 0x4000000000000000 + + + + +#define RX_ATTENTION_FCS_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_FCS_ERR_LSB 63 +#define RX_ATTENTION_FCS_ERR_MSB 63 +#define RX_ATTENTION_FCS_ERR_MASK 0x8000000000000000 + + + + +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000008 +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_LSB 0 +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MSB 0 +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MASK 0x0000000000000001 + + + + +#define RX_ATTENTION_FLOW_IDX_INVALID_OFFSET 0x0000000000000008 +#define RX_ATTENTION_FLOW_IDX_INVALID_LSB 1 +#define RX_ATTENTION_FLOW_IDX_INVALID_MSB 1 +#define RX_ATTENTION_FLOW_IDX_INVALID_MASK 0x0000000000000002 + + + + +#define RX_ATTENTION_WIFI_PARSER_ERROR_OFFSET 0x0000000000000008 +#define RX_ATTENTION_WIFI_PARSER_ERROR_LSB 2 +#define RX_ATTENTION_WIFI_PARSER_ERROR_MSB 2 +#define RX_ATTENTION_WIFI_PARSER_ERROR_MASK 0x0000000000000004 + + + + +#define RX_ATTENTION_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000008 +#define RX_ATTENTION_AMSDU_PARSER_ERROR_LSB 3 +#define RX_ATTENTION_AMSDU_PARSER_ERROR_MSB 3 +#define RX_ATTENTION_AMSDU_PARSER_ERROR_MASK 0x0000000000000008 + + + + +#define RX_ATTENTION_SA_IDX_TIMEOUT_OFFSET 0x0000000000000008 +#define RX_ATTENTION_SA_IDX_TIMEOUT_LSB 4 +#define RX_ATTENTION_SA_IDX_TIMEOUT_MSB 4 +#define RX_ATTENTION_SA_IDX_TIMEOUT_MASK 0x0000000000000010 + + + + +#define RX_ATTENTION_DA_IDX_TIMEOUT_OFFSET 0x0000000000000008 +#define RX_ATTENTION_DA_IDX_TIMEOUT_LSB 5 +#define RX_ATTENTION_DA_IDX_TIMEOUT_MSB 5 +#define RX_ATTENTION_DA_IDX_TIMEOUT_MASK 0x0000000000000020 + + + + +#define RX_ATTENTION_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000008 +#define RX_ATTENTION_MSDU_LIMIT_ERROR_LSB 6 +#define RX_ATTENTION_MSDU_LIMIT_ERROR_MSB 6 +#define RX_ATTENTION_MSDU_LIMIT_ERROR_MASK 0x0000000000000040 + + + + +#define RX_ATTENTION_DA_IS_VALID_OFFSET 0x0000000000000008 +#define RX_ATTENTION_DA_IS_VALID_LSB 7 +#define RX_ATTENTION_DA_IS_VALID_MSB 7 +#define RX_ATTENTION_DA_IS_VALID_MASK 0x0000000000000080 + + + + +#define RX_ATTENTION_DA_IS_MCBC_OFFSET 0x0000000000000008 +#define RX_ATTENTION_DA_IS_MCBC_LSB 8 +#define RX_ATTENTION_DA_IS_MCBC_MSB 8 +#define RX_ATTENTION_DA_IS_MCBC_MASK 0x0000000000000100 + + + + +#define RX_ATTENTION_SA_IS_VALID_OFFSET 0x0000000000000008 +#define RX_ATTENTION_SA_IS_VALID_LSB 9 +#define RX_ATTENTION_SA_IS_VALID_MSB 9 +#define RX_ATTENTION_SA_IS_VALID_MASK 0x0000000000000200 + + + + +#define RX_ATTENTION_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000008 +#define RX_ATTENTION_DECRYPT_STATUS_CODE_LSB 10 +#define RX_ATTENTION_DECRYPT_STATUS_CODE_MSB 12 +#define RX_ATTENTION_DECRYPT_STATUS_CODE_MASK 0x0000000000001c00 + + + + +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000008 +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_LSB 13 +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MSB 13 +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MASK 0x0000000000002000 + + + + +#define RX_ATTENTION_RESERVED_2_OFFSET 0x0000000000000008 +#define RX_ATTENTION_RESERVED_2_LSB 14 +#define RX_ATTENTION_RESERVED_2_MSB 30 +#define RX_ATTENTION_RESERVED_2_MASK 0x000000007fffc000 + + + + +#define RX_ATTENTION_MSDU_DONE_OFFSET 0x0000000000000008 +#define RX_ATTENTION_MSDU_DONE_LSB 31 +#define RX_ATTENTION_MSDU_DONE_MSB 31 +#define RX_ATTENTION_MSDU_DONE_MASK 0x0000000080000000 + + + + +#define RX_ATTENTION_TLV64_PADDING_OFFSET 0x0000000000000008 +#define RX_ATTENTION_TLV64_PADDING_LSB 32 +#define RX_ATTENTION_TLV64_PADDING_MSB 63 +#define RX_ATTENTION_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif diff --git a/hw/qcn9224/rx_flow_search_entry.h b/hw/qcn9224/rx_flow_search_entry.h new file mode 100644 index 000000000000..8b90fe033aba --- /dev/null +++ b/hw/qcn9224/rx_flow_search_entry.h @@ -0,0 +1,322 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RX_FLOW_SEARCH_ENTRY_H_ +#define _RX_FLOW_SEARCH_ENTRY_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16 + + +struct rx_flow_search_entry { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t src_ip_127_96 : 32; + uint32_t src_ip_95_64 : 32; + uint32_t src_ip_63_32 : 32; + uint32_t src_ip_31_0 : 32; + uint32_t dest_ip_127_96 : 32; + uint32_t dest_ip_95_64 : 32; + uint32_t dest_ip_63_32 : 32; + uint32_t dest_ip_31_0 : 32; + uint32_t src_port : 16, + dest_port : 16; + uint32_t l4_protocol : 8, + valid : 1, + reserved_9 : 4, + service_code : 9, + priority_valid : 1, + use_ppe : 1, + reo_destination_indication : 5, + msdu_drop : 1, + reo_destination_handler : 2; + uint32_t metadata : 32; + uint32_t aggregation_count : 7, + lro_eligible : 1, + msdu_count : 24; + uint32_t msdu_byte_count : 32; + uint32_t timestamp : 32; + uint32_t cumulative_ip_length_pmac1 : 16, + cumulative_ip_length : 16; + uint32_t tcp_sequence_number : 32; +#else + uint32_t src_ip_127_96 : 32; + uint32_t src_ip_95_64 : 32; + uint32_t src_ip_63_32 : 32; + uint32_t src_ip_31_0 : 32; + uint32_t dest_ip_127_96 : 32; + uint32_t dest_ip_95_64 : 32; + uint32_t dest_ip_63_32 : 32; + uint32_t dest_ip_31_0 : 32; + uint32_t dest_port : 16, + src_port : 16; + uint32_t reo_destination_handler : 2, + msdu_drop : 1, + reo_destination_indication : 5, + use_ppe : 1, + priority_valid : 1, + service_code : 9, + reserved_9 : 4, + valid : 1, + l4_protocol : 8; + uint32_t metadata : 32; + uint32_t msdu_count : 24, + lro_eligible : 1, + aggregation_count : 7; + uint32_t msdu_byte_count : 32; + uint32_t timestamp : 32; + uint32_t cumulative_ip_length : 16, + cumulative_ip_length_pmac1 : 16; + uint32_t tcp_sequence_number : 32; +#endif +}; + + + + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_OFFSET 0x00000000 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MASK 0xffffffff + + + + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_OFFSET 0x00000004 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MASK 0xffffffff + + + + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_OFFSET 0x00000008 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MASK 0xffffffff + + + + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_OFFSET 0x0000000c +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MASK 0xffffffff + + + + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_OFFSET 0x00000010 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MASK 0xffffffff + + + + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_OFFSET 0x00000014 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MASK 0xffffffff + + + + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_OFFSET 0x00000018 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MASK 0xffffffff + + + + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_OFFSET 0x0000001c +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MASK 0xffffffff + + + + +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_OFFSET 0x00000020 +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MSB 15 +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MASK 0x0000ffff + + + + +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_OFFSET 0x00000020 +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_LSB 16 +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MASK 0xffff0000 + + + + +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MSB 7 +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MASK 0x000000ff + + + + +#define RX_FLOW_SEARCH_ENTRY_VALID_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_VALID_LSB 8 +#define RX_FLOW_SEARCH_ENTRY_VALID_MSB 8 +#define RX_FLOW_SEARCH_ENTRY_VALID_MASK 0x00000100 + + + + +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_LSB 9 +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MSB 12 +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MASK 0x00001e00 + + + + +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_LSB 13 +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MSB 21 +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MASK 0x003fe000 + + + + +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_LSB 22 +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MSB 22 +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MASK 0x00400000 + + + + +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_LSB 23 +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MSB 23 +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MASK 0x00800000 + + + + +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_LSB 24 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MSB 28 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MASK 0x1f000000 + + + + +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_LSB 29 +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MSB 29 +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MASK 0x20000000 + + + + +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_LSB 30 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MASK 0xc0000000 + + + + +#define RX_FLOW_SEARCH_ENTRY_METADATA_OFFSET 0x00000028 +#define RX_FLOW_SEARCH_ENTRY_METADATA_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_METADATA_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_METADATA_MASK 0xffffffff + + + + +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MSB 6 +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MASK 0x0000007f + + + + +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_LSB 7 +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MSB 7 +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MASK 0x00000080 + + + + +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_LSB 8 +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MASK 0xffffff00 + + + + +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_OFFSET 0x00000030 +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MASK 0xffffffff + + + + +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_OFFSET 0x00000034 +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MASK 0xffffffff + + + + +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_OFFSET 0x00000038 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MSB 15 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MASK 0x0000ffff + + + + +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_LSB 16 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 + + + + +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MASK 0xffffffff + + + +#endif diff --git a/hw/qcn9224/rx_location_info.h b/hw/qcn9224/rx_location_info.h new file mode 100644 index 000000000000..5415c4cd0717 --- /dev/null +++ b/hw/qcn9224/rx_location_info.h @@ -0,0 +1,672 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RX_LOCATION_INFO_H_ +#define _RX_LOCATION_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_LOCATION_INFO 28 + + +struct rx_location_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rx_location_info_valid : 1, + rtt_hw_ifft_mode : 1, + rtt_11az_mode : 2, + reserved_0 : 4, + rtt_num_fac : 8, + rtt_rx_chain_mask : 8, + rtt_num_streams : 8; + uint32_t rtt_first_selected_chain : 8, + rtt_second_selected_chain : 8, + rtt_cfr_status : 8, + rtt_cir_status : 8; + uint32_t rtt_che_buffer_pointer_low32 : 32; + uint32_t rtt_che_buffer_pointer_high8 : 8, + reserved_3 : 8, + rtt_pkt_bw_vht : 4, + rtt_pkt_bw_leg : 4, + rtt_mcs_rate : 8; + uint32_t rtt_cfo_measurement : 16, + rtt_preamble_type : 8, + rtt_gi_type : 8; + uint32_t rx_start_ts : 32; + uint32_t rx_start_ts_upper : 32; + uint32_t rx_end_ts : 32; + uint32_t gain_chain0 : 16, + gain_chain1 : 16; + uint32_t gain_chain2 : 16, + gain_chain3 : 16; + uint32_t gain_report_status : 8, + rtt_timing_backoff_sel : 8, + rtt_fac_combined : 16; + uint32_t rtt_fac_0 : 16, + rtt_fac_1 : 16; + uint32_t rtt_fac_2 : 16, + rtt_fac_3 : 16; + uint32_t rtt_fac_4 : 16, + rtt_fac_5 : 16; + uint32_t rtt_fac_6 : 16, + rtt_fac_7 : 16; + uint32_t rtt_fac_8 : 16, + rtt_fac_9 : 16; + uint32_t rtt_fac_10 : 16, + rtt_fac_11 : 16; + uint32_t rtt_fac_12 : 16, + rtt_fac_13 : 16; + uint32_t rtt_fac_14 : 16, + rtt_fac_15 : 16; + uint32_t rtt_fac_16 : 16, + rtt_fac_17 : 16; + uint32_t rtt_fac_18 : 16, + rtt_fac_19 : 16; + uint32_t rtt_fac_20 : 16, + rtt_fac_21 : 16; + uint32_t rtt_fac_22 : 16, + rtt_fac_23 : 16; + uint32_t rtt_fac_24 : 16, + rtt_fac_25 : 16; + uint32_t rtt_fac_26 : 16, + rtt_fac_27 : 16; + uint32_t rtt_fac_28 : 16, + rtt_fac_29 : 16; + uint32_t rtt_fac_30 : 16, + rtt_fac_31 : 16; + uint32_t reserved_27a : 32; +#else + uint32_t rtt_num_streams : 8, + rtt_rx_chain_mask : 8, + rtt_num_fac : 8, + reserved_0 : 4, + rtt_11az_mode : 2, + rtt_hw_ifft_mode : 1, + rx_location_info_valid : 1; + uint32_t rtt_cir_status : 8, + rtt_cfr_status : 8, + rtt_second_selected_chain : 8, + rtt_first_selected_chain : 8; + uint32_t rtt_che_buffer_pointer_low32 : 32; + uint32_t rtt_mcs_rate : 8, + rtt_pkt_bw_leg : 4, + rtt_pkt_bw_vht : 4, + reserved_3 : 8, + rtt_che_buffer_pointer_high8 : 8; + uint32_t rtt_gi_type : 8, + rtt_preamble_type : 8, + rtt_cfo_measurement : 16; + uint32_t rx_start_ts : 32; + uint32_t rx_start_ts_upper : 32; + uint32_t rx_end_ts : 32; + uint32_t gain_chain1 : 16, + gain_chain0 : 16; + uint32_t gain_chain3 : 16, + gain_chain2 : 16; + uint32_t rtt_fac_combined : 16, + rtt_timing_backoff_sel : 8, + gain_report_status : 8; + uint32_t rtt_fac_1 : 16, + rtt_fac_0 : 16; + uint32_t rtt_fac_3 : 16, + rtt_fac_2 : 16; + uint32_t rtt_fac_5 : 16, + rtt_fac_4 : 16; + uint32_t rtt_fac_7 : 16, + rtt_fac_6 : 16; + uint32_t rtt_fac_9 : 16, + rtt_fac_8 : 16; + uint32_t rtt_fac_11 : 16, + rtt_fac_10 : 16; + uint32_t rtt_fac_13 : 16, + rtt_fac_12 : 16; + uint32_t rtt_fac_15 : 16, + rtt_fac_14 : 16; + uint32_t rtt_fac_17 : 16, + rtt_fac_16 : 16; + uint32_t rtt_fac_19 : 16, + rtt_fac_18 : 16; + uint32_t rtt_fac_21 : 16, + rtt_fac_20 : 16; + uint32_t rtt_fac_23 : 16, + rtt_fac_22 : 16; + uint32_t rtt_fac_25 : 16, + rtt_fac_24 : 16; + uint32_t rtt_fac_27 : 16, + rtt_fac_26 : 16; + uint32_t rtt_fac_29 : 16, + rtt_fac_28 : 16; + uint32_t rtt_fac_31 : 16, + rtt_fac_30 : 16; + uint32_t reserved_27a : 32; +#endif +}; + + + + +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_LSB 0 +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MSB 0 +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MASK 0x00000001 + + + + +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_LSB 1 +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MSB 1 +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MASK 0x00000002 + + + + +#define RX_LOCATION_INFO_RTT_11AZ_MODE_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_11AZ_MODE_LSB 2 +#define RX_LOCATION_INFO_RTT_11AZ_MODE_MSB 3 +#define RX_LOCATION_INFO_RTT_11AZ_MODE_MASK 0x0000000c + + + + +#define RX_LOCATION_INFO_RESERVED_0_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RESERVED_0_LSB 4 +#define RX_LOCATION_INFO_RESERVED_0_MSB 7 +#define RX_LOCATION_INFO_RESERVED_0_MASK 0x000000f0 + + + + +#define RX_LOCATION_INFO_RTT_NUM_FAC_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_NUM_FAC_LSB 8 +#define RX_LOCATION_INFO_RTT_NUM_FAC_MSB 15 +#define RX_LOCATION_INFO_RTT_NUM_FAC_MASK 0x0000ff00 + + + + +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_LSB 16 +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MSB 23 +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MASK 0x00ff0000 + + + + +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_LSB 24 +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MSB 31 +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MASK 0xff000000 + + + + +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_LSB 0 +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MSB 7 +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff + + + + +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_LSB 8 +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MSB 15 +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff00 + + + + +#define RX_LOCATION_INFO_RTT_CFR_STATUS_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_CFR_STATUS_LSB 16 +#define RX_LOCATION_INFO_RTT_CFR_STATUS_MSB 23 +#define RX_LOCATION_INFO_RTT_CFR_STATUS_MASK 0x00ff0000 + + + + +#define RX_LOCATION_INFO_RTT_CIR_STATUS_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_CIR_STATUS_LSB 24 +#define RX_LOCATION_INFO_RTT_CIR_STATUS_MSB 31 +#define RX_LOCATION_INFO_RTT_CIR_STATUS_MASK 0xff000000 + + + + +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000008 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff + + + + +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 0 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 7 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff + + + + +#define RX_LOCATION_INFO_RESERVED_3_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RESERVED_3_LSB 8 +#define RX_LOCATION_INFO_RESERVED_3_MSB 15 +#define RX_LOCATION_INFO_RESERVED_3_MASK 0x0000ff00 + + + + +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_LSB 16 +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MSB 19 +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MASK 0x000f0000 + + + + +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_LSB 20 +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MSB 23 +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MASK 0x00f00000 + + + + +#define RX_LOCATION_INFO_RTT_MCS_RATE_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_MCS_RATE_LSB 24 +#define RX_LOCATION_INFO_RTT_MCS_RATE_MSB 31 +#define RX_LOCATION_INFO_RTT_MCS_RATE_MASK 0xff000000 + + + + +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_OFFSET 0x00000010 +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_LSB 0 +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MSB 15 +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MASK 0x0000ffff + + + + +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_OFFSET 0x00000010 +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_LSB 16 +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MSB 23 +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MASK 0x00ff0000 + + + + +#define RX_LOCATION_INFO_RTT_GI_TYPE_OFFSET 0x00000010 +#define RX_LOCATION_INFO_RTT_GI_TYPE_LSB 24 +#define RX_LOCATION_INFO_RTT_GI_TYPE_MSB 31 +#define RX_LOCATION_INFO_RTT_GI_TYPE_MASK 0xff000000 + + + + +#define RX_LOCATION_INFO_RX_START_TS_OFFSET 0x00000014 +#define RX_LOCATION_INFO_RX_START_TS_LSB 0 +#define RX_LOCATION_INFO_RX_START_TS_MSB 31 +#define RX_LOCATION_INFO_RX_START_TS_MASK 0xffffffff + + + + +#define RX_LOCATION_INFO_RX_START_TS_UPPER_OFFSET 0x00000018 +#define RX_LOCATION_INFO_RX_START_TS_UPPER_LSB 0 +#define RX_LOCATION_INFO_RX_START_TS_UPPER_MSB 31 +#define RX_LOCATION_INFO_RX_START_TS_UPPER_MASK 0xffffffff + + + + +#define RX_LOCATION_INFO_RX_END_TS_OFFSET 0x0000001c +#define RX_LOCATION_INFO_RX_END_TS_LSB 0 +#define RX_LOCATION_INFO_RX_END_TS_MSB 31 +#define RX_LOCATION_INFO_RX_END_TS_MASK 0xffffffff + + + + +#define RX_LOCATION_INFO_GAIN_CHAIN0_OFFSET 0x00000020 +#define RX_LOCATION_INFO_GAIN_CHAIN0_LSB 0 +#define RX_LOCATION_INFO_GAIN_CHAIN0_MSB 15 +#define RX_LOCATION_INFO_GAIN_CHAIN0_MASK 0x0000ffff + + + + +#define RX_LOCATION_INFO_GAIN_CHAIN1_OFFSET 0x00000020 +#define RX_LOCATION_INFO_GAIN_CHAIN1_LSB 16 +#define RX_LOCATION_INFO_GAIN_CHAIN1_MSB 31 +#define RX_LOCATION_INFO_GAIN_CHAIN1_MASK 0xffff0000 + + + + +#define RX_LOCATION_INFO_GAIN_CHAIN2_OFFSET 0x00000024 +#define RX_LOCATION_INFO_GAIN_CHAIN2_LSB 0 +#define RX_LOCATION_INFO_GAIN_CHAIN2_MSB 15 +#define RX_LOCATION_INFO_GAIN_CHAIN2_MASK 0x0000ffff + + + + +#define RX_LOCATION_INFO_GAIN_CHAIN3_OFFSET 0x00000024 +#define RX_LOCATION_INFO_GAIN_CHAIN3_LSB 16 +#define RX_LOCATION_INFO_GAIN_CHAIN3_MSB 31 +#define RX_LOCATION_INFO_GAIN_CHAIN3_MASK 0xffff0000 + + + + +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_OFFSET 0x00000028 +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_LSB 0 +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MSB 7 +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MASK 0x000000ff + + + + +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000028 +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_LSB 8 +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MSB 15 +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MASK 0x0000ff00 + + + + +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_OFFSET 0x00000028 +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MASK 0xffff0000 + + + + +#define RX_LOCATION_INFO_RTT_FAC_0_OFFSET 0x0000002c +#define RX_LOCATION_INFO_RTT_FAC_0_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_0_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_0_MASK 0x0000ffff + + + + +#define RX_LOCATION_INFO_RTT_FAC_1_OFFSET 0x0000002c +#define RX_LOCATION_INFO_RTT_FAC_1_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_1_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_1_MASK 0xffff0000 + + + + +#define RX_LOCATION_INFO_RTT_FAC_2_OFFSET 0x00000030 +#define RX_LOCATION_INFO_RTT_FAC_2_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_2_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_2_MASK 0x0000ffff + + + + +#define RX_LOCATION_INFO_RTT_FAC_3_OFFSET 0x00000030 +#define RX_LOCATION_INFO_RTT_FAC_3_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_3_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_3_MASK 0xffff0000 + + + + +#define RX_LOCATION_INFO_RTT_FAC_4_OFFSET 0x00000034 +#define RX_LOCATION_INFO_RTT_FAC_4_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_4_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_4_MASK 0x0000ffff + + + + +#define RX_LOCATION_INFO_RTT_FAC_5_OFFSET 0x00000034 +#define RX_LOCATION_INFO_RTT_FAC_5_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_5_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_5_MASK 0xffff0000 + + + + +#define RX_LOCATION_INFO_RTT_FAC_6_OFFSET 0x00000038 +#define RX_LOCATION_INFO_RTT_FAC_6_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_6_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_6_MASK 0x0000ffff + + + + +#define RX_LOCATION_INFO_RTT_FAC_7_OFFSET 0x00000038 +#define RX_LOCATION_INFO_RTT_FAC_7_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_7_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_7_MASK 0xffff0000 + + + + +#define RX_LOCATION_INFO_RTT_FAC_8_OFFSET 0x0000003c +#define RX_LOCATION_INFO_RTT_FAC_8_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_8_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_8_MASK 0x0000ffff + + + + +#define RX_LOCATION_INFO_RTT_FAC_9_OFFSET 0x0000003c +#define RX_LOCATION_INFO_RTT_FAC_9_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_9_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_9_MASK 0xffff0000 + + + + +#define RX_LOCATION_INFO_RTT_FAC_10_OFFSET 0x00000040 +#define RX_LOCATION_INFO_RTT_FAC_10_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_10_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_10_MASK 0x0000ffff + + + + +#define RX_LOCATION_INFO_RTT_FAC_11_OFFSET 0x00000040 +#define RX_LOCATION_INFO_RTT_FAC_11_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_11_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_11_MASK 0xffff0000 + + + + +#define RX_LOCATION_INFO_RTT_FAC_12_OFFSET 0x00000044 +#define RX_LOCATION_INFO_RTT_FAC_12_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_12_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_12_MASK 0x0000ffff + + + + +#define RX_LOCATION_INFO_RTT_FAC_13_OFFSET 0x00000044 +#define RX_LOCATION_INFO_RTT_FAC_13_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_13_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_13_MASK 0xffff0000 + + + + +#define RX_LOCATION_INFO_RTT_FAC_14_OFFSET 0x00000048 +#define RX_LOCATION_INFO_RTT_FAC_14_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_14_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_14_MASK 0x0000ffff + + + + +#define RX_LOCATION_INFO_RTT_FAC_15_OFFSET 0x00000048 +#define RX_LOCATION_INFO_RTT_FAC_15_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_15_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_15_MASK 0xffff0000 + + + + +#define RX_LOCATION_INFO_RTT_FAC_16_OFFSET 0x0000004c +#define RX_LOCATION_INFO_RTT_FAC_16_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_16_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_16_MASK 0x0000ffff + + + + +#define RX_LOCATION_INFO_RTT_FAC_17_OFFSET 0x0000004c +#define RX_LOCATION_INFO_RTT_FAC_17_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_17_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_17_MASK 0xffff0000 + + + + +#define RX_LOCATION_INFO_RTT_FAC_18_OFFSET 0x00000050 +#define RX_LOCATION_INFO_RTT_FAC_18_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_18_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_18_MASK 0x0000ffff + + + + +#define RX_LOCATION_INFO_RTT_FAC_19_OFFSET 0x00000050 +#define RX_LOCATION_INFO_RTT_FAC_19_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_19_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_19_MASK 0xffff0000 + + + + +#define RX_LOCATION_INFO_RTT_FAC_20_OFFSET 0x00000054 +#define RX_LOCATION_INFO_RTT_FAC_20_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_20_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_20_MASK 0x0000ffff + + + + +#define RX_LOCATION_INFO_RTT_FAC_21_OFFSET 0x00000054 +#define RX_LOCATION_INFO_RTT_FAC_21_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_21_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_21_MASK 0xffff0000 + + + + +#define RX_LOCATION_INFO_RTT_FAC_22_OFFSET 0x00000058 +#define RX_LOCATION_INFO_RTT_FAC_22_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_22_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_22_MASK 0x0000ffff + + + + +#define RX_LOCATION_INFO_RTT_FAC_23_OFFSET 0x00000058 +#define RX_LOCATION_INFO_RTT_FAC_23_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_23_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_23_MASK 0xffff0000 + + + + +#define RX_LOCATION_INFO_RTT_FAC_24_OFFSET 0x0000005c +#define RX_LOCATION_INFO_RTT_FAC_24_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_24_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_24_MASK 0x0000ffff + + + + +#define RX_LOCATION_INFO_RTT_FAC_25_OFFSET 0x0000005c +#define RX_LOCATION_INFO_RTT_FAC_25_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_25_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_25_MASK 0xffff0000 + + + + +#define RX_LOCATION_INFO_RTT_FAC_26_OFFSET 0x00000060 +#define RX_LOCATION_INFO_RTT_FAC_26_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_26_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_26_MASK 0x0000ffff + + + + +#define RX_LOCATION_INFO_RTT_FAC_27_OFFSET 0x00000060 +#define RX_LOCATION_INFO_RTT_FAC_27_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_27_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_27_MASK 0xffff0000 + + + + +#define RX_LOCATION_INFO_RTT_FAC_28_OFFSET 0x00000064 +#define RX_LOCATION_INFO_RTT_FAC_28_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_28_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_28_MASK 0x0000ffff + + + + +#define RX_LOCATION_INFO_RTT_FAC_29_OFFSET 0x00000064 +#define RX_LOCATION_INFO_RTT_FAC_29_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_29_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_29_MASK 0xffff0000 + + + + +#define RX_LOCATION_INFO_RTT_FAC_30_OFFSET 0x00000068 +#define RX_LOCATION_INFO_RTT_FAC_30_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_30_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_30_MASK 0x0000ffff + + + + +#define RX_LOCATION_INFO_RTT_FAC_31_OFFSET 0x00000068 +#define RX_LOCATION_INFO_RTT_FAC_31_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_31_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_31_MASK 0xffff0000 + + + + +#define RX_LOCATION_INFO_RESERVED_27A_OFFSET 0x0000006c +#define RX_LOCATION_INFO_RESERVED_27A_LSB 0 +#define RX_LOCATION_INFO_RESERVED_27A_MSB 31 +#define RX_LOCATION_INFO_RESERVED_27A_MASK 0xffffffff + + + +#endif diff --git a/hw/qcn9224/rx_mpdu_desc_info.h b/hw/qcn9224/rx_mpdu_desc_info.h new file mode 100644 index 000000000000..6d0fd23e4921 --- /dev/null +++ b/hw/qcn9224/rx_mpdu_desc_info.h @@ -0,0 +1,162 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RX_MPDU_DESC_INFO_H_ +#define _RX_MPDU_DESC_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2 + + +struct rx_mpdu_desc_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t msdu_count : 8, + fragment_flag : 1, + mpdu_retry_bit : 1, + ampdu_flag : 1, + bar_frame : 1, + pn_fields_contain_valid_info : 1, + raw_mpdu : 1, + more_fragment_flag : 1, + src_info : 12, + mpdu_qos_control_valid : 1, + tid : 4; + uint32_t peer_meta_data : 32; +#else + uint32_t tid : 4, + mpdu_qos_control_valid : 1, + src_info : 12, + more_fragment_flag : 1, + raw_mpdu : 1, + pn_fields_contain_valid_info : 1, + bar_frame : 1, + ampdu_flag : 1, + mpdu_retry_bit : 1, + fragment_flag : 1, + msdu_count : 8; + uint32_t peer_meta_data : 32; +#endif +}; + + + + +#define RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MSDU_COUNT_LSB 0 +#define RX_MPDU_DESC_INFO_MSDU_COUNT_MSB 7 +#define RX_MPDU_DESC_INFO_MSDU_COUNT_MASK 0x000000ff + + + + +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_LSB 8 +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MSB 8 +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MASK 0x00000100 + + + + +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_LSB 9 +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MSB 9 +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MASK 0x00000200 + + + + +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_LSB 10 +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MSB 10 +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK 0x00000400 + + + + +#define RX_MPDU_DESC_INFO_BAR_FRAME_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_BAR_FRAME_LSB 11 +#define RX_MPDU_DESC_INFO_BAR_FRAME_MSB 11 +#define RX_MPDU_DESC_INFO_BAR_FRAME_MASK 0x00000800 + + + + +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + + + + +#define RX_MPDU_DESC_INFO_RAW_MPDU_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_RAW_MPDU_LSB 13 +#define RX_MPDU_DESC_INFO_RAW_MPDU_MSB 13 +#define RX_MPDU_DESC_INFO_RAW_MPDU_MASK 0x00002000 + + + + +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MSB 14 +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 + + + + +#define RX_MPDU_DESC_INFO_SRC_INFO_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_SRC_INFO_LSB 15 +#define RX_MPDU_DESC_INFO_SRC_INFO_MSB 26 +#define RX_MPDU_DESC_INFO_SRC_INFO_MASK 0x07ff8000 + + + + +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_LSB 27 +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MSB 27 +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + + + + +#define RX_MPDU_DESC_INFO_TID_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_TID_LSB 28 +#define RX_MPDU_DESC_INFO_TID_MSB 31 +#define RX_MPDU_DESC_INFO_TID_MASK 0xf0000000 + + + + +#define RX_MPDU_DESC_INFO_PEER_META_DATA_OFFSET 0x00000004 +#define RX_MPDU_DESC_INFO_PEER_META_DATA_LSB 0 +#define RX_MPDU_DESC_INFO_PEER_META_DATA_MSB 31 +#define RX_MPDU_DESC_INFO_PEER_META_DATA_MASK 0xffffffff + + + +#endif diff --git a/hw/qcn9224/rx_mpdu_details.h b/hw/qcn9224/rx_mpdu_details.h new file mode 100644 index 000000000000..286d526aa827 --- /dev/null +++ b/hw/qcn9224/rx_mpdu_details.h @@ -0,0 +1,182 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RX_MPDU_DETAILS_H_ +#define _RX_MPDU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_RX_MPDU_DETAILS 4 + + +struct rx_mpdu_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info msdu_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; +#else + struct buffer_addr_info msdu_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; +#endif +}; + + + + + + + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + + + + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + + + + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + + + + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + + + + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + + + + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + + + + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + + + + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + + + + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + + + + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + + + + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + + + + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + + + + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + + + +#endif diff --git a/hw/qcn9224/rx_mpdu_end.h b/hw/qcn9224/rx_mpdu_end.h new file mode 100644 index 000000000000..3e5faf234f8c --- /dev/null +++ b/hw/qcn9224/rx_mpdu_end.h @@ -0,0 +1,284 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RX_MPDU_END_H_ +#define _RX_MPDU_END_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MPDU_END 4 + +#define NUM_OF_QWORDS_RX_MPDU_END 2 + + +struct rx_mpdu_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t reserved_1a : 11, + unsup_ktype_short_frame : 1, + rx_in_tx_decrypt_byp : 1, + overflow_err : 1, + mpdu_length_err : 1, + tkip_mic_err : 1, + decrypt_err : 1, + unencrypted_frame_err : 1, + pn_fields_contain_valid_info : 1, + fcs_err : 1, + msdu_length_err : 1, + rxdma0_destination_ring : 3, + rxdma1_destination_ring : 3, + decrypt_status_code : 3, + rx_bitmap_not_updated : 1, + reserved_1b : 1; + uint32_t reserved_2a : 15, + rxpcu_mgmt_sequence_nr_valid : 1, + rxpcu_mgmt_sequence_nr : 16; + uint32_t rxframe_assert_mlo_timestamp : 32; +#else + uint32_t phy_ppdu_id : 16, + reserved_0 : 7, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t reserved_1b : 1, + rx_bitmap_not_updated : 1, + decrypt_status_code : 3, + rxdma1_destination_ring : 3, + rxdma0_destination_ring : 3, + msdu_length_err : 1, + fcs_err : 1, + pn_fields_contain_valid_info : 1, + unencrypted_frame_err : 1, + decrypt_err : 1, + tkip_mic_err : 1, + mpdu_length_err : 1, + overflow_err : 1, + rx_in_tx_decrypt_byp : 1, + unsup_ktype_short_frame : 1, + reserved_1a : 11; + uint32_t rxpcu_mgmt_sequence_nr : 16, + rxpcu_mgmt_sequence_nr_valid : 1, + reserved_2a : 15; + uint32_t rxframe_assert_mlo_timestamp : 32; +#endif +}; + + + + +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 + + + + +#define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 +#define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc + + + + +#define RX_MPDU_END_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RESERVED_0_LSB 9 +#define RX_MPDU_END_RESERVED_0_MSB 15 +#define RX_MPDU_END_RESERVED_0_MASK 0x000000000000fe00 + + + + +#define RX_MPDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_MPDU_END_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_END_PHY_PPDU_ID_MSB 31 +#define RX_MPDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 + + + + +#define RX_MPDU_END_RESERVED_1A_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RESERVED_1A_LSB 32 +#define RX_MPDU_END_RESERVED_1A_MSB 42 +#define RX_MPDU_END_RESERVED_1A_MASK 0x000007ff00000000 + + + + +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x0000000000000000 +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB 43 +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB 43 +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK 0x0000080000000000 + + + + +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB 44 +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB 44 +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000100000000000 + + + + +#define RX_MPDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_OVERFLOW_ERR_LSB 45 +#define RX_MPDU_END_OVERFLOW_ERR_MSB 45 +#define RX_MPDU_END_OVERFLOW_ERR_MASK 0x0000200000000000 + + + + +#define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_MPDU_LENGTH_ERR_LSB 46 +#define RX_MPDU_END_MPDU_LENGTH_ERR_MSB 46 +#define RX_MPDU_END_MPDU_LENGTH_ERR_MASK 0x0000400000000000 + + + + +#define RX_MPDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_TKIP_MIC_ERR_LSB 47 +#define RX_MPDU_END_TKIP_MIC_ERR_MSB 47 +#define RX_MPDU_END_TKIP_MIC_ERR_MASK 0x0000800000000000 + + + + +#define RX_MPDU_END_DECRYPT_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_DECRYPT_ERR_LSB 48 +#define RX_MPDU_END_DECRYPT_ERR_MSB 48 +#define RX_MPDU_END_DECRYPT_ERR_MASK 0x0001000000000000 + + + + +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB 49 +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB 49 +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0002000000000000 + + + + +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000000000000 +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB 50 +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB 50 +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x0004000000000000 + + + + +#define RX_MPDU_END_FCS_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_FCS_ERR_LSB 51 +#define RX_MPDU_END_FCS_ERR_MSB 51 +#define RX_MPDU_END_FCS_ERR_MASK 0x0008000000000000 + + + + +#define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_MSDU_LENGTH_ERR_LSB 52 +#define RX_MPDU_END_MSDU_LENGTH_ERR_MSB 52 +#define RX_MPDU_END_MSDU_LENGTH_ERR_MASK 0x0010000000000000 + + + + +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_LSB 53 +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_MSB 55 +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_MASK 0x00e0000000000000 + + + + +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_LSB 56 +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_MSB 58 +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_MASK 0x0700000000000000 + + + + +#define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000000 +#define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB 59 +#define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB 61 +#define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK 0x3800000000000000 + + + + +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB 62 +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB 62 +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x4000000000000000 + + + + +#define RX_MPDU_END_RESERVED_1B_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RESERVED_1B_LSB 63 +#define RX_MPDU_END_RESERVED_1B_MSB 63 +#define RX_MPDU_END_RESERVED_1B_MASK 0x8000000000000000 + + + + +#define RX_MPDU_END_RESERVED_2A_OFFSET 0x0000000000000008 +#define RX_MPDU_END_RESERVED_2A_LSB 0 +#define RX_MPDU_END_RESERVED_2A_MSB 14 +#define RX_MPDU_END_RESERVED_2A_MASK 0x0000000000007fff + + + + +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET 0x0000000000000008 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB 15 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB 15 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK 0x0000000000008000 + + + + +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET 0x0000000000000008 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB 16 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB 31 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK 0x00000000ffff0000 + + + + +#define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_OFFSET 0x0000000000000008 +#define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_LSB 32 +#define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_MSB 63 +#define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_MASK 0xffffffff00000000 + + + +#endif diff --git a/hw/qcn9224/rx_mpdu_info.h b/hw/qcn9224/rx_mpdu_info.h new file mode 100644 index 000000000000..3997d555cfe4 --- /dev/null +++ b/hw/qcn9224/rx_mpdu_info.h @@ -0,0 +1,1250 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RX_MPDU_INFO_H_ +#define _RX_MPDU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rxpt_classify_info.h" +#define NUM_OF_DWORDS_RX_MPDU_INFO 30 + + +struct rx_mpdu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rxpt_classify_info rxpt_classify_info_details; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + receive_queue_number : 16, + pre_delim_err_warning : 1, + first_delim_err : 1, + reserved_2a : 6; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t epd_en : 1, + all_frames_shall_be_encrypted : 1, + encrypt_type : 4, + wep_key_width_for_variable_key : 2, + mesh_sta : 2, + bssid_hit : 1, + bssid_number : 4, + tid : 4, + reserved_7a : 13; + uint32_t peer_meta_data : 32; + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + ndp_frame : 1, + phy_err : 1, + phy_err_during_mpdu_header : 1, + protocol_version_err : 1, + ast_based_lookup_valid : 1, + ranging : 1, + reserved_9a : 1, + phy_ppdu_id : 16; + uint32_t ast_index : 16, + sw_peer_id : 16; + uint32_t mpdu_frame_control_valid : 1, + mpdu_duration_valid : 1, + mac_addr_ad1_valid : 1, + mac_addr_ad2_valid : 1, + mac_addr_ad3_valid : 1, + mac_addr_ad4_valid : 1, + mpdu_sequence_control_valid : 1, + mpdu_qos_control_valid : 1, + mpdu_ht_control_valid : 1, + frame_encryption_info_valid : 1, + mpdu_fragment_number : 4, + more_fragment_flag : 1, + reserved_11a : 1, + fr_ds : 1, + to_ds : 1, + encrypted : 1, + mpdu_retry : 1, + mpdu_sequence_number : 12; + uint32_t key_id_octet : 8, + new_peer_entry : 1, + decrypt_needed : 1, + decap_type : 2, + rx_insert_vlan_c_tag_padding : 1, + rx_insert_vlan_s_tag_padding : 1, + strip_vlan_c_tag_decap : 1, + strip_vlan_s_tag_decap : 1, + pre_delim_count : 12, + ampdu_flag : 1, + bar_frame : 1, + raw_mpdu : 1, + reserved_12 : 1; + uint32_t mpdu_length : 14, + first_mpdu : 1, + mcast_bcast : 1, + ast_index_not_found : 1, + ast_index_timeout : 1, + power_mgmt : 1, + non_qos : 1, + null_data : 1, + mgmt_type : 1, + ctrl_type : 1, + more_data : 1, + eosp : 1, + fragment_flag : 1, + order : 1, + u_apsd_trigger : 1, + encrypt_required : 1, + directed : 1, + amsdu_present : 1, + reserved_13 : 1; + uint32_t mpdu_frame_control_field : 16, + mpdu_duration_field : 16; + uint32_t mac_addr_ad1_31_0 : 32; + uint32_t mac_addr_ad1_47_32 : 16, + mac_addr_ad2_15_0 : 16; + uint32_t mac_addr_ad2_47_16 : 32; + uint32_t mac_addr_ad3_31_0 : 32; + uint32_t mac_addr_ad3_47_32 : 16, + mpdu_sequence_control_field : 16; + uint32_t mac_addr_ad4_31_0 : 32; + uint32_t mac_addr_ad4_47_32 : 16, + mpdu_qos_control_field : 16; + uint32_t mpdu_ht_control_field : 32; + uint32_t vdev_id : 8, + service_code : 9, + priority_valid : 1, + src_info : 12, + reserved_23a : 1, + multi_link_addr_ad1_ad2_valid : 1; + uint32_t multi_link_addr_ad1_31_0 : 32; + uint32_t multi_link_addr_ad1_47_32 : 16, + multi_link_addr_ad2_15_0 : 16; + uint32_t multi_link_addr_ad2_47_16 : 32; + uint32_t authorized_to_send_wds : 1, + reserved_27a : 31; + uint32_t reserved_28a : 32; + uint32_t reserved_29a : 32; +#else + struct rxpt_classify_info rxpt_classify_info_details; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t reserved_2a : 6, + first_delim_err : 1, + pre_delim_err_warning : 1, + receive_queue_number : 16, + rx_reo_queue_desc_addr_39_32 : 8; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t reserved_7a : 13, + tid : 4, + bssid_number : 4, + bssid_hit : 1, + mesh_sta : 2, + wep_key_width_for_variable_key : 2, + encrypt_type : 4, + all_frames_shall_be_encrypted : 1, + epd_en : 1; + uint32_t peer_meta_data : 32; + uint32_t phy_ppdu_id : 16, + reserved_9a : 1, + ranging : 1, + ast_based_lookup_valid : 1, + protocol_version_err : 1, + phy_err_during_mpdu_header : 1, + phy_err : 1, + ndp_frame : 1, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t sw_peer_id : 16, + ast_index : 16; + uint32_t mpdu_sequence_number : 12, + mpdu_retry : 1, + encrypted : 1, + to_ds : 1, + fr_ds : 1, + reserved_11a : 1, + more_fragment_flag : 1, + mpdu_fragment_number : 4, + frame_encryption_info_valid : 1, + mpdu_ht_control_valid : 1, + mpdu_qos_control_valid : 1, + mpdu_sequence_control_valid : 1, + mac_addr_ad4_valid : 1, + mac_addr_ad3_valid : 1, + mac_addr_ad2_valid : 1, + mac_addr_ad1_valid : 1, + mpdu_duration_valid : 1, + mpdu_frame_control_valid : 1; + uint32_t reserved_12 : 1, + raw_mpdu : 1, + bar_frame : 1, + ampdu_flag : 1, + pre_delim_count : 12, + strip_vlan_s_tag_decap : 1, + strip_vlan_c_tag_decap : 1, + rx_insert_vlan_s_tag_padding : 1, + rx_insert_vlan_c_tag_padding : 1, + decap_type : 2, + decrypt_needed : 1, + new_peer_entry : 1, + key_id_octet : 8; + uint32_t reserved_13 : 1, + amsdu_present : 1, + directed : 1, + encrypt_required : 1, + u_apsd_trigger : 1, + order : 1, + fragment_flag : 1, + eosp : 1, + more_data : 1, + ctrl_type : 1, + mgmt_type : 1, + null_data : 1, + non_qos : 1, + power_mgmt : 1, + ast_index_timeout : 1, + ast_index_not_found : 1, + mcast_bcast : 1, + first_mpdu : 1, + mpdu_length : 14; + uint32_t mpdu_duration_field : 16, + mpdu_frame_control_field : 16; + uint32_t mac_addr_ad1_31_0 : 32; + uint32_t mac_addr_ad2_15_0 : 16, + mac_addr_ad1_47_32 : 16; + uint32_t mac_addr_ad2_47_16 : 32; + uint32_t mac_addr_ad3_31_0 : 32; + uint32_t mpdu_sequence_control_field : 16, + mac_addr_ad3_47_32 : 16; + uint32_t mac_addr_ad4_31_0 : 32; + uint32_t mpdu_qos_control_field : 16, + mac_addr_ad4_47_32 : 16; + uint32_t mpdu_ht_control_field : 32; + uint32_t multi_link_addr_ad1_ad2_valid : 1, + reserved_23a : 1, + src_info : 12, + priority_valid : 1, + service_code : 9, + vdev_id : 8; + uint32_t multi_link_addr_ad1_31_0 : 32; + uint32_t multi_link_addr_ad2_15_0 : 16, + multi_link_addr_ad1_47_32 : 16; + uint32_t multi_link_addr_ad2_47_16 : 32; + uint32_t reserved_27a : 31, + authorized_to_send_wds : 1; + uint32_t reserved_28a : 32; + uint32_t reserved_29a : 32; +#endif +}; + + + + + + + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + + + + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 + + + + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + + + + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + + + + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + + + + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 + + + + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 + + + + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 + + + + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 + + + + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x00040000 + + + + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x00080000 + + + + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x00100000 + + + + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x00200000 + + + + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 22 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffc00000 + + + + +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + + + + +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + + + + +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_LSB 8 +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MSB 23 +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 + + + + +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008 +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_LSB 24 +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MSB 24 +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MASK 0x01000000 + + + + +#define RX_MPDU_INFO_FIRST_DELIM_ERR_OFFSET 0x00000008 +#define RX_MPDU_INFO_FIRST_DELIM_ERR_LSB 25 +#define RX_MPDU_INFO_FIRST_DELIM_ERR_MSB 25 +#define RX_MPDU_INFO_FIRST_DELIM_ERR_MASK 0x02000000 + + + + +#define RX_MPDU_INFO_RESERVED_2A_OFFSET 0x00000008 +#define RX_MPDU_INFO_RESERVED_2A_LSB 26 +#define RX_MPDU_INFO_RESERVED_2A_MSB 31 +#define RX_MPDU_INFO_RESERVED_2A_MASK 0xfc000000 + + + + +#define RX_MPDU_INFO_PN_31_0_OFFSET 0x0000000c +#define RX_MPDU_INFO_PN_31_0_LSB 0 +#define RX_MPDU_INFO_PN_31_0_MSB 31 +#define RX_MPDU_INFO_PN_31_0_MASK 0xffffffff + + + + +#define RX_MPDU_INFO_PN_63_32_OFFSET 0x00000010 +#define RX_MPDU_INFO_PN_63_32_LSB 0 +#define RX_MPDU_INFO_PN_63_32_MSB 31 +#define RX_MPDU_INFO_PN_63_32_MASK 0xffffffff + + + + +#define RX_MPDU_INFO_PN_95_64_OFFSET 0x00000014 +#define RX_MPDU_INFO_PN_95_64_LSB 0 +#define RX_MPDU_INFO_PN_95_64_MSB 31 +#define RX_MPDU_INFO_PN_95_64_MASK 0xffffffff + + + + +#define RX_MPDU_INFO_PN_127_96_OFFSET 0x00000018 +#define RX_MPDU_INFO_PN_127_96_LSB 0 +#define RX_MPDU_INFO_PN_127_96_MSB 31 +#define RX_MPDU_INFO_PN_127_96_MASK 0xffffffff + + + + +#define RX_MPDU_INFO_EPD_EN_OFFSET 0x0000001c +#define RX_MPDU_INFO_EPD_EN_LSB 0 +#define RX_MPDU_INFO_EPD_EN_MSB 0 +#define RX_MPDU_INFO_EPD_EN_MASK 0x00000001 + + + + +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 1 +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 + + + + +#define RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET 0x0000001c +#define RX_MPDU_INFO_ENCRYPT_TYPE_LSB 2 +#define RX_MPDU_INFO_ENCRYPT_TYPE_MSB 5 +#define RX_MPDU_INFO_ENCRYPT_TYPE_MASK 0x0000003c + + + + +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 7 +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 + + + + +#define RX_MPDU_INFO_MESH_STA_OFFSET 0x0000001c +#define RX_MPDU_INFO_MESH_STA_LSB 8 +#define RX_MPDU_INFO_MESH_STA_MSB 9 +#define RX_MPDU_INFO_MESH_STA_MASK 0x00000300 + + + + +#define RX_MPDU_INFO_BSSID_HIT_OFFSET 0x0000001c +#define RX_MPDU_INFO_BSSID_HIT_LSB 10 +#define RX_MPDU_INFO_BSSID_HIT_MSB 10 +#define RX_MPDU_INFO_BSSID_HIT_MASK 0x00000400 + + + + +#define RX_MPDU_INFO_BSSID_NUMBER_OFFSET 0x0000001c +#define RX_MPDU_INFO_BSSID_NUMBER_LSB 11 +#define RX_MPDU_INFO_BSSID_NUMBER_MSB 14 +#define RX_MPDU_INFO_BSSID_NUMBER_MASK 0x00007800 + + + + +#define RX_MPDU_INFO_TID_OFFSET 0x0000001c +#define RX_MPDU_INFO_TID_LSB 15 +#define RX_MPDU_INFO_TID_MSB 18 +#define RX_MPDU_INFO_TID_MASK 0x00078000 + + + + +#define RX_MPDU_INFO_RESERVED_7A_OFFSET 0x0000001c +#define RX_MPDU_INFO_RESERVED_7A_LSB 19 +#define RX_MPDU_INFO_RESERVED_7A_MSB 31 +#define RX_MPDU_INFO_RESERVED_7A_MASK 0xfff80000 + + + + +#define RX_MPDU_INFO_PEER_META_DATA_OFFSET 0x00000020 +#define RX_MPDU_INFO_PEER_META_DATA_LSB 0 +#define RX_MPDU_INFO_PEER_META_DATA_MSB 31 +#define RX_MPDU_INFO_PEER_META_DATA_MASK 0xffffffff + + + + +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024 +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + + + + +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_OFFSET 0x00000024 +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MASK 0x000001fc + + + + +#define RX_MPDU_INFO_NDP_FRAME_OFFSET 0x00000024 +#define RX_MPDU_INFO_NDP_FRAME_LSB 9 +#define RX_MPDU_INFO_NDP_FRAME_MSB 9 +#define RX_MPDU_INFO_NDP_FRAME_MASK 0x00000200 + + + + +#define RX_MPDU_INFO_PHY_ERR_OFFSET 0x00000024 +#define RX_MPDU_INFO_PHY_ERR_LSB 10 +#define RX_MPDU_INFO_PHY_ERR_MSB 10 +#define RX_MPDU_INFO_PHY_ERR_MASK 0x00000400 + + + + +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024 +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_LSB 11 +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MSB 11 +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 + + + + +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_OFFSET 0x00000024 +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_LSB 12 +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MSB 12 +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MASK 0x00001000 + + + + +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024 +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_LSB 13 +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MSB 13 +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MASK 0x00002000 + + + + +#define RX_MPDU_INFO_RANGING_OFFSET 0x00000024 +#define RX_MPDU_INFO_RANGING_LSB 14 +#define RX_MPDU_INFO_RANGING_MSB 14 +#define RX_MPDU_INFO_RANGING_MASK 0x00004000 + + + + +#define RX_MPDU_INFO_RESERVED_9A_OFFSET 0x00000024 +#define RX_MPDU_INFO_RESERVED_9A_LSB 15 +#define RX_MPDU_INFO_RESERVED_9A_MSB 15 +#define RX_MPDU_INFO_RESERVED_9A_MASK 0x00008000 + + + + +#define RX_MPDU_INFO_PHY_PPDU_ID_OFFSET 0x00000024 +#define RX_MPDU_INFO_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_INFO_PHY_PPDU_ID_MSB 31 +#define RX_MPDU_INFO_PHY_PPDU_ID_MASK 0xffff0000 + + + + +#define RX_MPDU_INFO_AST_INDEX_OFFSET 0x00000028 +#define RX_MPDU_INFO_AST_INDEX_LSB 0 +#define RX_MPDU_INFO_AST_INDEX_MSB 15 +#define RX_MPDU_INFO_AST_INDEX_MASK 0x0000ffff + + + + +#define RX_MPDU_INFO_SW_PEER_ID_OFFSET 0x00000028 +#define RX_MPDU_INFO_SW_PEER_ID_LSB 16 +#define RX_MPDU_INFO_SW_PEER_ID_MSB 31 +#define RX_MPDU_INFO_SW_PEER_ID_MASK 0xffff0000 + + + + +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_LSB 0 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MSB 0 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 + + + + +#define RX_MPDU_INFO_MPDU_DURATION_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_DURATION_VALID_LSB 1 +#define RX_MPDU_INFO_MPDU_DURATION_VALID_MSB 1 +#define RX_MPDU_INFO_MPDU_DURATION_VALID_MASK 0x00000002 + + + + +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_LSB 2 +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MSB 2 +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MASK 0x00000004 + + + + +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_LSB 3 +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MSB 3 +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MASK 0x00000008 + + + + +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_LSB 4 +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MSB 4 +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MASK 0x00000010 + + + + +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_LSB 5 +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MSB 5 +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MASK 0x00000020 + + + + +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 + + + + +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_LSB 7 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MSB 7 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 + + + + +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_LSB 8 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MSB 8 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MASK 0x00000100 + + + + +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_LSB 9 +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MSB 9 +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 + + + + +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_LSB 10 +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MSB 13 +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 + + + + +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MSB 14 +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 + + + + +#define RX_MPDU_INFO_RESERVED_11A_OFFSET 0x0000002c +#define RX_MPDU_INFO_RESERVED_11A_LSB 15 +#define RX_MPDU_INFO_RESERVED_11A_MSB 15 +#define RX_MPDU_INFO_RESERVED_11A_MASK 0x00008000 + + + + +#define RX_MPDU_INFO_FR_DS_OFFSET 0x0000002c +#define RX_MPDU_INFO_FR_DS_LSB 16 +#define RX_MPDU_INFO_FR_DS_MSB 16 +#define RX_MPDU_INFO_FR_DS_MASK 0x00010000 + + + + +#define RX_MPDU_INFO_TO_DS_OFFSET 0x0000002c +#define RX_MPDU_INFO_TO_DS_LSB 17 +#define RX_MPDU_INFO_TO_DS_MSB 17 +#define RX_MPDU_INFO_TO_DS_MASK 0x00020000 + + + + +#define RX_MPDU_INFO_ENCRYPTED_OFFSET 0x0000002c +#define RX_MPDU_INFO_ENCRYPTED_LSB 18 +#define RX_MPDU_INFO_ENCRYPTED_MSB 18 +#define RX_MPDU_INFO_ENCRYPTED_MASK 0x00040000 + + + + +#define RX_MPDU_INFO_MPDU_RETRY_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_RETRY_LSB 19 +#define RX_MPDU_INFO_MPDU_RETRY_MSB 19 +#define RX_MPDU_INFO_MPDU_RETRY_MASK 0x00080000 + + + + +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_LSB 20 +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MSB 31 +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 + + + + +#define RX_MPDU_INFO_KEY_ID_OCTET_OFFSET 0x00000030 +#define RX_MPDU_INFO_KEY_ID_OCTET_LSB 0 +#define RX_MPDU_INFO_KEY_ID_OCTET_MSB 7 +#define RX_MPDU_INFO_KEY_ID_OCTET_MASK 0x000000ff + + + + +#define RX_MPDU_INFO_NEW_PEER_ENTRY_OFFSET 0x00000030 +#define RX_MPDU_INFO_NEW_PEER_ENTRY_LSB 8 +#define RX_MPDU_INFO_NEW_PEER_ENTRY_MSB 8 +#define RX_MPDU_INFO_NEW_PEER_ENTRY_MASK 0x00000100 + + + + +#define RX_MPDU_INFO_DECRYPT_NEEDED_OFFSET 0x00000030 +#define RX_MPDU_INFO_DECRYPT_NEEDED_LSB 9 +#define RX_MPDU_INFO_DECRYPT_NEEDED_MSB 9 +#define RX_MPDU_INFO_DECRYPT_NEEDED_MASK 0x00000200 + + + + +#define RX_MPDU_INFO_DECAP_TYPE_OFFSET 0x00000030 +#define RX_MPDU_INFO_DECAP_TYPE_LSB 10 +#define RX_MPDU_INFO_DECAP_TYPE_MSB 11 +#define RX_MPDU_INFO_DECAP_TYPE_MASK 0x00000c00 + + + + +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 + + + + +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 + + + + +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_LSB 14 +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MSB 14 +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 + + + + +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_LSB 15 +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MSB 15 +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 + + + + +#define RX_MPDU_INFO_PRE_DELIM_COUNT_OFFSET 0x00000030 +#define RX_MPDU_INFO_PRE_DELIM_COUNT_LSB 16 +#define RX_MPDU_INFO_PRE_DELIM_COUNT_MSB 27 +#define RX_MPDU_INFO_PRE_DELIM_COUNT_MASK 0x0fff0000 + + + + +#define RX_MPDU_INFO_AMPDU_FLAG_OFFSET 0x00000030 +#define RX_MPDU_INFO_AMPDU_FLAG_LSB 28 +#define RX_MPDU_INFO_AMPDU_FLAG_MSB 28 +#define RX_MPDU_INFO_AMPDU_FLAG_MASK 0x10000000 + + + + +#define RX_MPDU_INFO_BAR_FRAME_OFFSET 0x00000030 +#define RX_MPDU_INFO_BAR_FRAME_LSB 29 +#define RX_MPDU_INFO_BAR_FRAME_MSB 29 +#define RX_MPDU_INFO_BAR_FRAME_MASK 0x20000000 + + + + +#define RX_MPDU_INFO_RAW_MPDU_OFFSET 0x00000030 +#define RX_MPDU_INFO_RAW_MPDU_LSB 30 +#define RX_MPDU_INFO_RAW_MPDU_MSB 30 +#define RX_MPDU_INFO_RAW_MPDU_MASK 0x40000000 + + + + +#define RX_MPDU_INFO_RESERVED_12_OFFSET 0x00000030 +#define RX_MPDU_INFO_RESERVED_12_LSB 31 +#define RX_MPDU_INFO_RESERVED_12_MSB 31 +#define RX_MPDU_INFO_RESERVED_12_MASK 0x80000000 + + + + +#define RX_MPDU_INFO_MPDU_LENGTH_OFFSET 0x00000034 +#define RX_MPDU_INFO_MPDU_LENGTH_LSB 0 +#define RX_MPDU_INFO_MPDU_LENGTH_MSB 13 +#define RX_MPDU_INFO_MPDU_LENGTH_MASK 0x00003fff + + + + +#define RX_MPDU_INFO_FIRST_MPDU_OFFSET 0x00000034 +#define RX_MPDU_INFO_FIRST_MPDU_LSB 14 +#define RX_MPDU_INFO_FIRST_MPDU_MSB 14 +#define RX_MPDU_INFO_FIRST_MPDU_MASK 0x00004000 + + + + +#define RX_MPDU_INFO_MCAST_BCAST_OFFSET 0x00000034 +#define RX_MPDU_INFO_MCAST_BCAST_LSB 15 +#define RX_MPDU_INFO_MCAST_BCAST_MSB 15 +#define RX_MPDU_INFO_MCAST_BCAST_MASK 0x00008000 + + + + +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_LSB 16 +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MSB 16 +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MASK 0x00010000 + + + + +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_OFFSET 0x00000034 +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_LSB 17 +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MSB 17 +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MASK 0x00020000 + + + + +#define RX_MPDU_INFO_POWER_MGMT_OFFSET 0x00000034 +#define RX_MPDU_INFO_POWER_MGMT_LSB 18 +#define RX_MPDU_INFO_POWER_MGMT_MSB 18 +#define RX_MPDU_INFO_POWER_MGMT_MASK 0x00040000 + + + + +#define RX_MPDU_INFO_NON_QOS_OFFSET 0x00000034 +#define RX_MPDU_INFO_NON_QOS_LSB 19 +#define RX_MPDU_INFO_NON_QOS_MSB 19 +#define RX_MPDU_INFO_NON_QOS_MASK 0x00080000 + + + + +#define RX_MPDU_INFO_NULL_DATA_OFFSET 0x00000034 +#define RX_MPDU_INFO_NULL_DATA_LSB 20 +#define RX_MPDU_INFO_NULL_DATA_MSB 20 +#define RX_MPDU_INFO_NULL_DATA_MASK 0x00100000 + + + + +#define RX_MPDU_INFO_MGMT_TYPE_OFFSET 0x00000034 +#define RX_MPDU_INFO_MGMT_TYPE_LSB 21 +#define RX_MPDU_INFO_MGMT_TYPE_MSB 21 +#define RX_MPDU_INFO_MGMT_TYPE_MASK 0x00200000 + + + + +#define RX_MPDU_INFO_CTRL_TYPE_OFFSET 0x00000034 +#define RX_MPDU_INFO_CTRL_TYPE_LSB 22 +#define RX_MPDU_INFO_CTRL_TYPE_MSB 22 +#define RX_MPDU_INFO_CTRL_TYPE_MASK 0x00400000 + + + + +#define RX_MPDU_INFO_MORE_DATA_OFFSET 0x00000034 +#define RX_MPDU_INFO_MORE_DATA_LSB 23 +#define RX_MPDU_INFO_MORE_DATA_MSB 23 +#define RX_MPDU_INFO_MORE_DATA_MASK 0x00800000 + + + + +#define RX_MPDU_INFO_EOSP_OFFSET 0x00000034 +#define RX_MPDU_INFO_EOSP_LSB 24 +#define RX_MPDU_INFO_EOSP_MSB 24 +#define RX_MPDU_INFO_EOSP_MASK 0x01000000 + + + + +#define RX_MPDU_INFO_FRAGMENT_FLAG_OFFSET 0x00000034 +#define RX_MPDU_INFO_FRAGMENT_FLAG_LSB 25 +#define RX_MPDU_INFO_FRAGMENT_FLAG_MSB 25 +#define RX_MPDU_INFO_FRAGMENT_FLAG_MASK 0x02000000 + + + + +#define RX_MPDU_INFO_ORDER_OFFSET 0x00000034 +#define RX_MPDU_INFO_ORDER_LSB 26 +#define RX_MPDU_INFO_ORDER_MSB 26 +#define RX_MPDU_INFO_ORDER_MASK 0x04000000 + + + + +#define RX_MPDU_INFO_U_APSD_TRIGGER_OFFSET 0x00000034 +#define RX_MPDU_INFO_U_APSD_TRIGGER_LSB 27 +#define RX_MPDU_INFO_U_APSD_TRIGGER_MSB 27 +#define RX_MPDU_INFO_U_APSD_TRIGGER_MASK 0x08000000 + + + + +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_OFFSET 0x00000034 +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_LSB 28 +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MSB 28 +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MASK 0x10000000 + + + + +#define RX_MPDU_INFO_DIRECTED_OFFSET 0x00000034 +#define RX_MPDU_INFO_DIRECTED_LSB 29 +#define RX_MPDU_INFO_DIRECTED_MSB 29 +#define RX_MPDU_INFO_DIRECTED_MASK 0x20000000 + + + + +#define RX_MPDU_INFO_AMSDU_PRESENT_OFFSET 0x00000034 +#define RX_MPDU_INFO_AMSDU_PRESENT_LSB 30 +#define RX_MPDU_INFO_AMSDU_PRESENT_MSB 30 +#define RX_MPDU_INFO_AMSDU_PRESENT_MASK 0x40000000 + + + + +#define RX_MPDU_INFO_RESERVED_13_OFFSET 0x00000034 +#define RX_MPDU_INFO_RESERVED_13_LSB 31 +#define RX_MPDU_INFO_RESERVED_13_MSB 31 +#define RX_MPDU_INFO_RESERVED_13_MASK 0x80000000 + + + + +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_LSB 0 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MSB 15 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff + + + + +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_OFFSET 0x00000038 +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_LSB 16 +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MASK 0xffff0000 + + + + +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MASK 0xffffffff + + + + +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MSB 15 +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MASK 0x0000ffff + + + + +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_LSB 16 +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MASK 0xffff0000 + + + + +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MASK 0xffffffff + + + + +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MASK 0xffffffff + + + + +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MSB 15 +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MASK 0x0000ffff + + + + +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 + + + + +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MASK 0xffffffff + + + + +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MSB 15 +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MASK 0x0000ffff + + + + +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_LSB 16 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 + + + + +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_LSB 0 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff + + + + +#define RX_MPDU_INFO_VDEV_ID_OFFSET 0x0000005c +#define RX_MPDU_INFO_VDEV_ID_LSB 0 +#define RX_MPDU_INFO_VDEV_ID_MSB 7 +#define RX_MPDU_INFO_VDEV_ID_MASK 0x000000ff + + + + +#define RX_MPDU_INFO_SERVICE_CODE_OFFSET 0x0000005c +#define RX_MPDU_INFO_SERVICE_CODE_LSB 8 +#define RX_MPDU_INFO_SERVICE_CODE_MSB 16 +#define RX_MPDU_INFO_SERVICE_CODE_MASK 0x0001ff00 + + + + +#define RX_MPDU_INFO_PRIORITY_VALID_OFFSET 0x0000005c +#define RX_MPDU_INFO_PRIORITY_VALID_LSB 17 +#define RX_MPDU_INFO_PRIORITY_VALID_MSB 17 +#define RX_MPDU_INFO_PRIORITY_VALID_MASK 0x00020000 + + + + +#define RX_MPDU_INFO_SRC_INFO_OFFSET 0x0000005c +#define RX_MPDU_INFO_SRC_INFO_LSB 18 +#define RX_MPDU_INFO_SRC_INFO_MSB 29 +#define RX_MPDU_INFO_SRC_INFO_MASK 0x3ffc0000 + + + + +#define RX_MPDU_INFO_RESERVED_23A_OFFSET 0x0000005c +#define RX_MPDU_INFO_RESERVED_23A_LSB 30 +#define RX_MPDU_INFO_RESERVED_23A_MSB 30 +#define RX_MPDU_INFO_RESERVED_23A_MASK 0x40000000 + + + + +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_OFFSET 0x0000005c +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_LSB 31 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_MSB 31 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_MASK 0x80000000 + + + + +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_OFFSET 0x00000060 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_LSB 0 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_MSB 31 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_MASK 0xffffffff + + + + +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_OFFSET 0x00000064 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_LSB 0 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_MSB 15 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_MASK 0x0000ffff + + + + +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_OFFSET 0x00000064 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_LSB 16 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_MSB 31 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_MASK 0xffff0000 + + + + +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_OFFSET 0x00000068 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_LSB 0 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_MSB 31 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_MASK 0xffffffff + + + + +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000006c +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_LSB 0 +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MSB 0 +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MASK 0x00000001 + + + + +#define RX_MPDU_INFO_RESERVED_27A_OFFSET 0x0000006c +#define RX_MPDU_INFO_RESERVED_27A_LSB 1 +#define RX_MPDU_INFO_RESERVED_27A_MSB 31 +#define RX_MPDU_INFO_RESERVED_27A_MASK 0xfffffffe + + + + +#define RX_MPDU_INFO_RESERVED_28A_OFFSET 0x00000070 +#define RX_MPDU_INFO_RESERVED_28A_LSB 0 +#define RX_MPDU_INFO_RESERVED_28A_MSB 31 +#define RX_MPDU_INFO_RESERVED_28A_MASK 0xffffffff + + + + +#define RX_MPDU_INFO_RESERVED_29A_OFFSET 0x00000074 +#define RX_MPDU_INFO_RESERVED_29A_LSB 0 +#define RX_MPDU_INFO_RESERVED_29A_MSB 31 +#define RX_MPDU_INFO_RESERVED_29A_MASK 0xffffffff + + + +#endif diff --git a/hw/qcn9224/rx_mpdu_link_ptr.h b/hw/qcn9224/rx_mpdu_link_ptr.h new file mode 100644 index 000000000000..c30666c5b228 --- /dev/null +++ b/hw/qcn9224/rx_mpdu_link_ptr.h @@ -0,0 +1,80 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RX_MPDU_LINK_PTR_H_ +#define _RX_MPDU_LINK_PTR_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2 + + +struct rx_mpdu_link_ptr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info mpdu_link_desc_addr_info; +#else + struct buffer_addr_info mpdu_link_desc_addr_info; +#endif +}; + + + + + + + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + +#endif diff --git a/hw/qcn9224/rx_mpdu_start.h b/hw/qcn9224/rx_mpdu_start.h new file mode 100644 index 000000000000..812c667da64d --- /dev/null +++ b/hw/qcn9224/rx_mpdu_start.h @@ -0,0 +1,1037 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RX_MPDU_START_H_ +#define _RX_MPDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_info.h" +#define NUM_OF_DWORDS_RX_MPDU_START 30 + +#define NUM_OF_QWORDS_RX_MPDU_START 15 + + +struct rx_mpdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_mpdu_info rx_mpdu_info_details; +#else + struct rx_mpdu_info rx_mpdu_info_details; +#endif +}; + + + + + + + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x000000000000001f + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x0000000000000060 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x0000000000000080 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x0000000000000100 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x0000000000000200 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x0000000000000400 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x0000000000003800 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x000000000001c000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x0000000000020000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x0000000000040000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x0000000000080000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x0000000000100000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x0000000000200000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 22 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0x00000000ffc00000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MSB 23 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x0000000000ffff00 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000000000008 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 24 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MSB 24 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x0000000001000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET 0x0000000000000008 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB 25 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MSB 25 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK 0x0000000002000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB 26 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK 0x00000000fc000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET 0x0000000000000008 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MASK 0xffffffff00000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET 0x0000000000000010 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MASK 0x00000000ffffffff + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET 0x0000000000000010 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MASK 0xffffffff00000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MASK 0x00000000ffffffff + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MASK 0x0000000100000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 33 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 33 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x0000000200000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB 34 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MSB 37 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK 0x0000003c00000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 38 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 39 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MESH_STA_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MESH_STA_LSB 40 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MESH_STA_MSB 41 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MESH_STA_MASK 0x0000030000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB 42 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MSB 42 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK 0x0000040000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB 43 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MSB 46 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK 0x0000780000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_LSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MSB 50 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MASK 0x0007800000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB 51 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK 0xfff8000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK 0x00000000ffffffff + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 33 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000300000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB 34 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MSB 40 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK 0x000001fc00000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB 41 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MSB 41 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK 0x0000020000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB 42 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MSB 42 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK 0x0000040000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 43 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MSB 43 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x0000080000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 44 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MSB 44 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x0000100000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 45 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MSB 45 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x0000200000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RANGING_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RANGING_LSB 46 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RANGING_MSB 46 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RANGING_MASK 0x0000400000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_LSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_MSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_MASK 0x0000800000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK 0xffff000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK 0x000000000000ffff + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK 0x00000000ffff0000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x0000000100000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 33 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MSB 33 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x0000000200000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 34 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MSB 34 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x0000000400000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 35 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MSB 35 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x0000000800000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 36 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MSB 36 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x0000001000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 37 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MSB 37 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x0000002000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 38 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MSB 38 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x0000004000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 39 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 39 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x0000008000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 40 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MSB 40 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x0000010000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 41 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MSB 41 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x0000020000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 42 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MSB 45 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x00003c0000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 46 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 46 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x0000400000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_LSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MASK 0x0000800000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_LSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MASK 0x0001000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_LSB 49 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MSB 49 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MASK 0x0002000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB 50 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MSB 50 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK 0x0004000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB 51 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MSB 51 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK 0x0008000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 52 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0xfff0000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK 0x00000000000000ff + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK 0x0000000000000100 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK 0x0000000000000200 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MSB 11 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK 0x0000000000000c00 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x0000000000001000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x0000000000002000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x0000000000004000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x0000000000008000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MSB 27 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK 0x000000000fff0000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB 28 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MSB 28 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK 0x0000000010000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB 29 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MSB 29 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK 0x0000000020000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB 30 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MSB 30 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK 0x0000000040000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK 0x0000000080000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MSB 45 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK 0x00003fff00000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB 46 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MSB 46 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK 0x0000400000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK 0x0000800000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x0001000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB 49 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MSB 49 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x0002000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB 50 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MSB 50 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK 0x0004000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_LSB 51 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MSB 51 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MASK 0x0008000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB 52 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MSB 52 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK 0x0010000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB 53 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MSB 53 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK 0x0020000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB 54 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MSB 54 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK 0x0040000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB 55 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MSB 55 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK 0x0080000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_LSB 56 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MSB 56 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MASK 0x0100000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB 57 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MSB 57 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x0200000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_LSB 58 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MSB 58 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MASK 0x0400000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB 59 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MSB 59 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK 0x0800000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB 60 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MSB 60 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK 0x1000000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_LSB 61 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MSB 61 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MASK 0x2000000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB 62 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MSB 62 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK 0x4000000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK 0x8000000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000038 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x000000000000ffff + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x0000000000000038 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0x00000000ffff0000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000000000000038 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff00000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x0000000000000040 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x000000000000ffff + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x0000000000000040 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0x00000000ffff0000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x0000000000000040 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff00000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x0000000000000048 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0x00000000ffffffff + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000000000000048 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff00000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000000000000048 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x0000000000000050 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0x00000000ffffffff + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x0000000000000050 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff00000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x0000000000000050 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x0000000000000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0x00000000ffffffff + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_OFFSET 0x0000000000000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MSB 39 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MASK 0x000000ff00000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000000000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_LSB 40 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MASK 0x0001ff0000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000000000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_LSB 49 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MSB 49 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MASK 0x0002000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000000000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_LSB 50 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MSB 61 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MASK 0x3ffc000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_OFFSET 0x0000000000000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_LSB 62 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MSB 62 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MASK 0x4000000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_AD2_VALID_OFFSET 0x0000000000000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_AD2_VALID_LSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_AD2_VALID_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_AD2_VALID_MASK 0x8000000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_31_0_OFFSET 0x0000000000000060 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_31_0_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_31_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_31_0_MASK 0x00000000ffffffff + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_47_32_OFFSET 0x0000000000000060 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_47_32_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_47_32_MSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_47_32_MASK 0x0000ffff00000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_15_0_OFFSET 0x0000000000000060 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_15_0_LSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_15_0_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_15_0_MASK 0xffff000000000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_47_16_OFFSET 0x0000000000000068 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_47_16_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_47_16_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_47_16_MASK 0x00000000ffffffff + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000000000000068 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MASK 0x0000000100000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000000000000068 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_LSB 33 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MASK 0xfffffffe00000000 + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_OFFSET 0x0000000000000070 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_MASK 0x00000000ffffffff + + + + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_OFFSET 0x0000000000000070 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MASK 0xffffffff00000000 + + + +#endif diff --git a/hw/qcn9224/rx_msdu_desc_info.h b/hw/qcn9224/rx_msdu_desc_info.h new file mode 100644 index 000000000000..b982268931a6 --- /dev/null +++ b/hw/qcn9224/rx_msdu_desc_info.h @@ -0,0 +1,212 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RX_MSDU_DESC_INFO_H_ +#define _RX_MSDU_DESC_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 1 + + +struct rx_msdu_desc_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t first_msdu_in_mpdu_flag : 1, + last_msdu_in_mpdu_flag : 1, + msdu_continuation : 1, + msdu_length : 14, + msdu_drop : 1, + sa_is_valid : 1, + da_is_valid : 1, + da_is_mcbc : 1, + l3_header_padding_msb : 1, + tcp_udp_chksum_fail : 1, + ip_chksum_fail : 1, + fr_ds : 1, + to_ds : 1, + intra_bss : 1, + dest_chip_id : 2, + decap_format : 2, + reserved_0a : 1; +#else + uint32_t reserved_0a : 1, + decap_format : 2, + dest_chip_id : 2, + intra_bss : 1, + to_ds : 1, + fr_ds : 1, + ip_chksum_fail : 1, + tcp_udp_chksum_fail : 1, + l3_header_padding_msb : 1, + da_is_mcbc : 1, + da_is_valid : 1, + sa_is_valid : 1, + msdu_drop : 1, + msdu_length : 14, + msdu_continuation : 1, + last_msdu_in_mpdu_flag : 1, + first_msdu_in_mpdu_flag : 1; +#endif +}; + + + + +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + + + +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + + + +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK 0x00000004 + + + + +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3 +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MSB 16 +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8 + + + + +#define RX_MSDU_DESC_INFO_MSDU_DROP_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_MSDU_DROP_LSB 17 +#define RX_MSDU_DESC_INFO_MSDU_DROP_MSB 17 +#define RX_MSDU_DESC_INFO_MSDU_DROP_MASK 0x00020000 + + + + +#define RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_SA_IS_VALID_LSB 18 +#define RX_MSDU_DESC_INFO_SA_IS_VALID_MSB 18 +#define RX_MSDU_DESC_INFO_SA_IS_VALID_MASK 0x00040000 + + + + +#define RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DA_IS_VALID_LSB 19 +#define RX_MSDU_DESC_INFO_DA_IS_VALID_MSB 19 +#define RX_MSDU_DESC_INFO_DA_IS_VALID_MASK 0x00080000 + + + + +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_LSB 20 +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MSB 20 +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK 0x00100000 + + + + +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + + + +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + + + +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK 0x00800000 + + + + +#define RX_MSDU_DESC_INFO_FR_DS_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_FR_DS_LSB 24 +#define RX_MSDU_DESC_INFO_FR_DS_MSB 24 +#define RX_MSDU_DESC_INFO_FR_DS_MASK 0x01000000 + + + + +#define RX_MSDU_DESC_INFO_TO_DS_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_TO_DS_LSB 25 +#define RX_MSDU_DESC_INFO_TO_DS_MSB 25 +#define RX_MSDU_DESC_INFO_TO_DS_MASK 0x02000000 + + + + +#define RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_INTRA_BSS_LSB 26 +#define RX_MSDU_DESC_INFO_INTRA_BSS_MSB 26 +#define RX_MSDU_DESC_INFO_INTRA_BSS_MASK 0x04000000 + + + + +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MASK 0x18000000 + + + + +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_LSB 29 +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MSB 30 +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MASK 0x60000000 + + + + +#define RX_MSDU_DESC_INFO_RESERVED_0A_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_RESERVED_0A_LSB 31 +#define RX_MSDU_DESC_INFO_RESERVED_0A_MSB 31 +#define RX_MSDU_DESC_INFO_RESERVED_0A_MASK 0x80000000 + + + +#endif diff --git a/hw/qcn9224/rx_msdu_details.h b/hw/qcn9224/rx_msdu_details.h new file mode 100644 index 000000000000..39bfe25b0f80 --- /dev/null +++ b/hw/qcn9224/rx_msdu_details.h @@ -0,0 +1,276 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RX_MSDU_DETAILS_H_ +#define _RX_MSDU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_msdu_desc_info.h" +#include "rx_msdu_ext_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4 + + +struct rx_msdu_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buffer_addr_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; +#else + struct buffer_addr_info buffer_addr_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; +#endif +}; + + + + + + + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + + + + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + + + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + + + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + + + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + + + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + + + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + + + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + + + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + + + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + + + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + + + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + + + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + + + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + + + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + + + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + + + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + + + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000 + + + + + + + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + + + + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + + + + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + + + + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + + + + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + + + + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + + + +#endif diff --git a/hw/qcn9224/rx_msdu_end.h b/hw/qcn9224/rx_msdu_end.h new file mode 100644 index 000000000000..53182070b3fe --- /dev/null +++ b/hw/qcn9224/rx_msdu_end.h @@ -0,0 +1,1574 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RX_MSDU_END_H_ +#define _RX_MSDU_END_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MSDU_END 32 + +#define NUM_OF_QWORDS_RX_MSDU_END 16 + + +struct rx_msdu_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t ip_hdr_chksum : 16, + reported_mpdu_length : 14, + reserved_1a : 2; + uint32_t reserved_2a : 8, + cce_super_rule : 6, + cce_classify_not_done_truncate : 1, + cce_classify_not_done_cce_dis : 1, + cumulative_l3_checksum : 16; + uint32_t rule_indication_31_0 : 32; + uint32_t ipv6_options_crc : 32; + uint32_t da_offset : 6, + sa_offset : 6, + da_offset_valid : 1, + sa_offset_valid : 1, + reserved_5a : 2, + l3_type : 16; + uint32_t rule_indication_63_32 : 32; + uint32_t tcp_seq_number : 32; + uint32_t tcp_ack_number : 32; + uint32_t tcp_flag : 9, + lro_eligible : 1, + reserved_9a : 6, + window_size : 16; + uint32_t sa_sw_peer_id : 16, + sa_idx_timeout : 1, + da_idx_timeout : 1, + to_ds : 1, + tid : 4, + sa_is_valid : 1, + da_is_valid : 1, + da_is_mcbc : 1, + l3_header_padding : 2, + first_msdu : 1, + last_msdu : 1, + fr_ds : 1, + ip_chksum_fail_copy : 1; + uint32_t sa_idx : 16, + da_idx_or_sw_peer_id : 16; + uint32_t msdu_drop : 1, + reo_destination_indication : 5, + flow_idx : 20, + use_ppe : 1, + mesh_sta : 2, + vlan_ctag_stripped : 1, + vlan_stag_stripped : 1, + fragment_flag : 1; + uint32_t fse_metadata : 32; + uint32_t cce_metadata : 16, + tcp_udp_chksum : 16; + uint32_t aggregation_count : 8, + flow_aggregation_continuation : 1, + fisa_timeout : 1, + tcp_udp_chksum_fail_copy : 1, + msdu_limit_error : 1, + flow_idx_timeout : 1, + flow_idx_invalid : 1, + cce_match : 1, + amsdu_parser_error : 1, + cumulative_ip_length : 16; + uint32_t key_id_octet : 8, + reserved_16a : 24; + uint32_t reserved_17a : 6, + service_code : 9, + priority_valid : 1, + intra_bss : 1, + dest_chip_id : 2, + multicast_echo : 1, + wds_learning_event : 1, + wds_roaming_event : 1, + wds_keep_alive_event : 1, + reserved_17b : 9; + uint32_t msdu_length : 14, + stbc : 1, + ipsec_esp : 1, + l3_offset : 7, + ipsec_ah : 1, + l4_offset : 8; + uint32_t msdu_number : 8, + decap_format : 2, + ipv4_proto : 1, + ipv6_proto : 1, + tcp_proto : 1, + udp_proto : 1, + ip_frag : 1, + tcp_only_ack : 1, + da_is_bcast_mcast : 1, + toeplitz_hash_sel : 2, + ip_fixed_header_valid : 1, + ip_extn_header_valid : 1, + tcp_udp_header_valid : 1, + mesh_control_present : 1, + ldpc : 1, + ip4_protocol_ip6_next_header : 8; + uint32_t vlan_ctag_ci : 16, + vlan_stag_ci : 16; + uint32_t peer_meta_data : 32; + uint32_t user_rssi : 8, + pkt_type : 4, + sgi : 2, + rate_mcs : 4, + receive_bandwidth : 3, + reception_type : 3, + mimo_ss_bitmap : 7, + msdu_done_copy : 1; + uint32_t flow_id_toeplitz : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t toeplitz_hash_2_or_4 : 32; + uint32_t reserved_28a : 16, + sa_15_0 : 16; + uint32_t sa_47_16 : 32; + uint32_t first_mpdu : 1, + reserved_30a : 1, + mcast_bcast : 1, + ast_index_not_found : 1, + ast_index_timeout : 1, + power_mgmt : 1, + non_qos : 1, + null_data : 1, + mgmt_type : 1, + ctrl_type : 1, + more_data : 1, + eosp : 1, + a_msdu_error : 1, + reserved_30b : 1, + order : 1, + wifi_parser_error : 1, + overflow_err : 1, + msdu_length_err : 1, + tcp_udp_chksum_fail : 1, + ip_chksum_fail : 1, + sa_idx_invalid : 1, + da_idx_invalid : 1, + amsdu_addr_mismatch : 1, + rx_in_tx_decrypt_byp : 1, + encrypt_required : 1, + directed : 1, + buffer_fragment : 1, + mpdu_length_err : 1, + tkip_mic_err : 1, + decrypt_err : 1, + unencrypted_frame_err : 1, + fcs_err : 1; + uint32_t reserved_31a : 10, + decrypt_status_code : 3, + rx_bitmap_not_updated : 1, + reserved_31b : 17, + msdu_done : 1; +#else + uint32_t phy_ppdu_id : 16, + reserved_0 : 7, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t reserved_1a : 2, + reported_mpdu_length : 14, + ip_hdr_chksum : 16; + uint32_t cumulative_l3_checksum : 16, + cce_classify_not_done_cce_dis : 1, + cce_classify_not_done_truncate : 1, + cce_super_rule : 6, + reserved_2a : 8; + uint32_t rule_indication_31_0 : 32; + uint32_t ipv6_options_crc : 32; + uint32_t l3_type : 16, + reserved_5a : 2, + sa_offset_valid : 1, + da_offset_valid : 1, + sa_offset : 6, + da_offset : 6; + uint32_t rule_indication_63_32 : 32; + uint32_t tcp_seq_number : 32; + uint32_t tcp_ack_number : 32; + uint32_t window_size : 16, + reserved_9a : 6, + lro_eligible : 1, + tcp_flag : 9; + uint32_t ip_chksum_fail_copy : 1, + fr_ds : 1, + last_msdu : 1, + first_msdu : 1, + l3_header_padding : 2, + da_is_mcbc : 1, + da_is_valid : 1, + sa_is_valid : 1, + tid : 4, + to_ds : 1, + da_idx_timeout : 1, + sa_idx_timeout : 1, + sa_sw_peer_id : 16; + uint32_t da_idx_or_sw_peer_id : 16, + sa_idx : 16; + uint32_t fragment_flag : 1, + vlan_stag_stripped : 1, + vlan_ctag_stripped : 1, + mesh_sta : 2, + use_ppe : 1, + flow_idx : 20, + reo_destination_indication : 5, + msdu_drop : 1; + uint32_t fse_metadata : 32; + uint32_t tcp_udp_chksum : 16, + cce_metadata : 16; + uint32_t cumulative_ip_length : 16, + amsdu_parser_error : 1, + cce_match : 1, + flow_idx_invalid : 1, + flow_idx_timeout : 1, + msdu_limit_error : 1, + tcp_udp_chksum_fail_copy : 1, + fisa_timeout : 1, + flow_aggregation_continuation : 1, + aggregation_count : 8; + uint32_t reserved_16a : 24, + key_id_octet : 8; + uint32_t reserved_17b : 9, + wds_keep_alive_event : 1, + wds_roaming_event : 1, + wds_learning_event : 1, + multicast_echo : 1, + dest_chip_id : 2, + intra_bss : 1, + priority_valid : 1, + service_code : 9, + reserved_17a : 6; + uint32_t l4_offset : 8, + ipsec_ah : 1, + l3_offset : 7, + ipsec_esp : 1, + stbc : 1, + msdu_length : 14; + uint32_t ip4_protocol_ip6_next_header : 8, + ldpc : 1, + mesh_control_present : 1, + tcp_udp_header_valid : 1, + ip_extn_header_valid : 1, + ip_fixed_header_valid : 1, + toeplitz_hash_sel : 2, + da_is_bcast_mcast : 1, + tcp_only_ack : 1, + ip_frag : 1, + udp_proto : 1, + tcp_proto : 1, + ipv6_proto : 1, + ipv4_proto : 1, + decap_format : 2, + msdu_number : 8; + uint32_t vlan_stag_ci : 16, + vlan_ctag_ci : 16; + uint32_t peer_meta_data : 32; + uint32_t msdu_done_copy : 1, + mimo_ss_bitmap : 7, + reception_type : 3, + receive_bandwidth : 3, + rate_mcs : 4, + sgi : 2, + pkt_type : 4, + user_rssi : 8; + uint32_t flow_id_toeplitz : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t toeplitz_hash_2_or_4 : 32; + uint32_t sa_15_0 : 16, + reserved_28a : 16; + uint32_t sa_47_16 : 32; + uint32_t fcs_err : 1, + unencrypted_frame_err : 1, + decrypt_err : 1, + tkip_mic_err : 1, + mpdu_length_err : 1, + buffer_fragment : 1, + directed : 1, + encrypt_required : 1, + rx_in_tx_decrypt_byp : 1, + amsdu_addr_mismatch : 1, + da_idx_invalid : 1, + sa_idx_invalid : 1, + ip_chksum_fail : 1, + tcp_udp_chksum_fail : 1, + msdu_length_err : 1, + overflow_err : 1, + wifi_parser_error : 1, + order : 1, + reserved_30b : 1, + a_msdu_error : 1, + eosp : 1, + more_data : 1, + ctrl_type : 1, + mgmt_type : 1, + null_data : 1, + non_qos : 1, + power_mgmt : 1, + ast_index_timeout : 1, + ast_index_not_found : 1, + mcast_bcast : 1, + reserved_30a : 1, + first_mpdu : 1; + uint32_t msdu_done : 1, + reserved_31b : 17, + rx_bitmap_not_updated : 1, + decrypt_status_code : 3, + reserved_31a : 10; +#endif +}; + + + + +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 + + + + +#define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 +#define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc + + + + +#define RX_MSDU_END_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_MSDU_END_RESERVED_0_LSB 9 +#define RX_MSDU_END_RESERVED_0_MSB 15 +#define RX_MSDU_END_RESERVED_0_MASK 0x000000000000fe00 + + + + +#define RX_MSDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_MSDU_END_PHY_PPDU_ID_LSB 16 +#define RX_MSDU_END_PHY_PPDU_ID_MSB 31 +#define RX_MSDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 + + + + +#define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET 0x0000000000000000 +#define RX_MSDU_END_IP_HDR_CHKSUM_LSB 32 +#define RX_MSDU_END_IP_HDR_CHKSUM_MSB 47 +#define RX_MSDU_END_IP_HDR_CHKSUM_MASK 0x0000ffff00000000 + + + + +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET 0x0000000000000000 +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB 48 +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB 61 +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK 0x3fff000000000000 + + + + +#define RX_MSDU_END_RESERVED_1A_OFFSET 0x0000000000000000 +#define RX_MSDU_END_RESERVED_1A_LSB 62 +#define RX_MSDU_END_RESERVED_1A_MSB 63 +#define RX_MSDU_END_RESERVED_1A_MASK 0xc000000000000000 + + + + +#define RX_MSDU_END_RESERVED_2A_OFFSET 0x0000000000000008 +#define RX_MSDU_END_RESERVED_2A_LSB 0 +#define RX_MSDU_END_RESERVED_2A_MSB 7 +#define RX_MSDU_END_RESERVED_2A_MASK 0x00000000000000ff + + + + +#define RX_MSDU_END_CCE_SUPER_RULE_OFFSET 0x0000000000000008 +#define RX_MSDU_END_CCE_SUPER_RULE_LSB 8 +#define RX_MSDU_END_CCE_SUPER_RULE_MSB 13 +#define RX_MSDU_END_CCE_SUPER_RULE_MASK 0x0000000000003f00 + + + + +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x0000000000000008 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB 14 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x0000000000004000 + + + + +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x0000000000000008 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB 15 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x0000000000008000 + + + + +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET 0x0000000000000008 +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB 16 +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB 31 +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK 0x00000000ffff0000 + + + + +#define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET 0x0000000000000008 +#define RX_MSDU_END_RULE_INDICATION_31_0_LSB 32 +#define RX_MSDU_END_RULE_INDICATION_31_0_MSB 63 +#define RX_MSDU_END_RULE_INDICATION_31_0_MASK 0xffffffff00000000 + + + + +#define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET 0x0000000000000010 +#define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB 0 +#define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB 31 +#define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK 0x00000000ffffffff + + + + +#define RX_MSDU_END_DA_OFFSET_OFFSET 0x0000000000000010 +#define RX_MSDU_END_DA_OFFSET_LSB 32 +#define RX_MSDU_END_DA_OFFSET_MSB 37 +#define RX_MSDU_END_DA_OFFSET_MASK 0x0000003f00000000 + + + + +#define RX_MSDU_END_SA_OFFSET_OFFSET 0x0000000000000010 +#define RX_MSDU_END_SA_OFFSET_LSB 38 +#define RX_MSDU_END_SA_OFFSET_MSB 43 +#define RX_MSDU_END_SA_OFFSET_MASK 0x00000fc000000000 + + + + +#define RX_MSDU_END_DA_OFFSET_VALID_OFFSET 0x0000000000000010 +#define RX_MSDU_END_DA_OFFSET_VALID_LSB 44 +#define RX_MSDU_END_DA_OFFSET_VALID_MSB 44 +#define RX_MSDU_END_DA_OFFSET_VALID_MASK 0x0000100000000000 + + + + +#define RX_MSDU_END_SA_OFFSET_VALID_OFFSET 0x0000000000000010 +#define RX_MSDU_END_SA_OFFSET_VALID_LSB 45 +#define RX_MSDU_END_SA_OFFSET_VALID_MSB 45 +#define RX_MSDU_END_SA_OFFSET_VALID_MASK 0x0000200000000000 + + + + +#define RX_MSDU_END_RESERVED_5A_OFFSET 0x0000000000000010 +#define RX_MSDU_END_RESERVED_5A_LSB 46 +#define RX_MSDU_END_RESERVED_5A_MSB 47 +#define RX_MSDU_END_RESERVED_5A_MASK 0x0000c00000000000 + + + + +#define RX_MSDU_END_L3_TYPE_OFFSET 0x0000000000000010 +#define RX_MSDU_END_L3_TYPE_LSB 48 +#define RX_MSDU_END_L3_TYPE_MSB 63 +#define RX_MSDU_END_L3_TYPE_MASK 0xffff000000000000 + + + + +#define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET 0x0000000000000018 +#define RX_MSDU_END_RULE_INDICATION_63_32_LSB 0 +#define RX_MSDU_END_RULE_INDICATION_63_32_MSB 31 +#define RX_MSDU_END_RULE_INDICATION_63_32_MASK 0x00000000ffffffff + + + + +#define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET 0x0000000000000018 +#define RX_MSDU_END_TCP_SEQ_NUMBER_LSB 32 +#define RX_MSDU_END_TCP_SEQ_NUMBER_MSB 63 +#define RX_MSDU_END_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 + + + + +#define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET 0x0000000000000020 +#define RX_MSDU_END_TCP_ACK_NUMBER_LSB 0 +#define RX_MSDU_END_TCP_ACK_NUMBER_MSB 31 +#define RX_MSDU_END_TCP_ACK_NUMBER_MASK 0x00000000ffffffff + + + + +#define RX_MSDU_END_TCP_FLAG_OFFSET 0x0000000000000020 +#define RX_MSDU_END_TCP_FLAG_LSB 32 +#define RX_MSDU_END_TCP_FLAG_MSB 40 +#define RX_MSDU_END_TCP_FLAG_MASK 0x000001ff00000000 + + + + +#define RX_MSDU_END_LRO_ELIGIBLE_OFFSET 0x0000000000000020 +#define RX_MSDU_END_LRO_ELIGIBLE_LSB 41 +#define RX_MSDU_END_LRO_ELIGIBLE_MSB 41 +#define RX_MSDU_END_LRO_ELIGIBLE_MASK 0x0000020000000000 + + + + +#define RX_MSDU_END_RESERVED_9A_OFFSET 0x0000000000000020 +#define RX_MSDU_END_RESERVED_9A_LSB 42 +#define RX_MSDU_END_RESERVED_9A_MSB 47 +#define RX_MSDU_END_RESERVED_9A_MASK 0x0000fc0000000000 + + + + +#define RX_MSDU_END_WINDOW_SIZE_OFFSET 0x0000000000000020 +#define RX_MSDU_END_WINDOW_SIZE_LSB 48 +#define RX_MSDU_END_WINDOW_SIZE_MSB 63 +#define RX_MSDU_END_WINDOW_SIZE_MASK 0xffff000000000000 + + + + +#define RX_MSDU_END_SA_SW_PEER_ID_OFFSET 0x0000000000000028 +#define RX_MSDU_END_SA_SW_PEER_ID_LSB 0 +#define RX_MSDU_END_SA_SW_PEER_ID_MSB 15 +#define RX_MSDU_END_SA_SW_PEER_ID_MASK 0x000000000000ffff + + + + +#define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET 0x0000000000000028 +#define RX_MSDU_END_SA_IDX_TIMEOUT_LSB 16 +#define RX_MSDU_END_SA_IDX_TIMEOUT_MSB 16 +#define RX_MSDU_END_SA_IDX_TIMEOUT_MASK 0x0000000000010000 + + + + +#define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET 0x0000000000000028 +#define RX_MSDU_END_DA_IDX_TIMEOUT_LSB 17 +#define RX_MSDU_END_DA_IDX_TIMEOUT_MSB 17 +#define RX_MSDU_END_DA_IDX_TIMEOUT_MASK 0x0000000000020000 + + + + +#define RX_MSDU_END_TO_DS_OFFSET 0x0000000000000028 +#define RX_MSDU_END_TO_DS_LSB 18 +#define RX_MSDU_END_TO_DS_MSB 18 +#define RX_MSDU_END_TO_DS_MASK 0x0000000000040000 + + + + +#define RX_MSDU_END_TID_OFFSET 0x0000000000000028 +#define RX_MSDU_END_TID_LSB 19 +#define RX_MSDU_END_TID_MSB 22 +#define RX_MSDU_END_TID_MASK 0x0000000000780000 + + + + +#define RX_MSDU_END_SA_IS_VALID_OFFSET 0x0000000000000028 +#define RX_MSDU_END_SA_IS_VALID_LSB 23 +#define RX_MSDU_END_SA_IS_VALID_MSB 23 +#define RX_MSDU_END_SA_IS_VALID_MASK 0x0000000000800000 + + + + +#define RX_MSDU_END_DA_IS_VALID_OFFSET 0x0000000000000028 +#define RX_MSDU_END_DA_IS_VALID_LSB 24 +#define RX_MSDU_END_DA_IS_VALID_MSB 24 +#define RX_MSDU_END_DA_IS_VALID_MASK 0x0000000001000000 + + + + +#define RX_MSDU_END_DA_IS_MCBC_OFFSET 0x0000000000000028 +#define RX_MSDU_END_DA_IS_MCBC_LSB 25 +#define RX_MSDU_END_DA_IS_MCBC_MSB 25 +#define RX_MSDU_END_DA_IS_MCBC_MASK 0x0000000002000000 + + + + +#define RX_MSDU_END_L3_HEADER_PADDING_OFFSET 0x0000000000000028 +#define RX_MSDU_END_L3_HEADER_PADDING_LSB 26 +#define RX_MSDU_END_L3_HEADER_PADDING_MSB 27 +#define RX_MSDU_END_L3_HEADER_PADDING_MASK 0x000000000c000000 + + + + +#define RX_MSDU_END_FIRST_MSDU_OFFSET 0x0000000000000028 +#define RX_MSDU_END_FIRST_MSDU_LSB 28 +#define RX_MSDU_END_FIRST_MSDU_MSB 28 +#define RX_MSDU_END_FIRST_MSDU_MASK 0x0000000010000000 + + + + +#define RX_MSDU_END_LAST_MSDU_OFFSET 0x0000000000000028 +#define RX_MSDU_END_LAST_MSDU_LSB 29 +#define RX_MSDU_END_LAST_MSDU_MSB 29 +#define RX_MSDU_END_LAST_MSDU_MASK 0x0000000020000000 + + + + +#define RX_MSDU_END_FR_DS_OFFSET 0x0000000000000028 +#define RX_MSDU_END_FR_DS_LSB 30 +#define RX_MSDU_END_FR_DS_MSB 30 +#define RX_MSDU_END_FR_DS_MASK 0x0000000040000000 + + + + +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000028 +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB 31 +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB 31 +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK 0x0000000080000000 + + + + +#define RX_MSDU_END_SA_IDX_OFFSET 0x0000000000000028 +#define RX_MSDU_END_SA_IDX_LSB 32 +#define RX_MSDU_END_SA_IDX_MSB 47 +#define RX_MSDU_END_SA_IDX_MASK 0x0000ffff00000000 + + + + +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000000000000028 +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB 48 +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB 63 +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK 0xffff000000000000 + + + + +#define RX_MSDU_END_MSDU_DROP_OFFSET 0x0000000000000030 +#define RX_MSDU_END_MSDU_DROP_LSB 0 +#define RX_MSDU_END_MSDU_DROP_MSB 0 +#define RX_MSDU_END_MSDU_DROP_MASK 0x0000000000000001 + + + + +#define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000030 +#define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB 1 +#define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB 5 +#define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK 0x000000000000003e + + + + +#define RX_MSDU_END_FLOW_IDX_OFFSET 0x0000000000000030 +#define RX_MSDU_END_FLOW_IDX_LSB 6 +#define RX_MSDU_END_FLOW_IDX_MSB 25 +#define RX_MSDU_END_FLOW_IDX_MASK 0x0000000003ffffc0 + + + + +#define RX_MSDU_END_USE_PPE_OFFSET 0x0000000000000030 +#define RX_MSDU_END_USE_PPE_LSB 26 +#define RX_MSDU_END_USE_PPE_MSB 26 +#define RX_MSDU_END_USE_PPE_MASK 0x0000000004000000 + + + + +#define RX_MSDU_END_MESH_STA_OFFSET 0x0000000000000030 +#define RX_MSDU_END_MESH_STA_LSB 27 +#define RX_MSDU_END_MESH_STA_MSB 28 +#define RX_MSDU_END_MESH_STA_MASK 0x0000000018000000 + + + + +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_OFFSET 0x0000000000000030 +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_LSB 29 +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MSB 29 +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MASK 0x0000000020000000 + + + + +#define RX_MSDU_END_VLAN_STAG_STRIPPED_OFFSET 0x0000000000000030 +#define RX_MSDU_END_VLAN_STAG_STRIPPED_LSB 30 +#define RX_MSDU_END_VLAN_STAG_STRIPPED_MSB 30 +#define RX_MSDU_END_VLAN_STAG_STRIPPED_MASK 0x0000000040000000 + + + + +#define RX_MSDU_END_FRAGMENT_FLAG_OFFSET 0x0000000000000030 +#define RX_MSDU_END_FRAGMENT_FLAG_LSB 31 +#define RX_MSDU_END_FRAGMENT_FLAG_MSB 31 +#define RX_MSDU_END_FRAGMENT_FLAG_MASK 0x0000000080000000 + + + + +#define RX_MSDU_END_FSE_METADATA_OFFSET 0x0000000000000030 +#define RX_MSDU_END_FSE_METADATA_LSB 32 +#define RX_MSDU_END_FSE_METADATA_MSB 63 +#define RX_MSDU_END_FSE_METADATA_MASK 0xffffffff00000000 + + + + +#define RX_MSDU_END_CCE_METADATA_OFFSET 0x0000000000000038 +#define RX_MSDU_END_CCE_METADATA_LSB 0 +#define RX_MSDU_END_CCE_METADATA_MSB 15 +#define RX_MSDU_END_CCE_METADATA_MASK 0x000000000000ffff + + + + +#define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET 0x0000000000000038 +#define RX_MSDU_END_TCP_UDP_CHKSUM_LSB 16 +#define RX_MSDU_END_TCP_UDP_CHKSUM_MSB 31 +#define RX_MSDU_END_TCP_UDP_CHKSUM_MASK 0x00000000ffff0000 + + + + +#define RX_MSDU_END_AGGREGATION_COUNT_OFFSET 0x0000000000000038 +#define RX_MSDU_END_AGGREGATION_COUNT_LSB 32 +#define RX_MSDU_END_AGGREGATION_COUNT_MSB 39 +#define RX_MSDU_END_AGGREGATION_COUNT_MASK 0x000000ff00000000 + + + + +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000000000000038 +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB 40 +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB 40 +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK 0x0000010000000000 + + + + +#define RX_MSDU_END_FISA_TIMEOUT_OFFSET 0x0000000000000038 +#define RX_MSDU_END_FISA_TIMEOUT_LSB 41 +#define RX_MSDU_END_FISA_TIMEOUT_MSB 41 +#define RX_MSDU_END_FISA_TIMEOUT_MASK 0x0000020000000000 + + + + +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000038 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB 42 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB 42 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK 0x0000040000000000 + + + + +#define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000038 +#define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB 43 +#define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB 43 +#define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK 0x0000080000000000 + + + + +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000038 +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB 44 +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB 44 +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK 0x0000100000000000 + + + + +#define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET 0x0000000000000038 +#define RX_MSDU_END_FLOW_IDX_INVALID_LSB 45 +#define RX_MSDU_END_FLOW_IDX_INVALID_MSB 45 +#define RX_MSDU_END_FLOW_IDX_INVALID_MASK 0x0000200000000000 + + + + +#define RX_MSDU_END_CCE_MATCH_OFFSET 0x0000000000000038 +#define RX_MSDU_END_CCE_MATCH_LSB 46 +#define RX_MSDU_END_CCE_MATCH_MSB 46 +#define RX_MSDU_END_CCE_MATCH_MASK 0x0000400000000000 + + + + +#define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000038 +#define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB 47 +#define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB 47 +#define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK 0x0000800000000000 + + + + +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET 0x0000000000000038 +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB 48 +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB 63 +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK 0xffff000000000000 + + + + +#define RX_MSDU_END_KEY_ID_OCTET_OFFSET 0x0000000000000040 +#define RX_MSDU_END_KEY_ID_OCTET_LSB 0 +#define RX_MSDU_END_KEY_ID_OCTET_MSB 7 +#define RX_MSDU_END_KEY_ID_OCTET_MASK 0x00000000000000ff + + + + +#define RX_MSDU_END_RESERVED_16A_OFFSET 0x0000000000000040 +#define RX_MSDU_END_RESERVED_16A_LSB 8 +#define RX_MSDU_END_RESERVED_16A_MSB 31 +#define RX_MSDU_END_RESERVED_16A_MASK 0x00000000ffffff00 + + + + +#define RX_MSDU_END_RESERVED_17A_OFFSET 0x0000000000000040 +#define RX_MSDU_END_RESERVED_17A_LSB 32 +#define RX_MSDU_END_RESERVED_17A_MSB 37 +#define RX_MSDU_END_RESERVED_17A_MASK 0x0000003f00000000 + + + + +#define RX_MSDU_END_SERVICE_CODE_OFFSET 0x0000000000000040 +#define RX_MSDU_END_SERVICE_CODE_LSB 38 +#define RX_MSDU_END_SERVICE_CODE_MSB 46 +#define RX_MSDU_END_SERVICE_CODE_MASK 0x00007fc000000000 + + + + +#define RX_MSDU_END_PRIORITY_VALID_OFFSET 0x0000000000000040 +#define RX_MSDU_END_PRIORITY_VALID_LSB 47 +#define RX_MSDU_END_PRIORITY_VALID_MSB 47 +#define RX_MSDU_END_PRIORITY_VALID_MASK 0x0000800000000000 + + + + +#define RX_MSDU_END_INTRA_BSS_OFFSET 0x0000000000000040 +#define RX_MSDU_END_INTRA_BSS_LSB 48 +#define RX_MSDU_END_INTRA_BSS_MSB 48 +#define RX_MSDU_END_INTRA_BSS_MASK 0x0001000000000000 + + + + +#define RX_MSDU_END_DEST_CHIP_ID_OFFSET 0x0000000000000040 +#define RX_MSDU_END_DEST_CHIP_ID_LSB 49 +#define RX_MSDU_END_DEST_CHIP_ID_MSB 50 +#define RX_MSDU_END_DEST_CHIP_ID_MASK 0x0006000000000000 + + + + +#define RX_MSDU_END_MULTICAST_ECHO_OFFSET 0x0000000000000040 +#define RX_MSDU_END_MULTICAST_ECHO_LSB 51 +#define RX_MSDU_END_MULTICAST_ECHO_MSB 51 +#define RX_MSDU_END_MULTICAST_ECHO_MASK 0x0008000000000000 + + + + +#define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET 0x0000000000000040 +#define RX_MSDU_END_WDS_LEARNING_EVENT_LSB 52 +#define RX_MSDU_END_WDS_LEARNING_EVENT_MSB 52 +#define RX_MSDU_END_WDS_LEARNING_EVENT_MASK 0x0010000000000000 + + + + +#define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET 0x0000000000000040 +#define RX_MSDU_END_WDS_ROAMING_EVENT_LSB 53 +#define RX_MSDU_END_WDS_ROAMING_EVENT_MSB 53 +#define RX_MSDU_END_WDS_ROAMING_EVENT_MASK 0x0020000000000000 + + + + +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET 0x0000000000000040 +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB 54 +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB 54 +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK 0x0040000000000000 + + + + +#define RX_MSDU_END_RESERVED_17B_OFFSET 0x0000000000000040 +#define RX_MSDU_END_RESERVED_17B_LSB 55 +#define RX_MSDU_END_RESERVED_17B_MSB 63 +#define RX_MSDU_END_RESERVED_17B_MASK 0xff80000000000000 + + + + +#define RX_MSDU_END_MSDU_LENGTH_OFFSET 0x0000000000000048 +#define RX_MSDU_END_MSDU_LENGTH_LSB 0 +#define RX_MSDU_END_MSDU_LENGTH_MSB 13 +#define RX_MSDU_END_MSDU_LENGTH_MASK 0x0000000000003fff + + + + +#define RX_MSDU_END_STBC_OFFSET 0x0000000000000048 +#define RX_MSDU_END_STBC_LSB 14 +#define RX_MSDU_END_STBC_MSB 14 +#define RX_MSDU_END_STBC_MASK 0x0000000000004000 + + + + +#define RX_MSDU_END_IPSEC_ESP_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IPSEC_ESP_LSB 15 +#define RX_MSDU_END_IPSEC_ESP_MSB 15 +#define RX_MSDU_END_IPSEC_ESP_MASK 0x0000000000008000 + + + + +#define RX_MSDU_END_L3_OFFSET_OFFSET 0x0000000000000048 +#define RX_MSDU_END_L3_OFFSET_LSB 16 +#define RX_MSDU_END_L3_OFFSET_MSB 22 +#define RX_MSDU_END_L3_OFFSET_MASK 0x00000000007f0000 + + + + +#define RX_MSDU_END_IPSEC_AH_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IPSEC_AH_LSB 23 +#define RX_MSDU_END_IPSEC_AH_MSB 23 +#define RX_MSDU_END_IPSEC_AH_MASK 0x0000000000800000 + + + + +#define RX_MSDU_END_L4_OFFSET_OFFSET 0x0000000000000048 +#define RX_MSDU_END_L4_OFFSET_LSB 24 +#define RX_MSDU_END_L4_OFFSET_MSB 31 +#define RX_MSDU_END_L4_OFFSET_MASK 0x00000000ff000000 + + + + +#define RX_MSDU_END_MSDU_NUMBER_OFFSET 0x0000000000000048 +#define RX_MSDU_END_MSDU_NUMBER_LSB 32 +#define RX_MSDU_END_MSDU_NUMBER_MSB 39 +#define RX_MSDU_END_MSDU_NUMBER_MASK 0x000000ff00000000 + + + + +#define RX_MSDU_END_DECAP_FORMAT_OFFSET 0x0000000000000048 +#define RX_MSDU_END_DECAP_FORMAT_LSB 40 +#define RX_MSDU_END_DECAP_FORMAT_MSB 41 +#define RX_MSDU_END_DECAP_FORMAT_MASK 0x0000030000000000 + + + + +#define RX_MSDU_END_IPV4_PROTO_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IPV4_PROTO_LSB 42 +#define RX_MSDU_END_IPV4_PROTO_MSB 42 +#define RX_MSDU_END_IPV4_PROTO_MASK 0x0000040000000000 + + + + +#define RX_MSDU_END_IPV6_PROTO_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IPV6_PROTO_LSB 43 +#define RX_MSDU_END_IPV6_PROTO_MSB 43 +#define RX_MSDU_END_IPV6_PROTO_MASK 0x0000080000000000 + + + + +#define RX_MSDU_END_TCP_PROTO_OFFSET 0x0000000000000048 +#define RX_MSDU_END_TCP_PROTO_LSB 44 +#define RX_MSDU_END_TCP_PROTO_MSB 44 +#define RX_MSDU_END_TCP_PROTO_MASK 0x0000100000000000 + + + + +#define RX_MSDU_END_UDP_PROTO_OFFSET 0x0000000000000048 +#define RX_MSDU_END_UDP_PROTO_LSB 45 +#define RX_MSDU_END_UDP_PROTO_MSB 45 +#define RX_MSDU_END_UDP_PROTO_MASK 0x0000200000000000 + + + + +#define RX_MSDU_END_IP_FRAG_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IP_FRAG_LSB 46 +#define RX_MSDU_END_IP_FRAG_MSB 46 +#define RX_MSDU_END_IP_FRAG_MASK 0x0000400000000000 + + + + +#define RX_MSDU_END_TCP_ONLY_ACK_OFFSET 0x0000000000000048 +#define RX_MSDU_END_TCP_ONLY_ACK_LSB 47 +#define RX_MSDU_END_TCP_ONLY_ACK_MSB 47 +#define RX_MSDU_END_TCP_ONLY_ACK_MASK 0x0000800000000000 + + + + +#define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000048 +#define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB 48 +#define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB 48 +#define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK 0x0001000000000000 + + + + +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000048 +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB 49 +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB 50 +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK 0x0006000000000000 + + + + +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB 51 +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB 51 +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK 0x0008000000000000 + + + + +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB 52 +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB 52 +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK 0x0010000000000000 + + + + +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000048 +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB 53 +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB 53 +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK 0x0020000000000000 + + + + +#define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000048 +#define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB 54 +#define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB 54 +#define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK 0x0040000000000000 + + + + +#define RX_MSDU_END_LDPC_OFFSET 0x0000000000000048 +#define RX_MSDU_END_LDPC_LSB 55 +#define RX_MSDU_END_LDPC_MSB 55 +#define RX_MSDU_END_LDPC_MASK 0x0080000000000000 + + + + +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 56 +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 63 +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff00000000000000 + + + + +#define RX_MSDU_END_VLAN_CTAG_CI_OFFSET 0x0000000000000050 +#define RX_MSDU_END_VLAN_CTAG_CI_LSB 0 +#define RX_MSDU_END_VLAN_CTAG_CI_MSB 15 +#define RX_MSDU_END_VLAN_CTAG_CI_MASK 0x000000000000ffff + + + + +#define RX_MSDU_END_VLAN_STAG_CI_OFFSET 0x0000000000000050 +#define RX_MSDU_END_VLAN_STAG_CI_LSB 16 +#define RX_MSDU_END_VLAN_STAG_CI_MSB 31 +#define RX_MSDU_END_VLAN_STAG_CI_MASK 0x00000000ffff0000 + + + + +#define RX_MSDU_END_PEER_META_DATA_OFFSET 0x0000000000000050 +#define RX_MSDU_END_PEER_META_DATA_LSB 32 +#define RX_MSDU_END_PEER_META_DATA_MSB 63 +#define RX_MSDU_END_PEER_META_DATA_MASK 0xffffffff00000000 + + + + +#define RX_MSDU_END_USER_RSSI_OFFSET 0x0000000000000058 +#define RX_MSDU_END_USER_RSSI_LSB 0 +#define RX_MSDU_END_USER_RSSI_MSB 7 +#define RX_MSDU_END_USER_RSSI_MASK 0x00000000000000ff + + + + +#define RX_MSDU_END_PKT_TYPE_OFFSET 0x0000000000000058 +#define RX_MSDU_END_PKT_TYPE_LSB 8 +#define RX_MSDU_END_PKT_TYPE_MSB 11 +#define RX_MSDU_END_PKT_TYPE_MASK 0x0000000000000f00 + + + + +#define RX_MSDU_END_SGI_OFFSET 0x0000000000000058 +#define RX_MSDU_END_SGI_LSB 12 +#define RX_MSDU_END_SGI_MSB 13 +#define RX_MSDU_END_SGI_MASK 0x0000000000003000 + + + + +#define RX_MSDU_END_RATE_MCS_OFFSET 0x0000000000000058 +#define RX_MSDU_END_RATE_MCS_LSB 14 +#define RX_MSDU_END_RATE_MCS_MSB 17 +#define RX_MSDU_END_RATE_MCS_MASK 0x000000000003c000 + + + + +#define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000058 +#define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB 18 +#define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB 20 +#define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK 0x00000000001c0000 + + + + +#define RX_MSDU_END_RECEPTION_TYPE_OFFSET 0x0000000000000058 +#define RX_MSDU_END_RECEPTION_TYPE_LSB 21 +#define RX_MSDU_END_RECEPTION_TYPE_MSB 23 +#define RX_MSDU_END_RECEPTION_TYPE_MASK 0x0000000000e00000 + + + + +#define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET 0x0000000000000058 +#define RX_MSDU_END_MIMO_SS_BITMAP_LSB 24 +#define RX_MSDU_END_MIMO_SS_BITMAP_MSB 30 +#define RX_MSDU_END_MIMO_SS_BITMAP_MASK 0x000000007f000000 + + + + +#define RX_MSDU_END_MSDU_DONE_COPY_OFFSET 0x0000000000000058 +#define RX_MSDU_END_MSDU_DONE_COPY_LSB 31 +#define RX_MSDU_END_MSDU_DONE_COPY_MSB 31 +#define RX_MSDU_END_MSDU_DONE_COPY_MASK 0x0000000080000000 + + + + +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000058 +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB 32 +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB 63 +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK 0xffffffff00000000 + + + + +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000060 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB 0 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB 31 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK 0x00000000ffffffff + + + + +#define RX_MSDU_END_SW_PHY_META_DATA_OFFSET 0x0000000000000060 +#define RX_MSDU_END_SW_PHY_META_DATA_LSB 32 +#define RX_MSDU_END_SW_PHY_META_DATA_MSB 63 +#define RX_MSDU_END_SW_PHY_META_DATA_MASK 0xffffffff00000000 + + + + +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000068 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff + + + + +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000068 +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB 32 +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB 63 +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000 + + + + +#define RX_MSDU_END_RESERVED_28A_OFFSET 0x0000000000000070 +#define RX_MSDU_END_RESERVED_28A_LSB 0 +#define RX_MSDU_END_RESERVED_28A_MSB 15 +#define RX_MSDU_END_RESERVED_28A_MASK 0x000000000000ffff + + + + +#define RX_MSDU_END_SA_15_0_OFFSET 0x0000000000000070 +#define RX_MSDU_END_SA_15_0_LSB 16 +#define RX_MSDU_END_SA_15_0_MSB 31 +#define RX_MSDU_END_SA_15_0_MASK 0x00000000ffff0000 + + + + +#define RX_MSDU_END_SA_47_16_OFFSET 0x0000000000000070 +#define RX_MSDU_END_SA_47_16_LSB 32 +#define RX_MSDU_END_SA_47_16_MSB 63 +#define RX_MSDU_END_SA_47_16_MASK 0xffffffff00000000 + + + + +#define RX_MSDU_END_FIRST_MPDU_OFFSET 0x0000000000000078 +#define RX_MSDU_END_FIRST_MPDU_LSB 0 +#define RX_MSDU_END_FIRST_MPDU_MSB 0 +#define RX_MSDU_END_FIRST_MPDU_MASK 0x0000000000000001 + + + + +#define RX_MSDU_END_RESERVED_30A_OFFSET 0x0000000000000078 +#define RX_MSDU_END_RESERVED_30A_LSB 1 +#define RX_MSDU_END_RESERVED_30A_MSB 1 +#define RX_MSDU_END_RESERVED_30A_MASK 0x0000000000000002 + + + + +#define RX_MSDU_END_MCAST_BCAST_OFFSET 0x0000000000000078 +#define RX_MSDU_END_MCAST_BCAST_LSB 2 +#define RX_MSDU_END_MCAST_BCAST_MSB 2 +#define RX_MSDU_END_MCAST_BCAST_MASK 0x0000000000000004 + + + + +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000078 +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB 3 +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB 3 +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK 0x0000000000000008 + + + + +#define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000078 +#define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB 4 +#define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB 4 +#define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK 0x0000000000000010 + + + + +#define RX_MSDU_END_POWER_MGMT_OFFSET 0x0000000000000078 +#define RX_MSDU_END_POWER_MGMT_LSB 5 +#define RX_MSDU_END_POWER_MGMT_MSB 5 +#define RX_MSDU_END_POWER_MGMT_MASK 0x0000000000000020 + + + + +#define RX_MSDU_END_NON_QOS_OFFSET 0x0000000000000078 +#define RX_MSDU_END_NON_QOS_LSB 6 +#define RX_MSDU_END_NON_QOS_MSB 6 +#define RX_MSDU_END_NON_QOS_MASK 0x0000000000000040 + + + + +#define RX_MSDU_END_NULL_DATA_OFFSET 0x0000000000000078 +#define RX_MSDU_END_NULL_DATA_LSB 7 +#define RX_MSDU_END_NULL_DATA_MSB 7 +#define RX_MSDU_END_NULL_DATA_MASK 0x0000000000000080 + + + + +#define RX_MSDU_END_MGMT_TYPE_OFFSET 0x0000000000000078 +#define RX_MSDU_END_MGMT_TYPE_LSB 8 +#define RX_MSDU_END_MGMT_TYPE_MSB 8 +#define RX_MSDU_END_MGMT_TYPE_MASK 0x0000000000000100 + + + + +#define RX_MSDU_END_CTRL_TYPE_OFFSET 0x0000000000000078 +#define RX_MSDU_END_CTRL_TYPE_LSB 9 +#define RX_MSDU_END_CTRL_TYPE_MSB 9 +#define RX_MSDU_END_CTRL_TYPE_MASK 0x0000000000000200 + + + + +#define RX_MSDU_END_MORE_DATA_OFFSET 0x0000000000000078 +#define RX_MSDU_END_MORE_DATA_LSB 10 +#define RX_MSDU_END_MORE_DATA_MSB 10 +#define RX_MSDU_END_MORE_DATA_MASK 0x0000000000000400 + + + + +#define RX_MSDU_END_EOSP_OFFSET 0x0000000000000078 +#define RX_MSDU_END_EOSP_LSB 11 +#define RX_MSDU_END_EOSP_MSB 11 +#define RX_MSDU_END_EOSP_MASK 0x0000000000000800 + + + + +#define RX_MSDU_END_A_MSDU_ERROR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_A_MSDU_ERROR_LSB 12 +#define RX_MSDU_END_A_MSDU_ERROR_MSB 12 +#define RX_MSDU_END_A_MSDU_ERROR_MASK 0x0000000000001000 + + + + +#define RX_MSDU_END_RESERVED_30B_OFFSET 0x0000000000000078 +#define RX_MSDU_END_RESERVED_30B_LSB 13 +#define RX_MSDU_END_RESERVED_30B_MSB 13 +#define RX_MSDU_END_RESERVED_30B_MASK 0x0000000000002000 + + + + +#define RX_MSDU_END_ORDER_OFFSET 0x0000000000000078 +#define RX_MSDU_END_ORDER_LSB 14 +#define RX_MSDU_END_ORDER_MSB 14 +#define RX_MSDU_END_ORDER_MASK 0x0000000000004000 + + + + +#define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_WIFI_PARSER_ERROR_LSB 15 +#define RX_MSDU_END_WIFI_PARSER_ERROR_MSB 15 +#define RX_MSDU_END_WIFI_PARSER_ERROR_MASK 0x0000000000008000 + + + + +#define RX_MSDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_OVERFLOW_ERR_LSB 16 +#define RX_MSDU_END_OVERFLOW_ERR_MSB 16 +#define RX_MSDU_END_OVERFLOW_ERR_MASK 0x0000000000010000 + + + + +#define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_MSDU_LENGTH_ERR_LSB 17 +#define RX_MSDU_END_MSDU_LENGTH_ERR_MSB 17 +#define RX_MSDU_END_MSDU_LENGTH_ERR_MASK 0x0000000000020000 + + + + +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000078 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB 18 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB 18 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK 0x0000000000040000 + + + + +#define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET 0x0000000000000078 +#define RX_MSDU_END_IP_CHKSUM_FAIL_LSB 19 +#define RX_MSDU_END_IP_CHKSUM_FAIL_MSB 19 +#define RX_MSDU_END_IP_CHKSUM_FAIL_MASK 0x0000000000080000 + + + + +#define RX_MSDU_END_SA_IDX_INVALID_OFFSET 0x0000000000000078 +#define RX_MSDU_END_SA_IDX_INVALID_LSB 20 +#define RX_MSDU_END_SA_IDX_INVALID_MSB 20 +#define RX_MSDU_END_SA_IDX_INVALID_MASK 0x0000000000100000 + + + + +#define RX_MSDU_END_DA_IDX_INVALID_OFFSET 0x0000000000000078 +#define RX_MSDU_END_DA_IDX_INVALID_LSB 21 +#define RX_MSDU_END_DA_IDX_INVALID_MSB 21 +#define RX_MSDU_END_DA_IDX_INVALID_MASK 0x0000000000200000 + + + + +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_OFFSET 0x0000000000000078 +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_LSB 22 +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MSB 22 +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MASK 0x0000000000400000 + + + + +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000078 +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB 23 +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB 23 +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000000000800000 + + + + +#define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET 0x0000000000000078 +#define RX_MSDU_END_ENCRYPT_REQUIRED_LSB 24 +#define RX_MSDU_END_ENCRYPT_REQUIRED_MSB 24 +#define RX_MSDU_END_ENCRYPT_REQUIRED_MASK 0x0000000001000000 + + + + +#define RX_MSDU_END_DIRECTED_OFFSET 0x0000000000000078 +#define RX_MSDU_END_DIRECTED_LSB 25 +#define RX_MSDU_END_DIRECTED_MSB 25 +#define RX_MSDU_END_DIRECTED_MASK 0x0000000002000000 + + + + +#define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET 0x0000000000000078 +#define RX_MSDU_END_BUFFER_FRAGMENT_LSB 26 +#define RX_MSDU_END_BUFFER_FRAGMENT_MSB 26 +#define RX_MSDU_END_BUFFER_FRAGMENT_MASK 0x0000000004000000 + + + + +#define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_MPDU_LENGTH_ERR_LSB 27 +#define RX_MSDU_END_MPDU_LENGTH_ERR_MSB 27 +#define RX_MSDU_END_MPDU_LENGTH_ERR_MASK 0x0000000008000000 + + + + +#define RX_MSDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_TKIP_MIC_ERR_LSB 28 +#define RX_MSDU_END_TKIP_MIC_ERR_MSB 28 +#define RX_MSDU_END_TKIP_MIC_ERR_MASK 0x0000000010000000 + + + + +#define RX_MSDU_END_DECRYPT_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_DECRYPT_ERR_LSB 29 +#define RX_MSDU_END_DECRYPT_ERR_MSB 29 +#define RX_MSDU_END_DECRYPT_ERR_MASK 0x0000000020000000 + + + + +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB 30 +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB 30 +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0000000040000000 + + + + +#define RX_MSDU_END_FCS_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_FCS_ERR_LSB 31 +#define RX_MSDU_END_FCS_ERR_MSB 31 +#define RX_MSDU_END_FCS_ERR_MASK 0x0000000080000000 + + + + +#define RX_MSDU_END_RESERVED_31A_OFFSET 0x0000000000000078 +#define RX_MSDU_END_RESERVED_31A_LSB 32 +#define RX_MSDU_END_RESERVED_31A_MSB 41 +#define RX_MSDU_END_RESERVED_31A_MASK 0x000003ff00000000 + + + + +#define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000078 +#define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB 42 +#define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB 44 +#define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK 0x00001c0000000000 + + + + +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000078 +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB 45 +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB 45 +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x0000200000000000 + + + + +#define RX_MSDU_END_RESERVED_31B_OFFSET 0x0000000000000078 +#define RX_MSDU_END_RESERVED_31B_LSB 46 +#define RX_MSDU_END_RESERVED_31B_MSB 62 +#define RX_MSDU_END_RESERVED_31B_MASK 0x7fffc00000000000 + + + + +#define RX_MSDU_END_MSDU_DONE_OFFSET 0x0000000000000078 +#define RX_MSDU_END_MSDU_DONE_LSB 63 +#define RX_MSDU_END_MSDU_DONE_MSB 63 +#define RX_MSDU_END_MSDU_DONE_MASK 0x8000000000000000 + + + +#endif diff --git a/hw/qcn9224/rx_msdu_ext_desc_info.h b/hw/qcn9224/rx_msdu_ext_desc_info.h new file mode 100644 index 000000000000..ba7967da94ba --- /dev/null +++ b/hw/qcn9224/rx_msdu_ext_desc_info.h @@ -0,0 +1,102 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RX_MSDU_EXT_DESC_INFO_H_ +#define _RX_MSDU_EXT_DESC_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MSDU_EXT_DESC_INFO 1 + + +struct rx_msdu_ext_desc_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_destination_indication : 5, + service_code : 9, + priority_valid : 1, + data_offset : 12, + src_link_id : 3, + reserved_0a : 2; +#else + uint32_t reserved_0a : 2, + src_link_id : 3, + data_offset : 12, + priority_valid : 1, + service_code : 9, + reo_destination_indication : 5; +#endif +}; + + + + +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f + + + + +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_LSB 5 +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MSB 13 +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MASK 0x00003fe0 + + + + +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_LSB 14 +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MSB 14 +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MASK 0x00004000 + + + + +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_LSB 15 +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MSB 26 +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MASK 0x07ff8000 + + + + +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_LSB 27 +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MSB 29 +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MASK 0x38000000 + + + + +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_LSB 30 +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MSB 31 +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MASK 0xc0000000 + + + +#endif diff --git a/hw/qcn9224/rx_msdu_link.h b/hw/qcn9224/rx_msdu_link.h new file mode 100644 index 000000000000..f06cbbd30fe5 --- /dev/null +++ b/hw/qcn9224/rx_msdu_link.h @@ -0,0 +1,1561 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RX_MSDU_LINK_H_ +#define _RX_MSDU_LINK_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" +#include "buffer_addr_info.h" +#include "rx_msdu_details.h" +#define NUM_OF_DWORDS_RX_MSDU_LINK 32 + + +struct rx_msdu_link { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_descriptor_header descriptor_header; + struct buffer_addr_info next_msdu_link_desc_addr_info; + uint32_t receive_queue_number : 16, + first_rx_msdu_link_struct : 1, + reserved_3a : 15; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + struct rx_msdu_details msdu_0; + struct rx_msdu_details msdu_1; + struct rx_msdu_details msdu_2; + struct rx_msdu_details msdu_3; + struct rx_msdu_details msdu_4; + struct rx_msdu_details msdu_5; +#else + struct uniform_descriptor_header descriptor_header; + struct buffer_addr_info next_msdu_link_desc_addr_info; + uint32_t reserved_3a : 15, + first_rx_msdu_link_struct : 1, + receive_queue_number : 16; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + struct rx_msdu_details msdu_0; + struct rx_msdu_details msdu_1; + struct rx_msdu_details msdu_2; + struct rx_msdu_details msdu_3; + struct rx_msdu_details msdu_4; + struct rx_msdu_details msdu_5; +#endif +}; + + + + + + + +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + + + + +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + + + + +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 + + + + + + + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_LSB 0 +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_MSB 15 +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + + + + +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_OFFSET 0x0000000c +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_LSB 16 +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_MSB 16 +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_MASK 0x00010000 + + + + +#define RX_MSDU_LINK_RESERVED_3A_OFFSET 0x0000000c +#define RX_MSDU_LINK_RESERVED_3A_LSB 17 +#define RX_MSDU_LINK_RESERVED_3A_MSB 31 +#define RX_MSDU_LINK_RESERVED_3A_MASK 0xfffe0000 + + + + +#define RX_MSDU_LINK_PN_31_0_OFFSET 0x00000010 +#define RX_MSDU_LINK_PN_31_0_LSB 0 +#define RX_MSDU_LINK_PN_31_0_MSB 31 +#define RX_MSDU_LINK_PN_31_0_MASK 0xffffffff + + + + +#define RX_MSDU_LINK_PN_63_32_OFFSET 0x00000014 +#define RX_MSDU_LINK_PN_63_32_LSB 0 +#define RX_MSDU_LINK_PN_63_32_MSB 31 +#define RX_MSDU_LINK_PN_63_32_MASK 0xffffffff + + + + +#define RX_MSDU_LINK_PN_95_64_OFFSET 0x00000018 +#define RX_MSDU_LINK_PN_95_64_LSB 0 +#define RX_MSDU_LINK_PN_95_64_MSB 31 +#define RX_MSDU_LINK_PN_95_64_MASK 0xffffffff + + + + +#define RX_MSDU_LINK_PN_127_96_OFFSET 0x0000001c +#define RX_MSDU_LINK_PN_127_96_LSB 0 +#define RX_MSDU_LINK_PN_127_96_MSB 31 +#define RX_MSDU_LINK_PN_127_96_MASK 0xffffffff + + + + + + + + + + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + + + + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + + + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + + + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + + + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + + + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + + + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + + + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + + + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + + + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + + + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + + + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + + + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + + + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + + + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + + + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + + + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + + + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000 + + + + + + + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + + + + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + + + + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + + + + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + + + + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + + + + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + + + + + + + + + + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + + + + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + + + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + + + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + + + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + + + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + + + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + + + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + + + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + + + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + + + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + + + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + + + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + + + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + + + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + + + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + + + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + + + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000 + + + + + + + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + + + + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + + + + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + + + + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + + + + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + + + + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + + + + + + + + + + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + + + + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + + + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + + + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + + + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + + + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + + + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + + + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + + + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + + + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + + + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + + + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + + + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + + + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + + + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + + + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + + + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + + + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000 + + + + + + + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + + + + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + + + + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + + + + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + + + + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + + + + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + + + + + + + + + + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + + + + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + + + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + + + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + + + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + + + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + + + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + + + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + + + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + + + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + + + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + + + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + + + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + + + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + + + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + + + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + + + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + + + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000 + + + + + + + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + + + + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + + + + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + + + + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + + + + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + + + + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + + + + + + + + + + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + + + + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + + + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + + + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + + + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + + + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + + + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + + + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + + + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + + + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + + + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + + + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + + + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + + + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + + + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + + + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + + + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + + + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000 + + + + + + + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + + + + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + + + + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + + + + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + + + + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + + + + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + + + + + + + + + + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + + + + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + + + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + + + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + + + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + + + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + + + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + + + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + + + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + + + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + + + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + + + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + + + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + + + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + + + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + + + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + + + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + + + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000 + + + + + + + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + + + + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + + + + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + + + + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + + + + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + + + + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + + + +#endif diff --git a/hw/qcn9224/rx_msdu_start.h b/hw/qcn9224/rx_msdu_start.h new file mode 100644 index 000000000000..216f3c35c078 --- /dev/null +++ b/hw/qcn9224/rx_msdu_start.h @@ -0,0 +1,444 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RX_MSDU_START_H_ +#define _RX_MSDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MSDU_START 10 + +#define NUM_OF_QWORDS_RX_MSDU_START 5 + + +struct rx_msdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t msdu_length : 14, + stbc : 1, + ipsec_esp : 1, + l3_offset : 7, + ipsec_ah : 1, + l4_offset : 8; + uint32_t msdu_number : 8, + decap_format : 2, + ipv4_proto : 1, + ipv6_proto : 1, + tcp_proto : 1, + udp_proto : 1, + ip_frag : 1, + tcp_only_ack : 1, + da_is_bcast_mcast : 1, + toeplitz_hash_sel : 2, + ip_fixed_header_valid : 1, + ip_extn_header_valid : 1, + tcp_udp_header_valid : 1, + mesh_control_present : 1, + ldpc : 1, + ip4_protocol_ip6_next_header : 8; + uint32_t toeplitz_hash_2_or_4 : 32; + uint32_t flow_id_toeplitz : 32; + uint32_t user_rssi : 8, + pkt_type : 4, + sgi : 2, + rate_mcs : 4, + receive_bandwidth : 3, + reception_type : 3, + mimo_ss_bitmap : 8; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t sw_phy_meta_data : 32; + uint32_t vlan_ctag_ci : 16, + vlan_stag_ci : 16; +#else + uint32_t phy_ppdu_id : 16, + reserved_0 : 7, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t l4_offset : 8, + ipsec_ah : 1, + l3_offset : 7, + ipsec_esp : 1, + stbc : 1, + msdu_length : 14; + uint32_t ip4_protocol_ip6_next_header : 8, + ldpc : 1, + mesh_control_present : 1, + tcp_udp_header_valid : 1, + ip_extn_header_valid : 1, + ip_fixed_header_valid : 1, + toeplitz_hash_sel : 2, + da_is_bcast_mcast : 1, + tcp_only_ack : 1, + ip_frag : 1, + udp_proto : 1, + tcp_proto : 1, + ipv6_proto : 1, + ipv4_proto : 1, + decap_format : 2, + msdu_number : 8; + uint32_t toeplitz_hash_2_or_4 : 32; + uint32_t flow_id_toeplitz : 32; + uint32_t mimo_ss_bitmap : 8, + reception_type : 3, + receive_bandwidth : 3, + rate_mcs : 4, + sgi : 2, + pkt_type : 4, + user_rssi : 8; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t sw_phy_meta_data : 32; + uint32_t vlan_stag_ci : 16, + vlan_ctag_ci : 16; +#endif +}; + + + + +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 + + + + +#define RX_MSDU_START_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 +#define RX_MSDU_START_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MSDU_START_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MSDU_START_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc + + + + +#define RX_MSDU_START_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_MSDU_START_RESERVED_0_LSB 9 +#define RX_MSDU_START_RESERVED_0_MSB 15 +#define RX_MSDU_START_RESERVED_0_MASK 0x000000000000fe00 + + + + +#define RX_MSDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_MSDU_START_PHY_PPDU_ID_LSB 16 +#define RX_MSDU_START_PHY_PPDU_ID_MSB 31 +#define RX_MSDU_START_PHY_PPDU_ID_MASK 0x00000000ffff0000 + + + + +#define RX_MSDU_START_MSDU_LENGTH_OFFSET 0x0000000000000000 +#define RX_MSDU_START_MSDU_LENGTH_LSB 32 +#define RX_MSDU_START_MSDU_LENGTH_MSB 45 +#define RX_MSDU_START_MSDU_LENGTH_MASK 0x00003fff00000000 + + + + +#define RX_MSDU_START_STBC_OFFSET 0x0000000000000000 +#define RX_MSDU_START_STBC_LSB 46 +#define RX_MSDU_START_STBC_MSB 46 +#define RX_MSDU_START_STBC_MASK 0x0000400000000000 + + + + +#define RX_MSDU_START_IPSEC_ESP_OFFSET 0x0000000000000000 +#define RX_MSDU_START_IPSEC_ESP_LSB 47 +#define RX_MSDU_START_IPSEC_ESP_MSB 47 +#define RX_MSDU_START_IPSEC_ESP_MASK 0x0000800000000000 + + + + +#define RX_MSDU_START_L3_OFFSET_OFFSET 0x0000000000000000 +#define RX_MSDU_START_L3_OFFSET_LSB 48 +#define RX_MSDU_START_L3_OFFSET_MSB 54 +#define RX_MSDU_START_L3_OFFSET_MASK 0x007f000000000000 + + + + +#define RX_MSDU_START_IPSEC_AH_OFFSET 0x0000000000000000 +#define RX_MSDU_START_IPSEC_AH_LSB 55 +#define RX_MSDU_START_IPSEC_AH_MSB 55 +#define RX_MSDU_START_IPSEC_AH_MASK 0x0080000000000000 + + + + +#define RX_MSDU_START_L4_OFFSET_OFFSET 0x0000000000000000 +#define RX_MSDU_START_L4_OFFSET_LSB 56 +#define RX_MSDU_START_L4_OFFSET_MSB 63 +#define RX_MSDU_START_L4_OFFSET_MASK 0xff00000000000000 + + + + +#define RX_MSDU_START_MSDU_NUMBER_OFFSET 0x0000000000000008 +#define RX_MSDU_START_MSDU_NUMBER_LSB 0 +#define RX_MSDU_START_MSDU_NUMBER_MSB 7 +#define RX_MSDU_START_MSDU_NUMBER_MASK 0x00000000000000ff + + + + +#define RX_MSDU_START_DECAP_FORMAT_OFFSET 0x0000000000000008 +#define RX_MSDU_START_DECAP_FORMAT_LSB 8 +#define RX_MSDU_START_DECAP_FORMAT_MSB 9 +#define RX_MSDU_START_DECAP_FORMAT_MASK 0x0000000000000300 + + + + +#define RX_MSDU_START_IPV4_PROTO_OFFSET 0x0000000000000008 +#define RX_MSDU_START_IPV4_PROTO_LSB 10 +#define RX_MSDU_START_IPV4_PROTO_MSB 10 +#define RX_MSDU_START_IPV4_PROTO_MASK 0x0000000000000400 + + + + +#define RX_MSDU_START_IPV6_PROTO_OFFSET 0x0000000000000008 +#define RX_MSDU_START_IPV6_PROTO_LSB 11 +#define RX_MSDU_START_IPV6_PROTO_MSB 11 +#define RX_MSDU_START_IPV6_PROTO_MASK 0x0000000000000800 + + + + +#define RX_MSDU_START_TCP_PROTO_OFFSET 0x0000000000000008 +#define RX_MSDU_START_TCP_PROTO_LSB 12 +#define RX_MSDU_START_TCP_PROTO_MSB 12 +#define RX_MSDU_START_TCP_PROTO_MASK 0x0000000000001000 + + + + +#define RX_MSDU_START_UDP_PROTO_OFFSET 0x0000000000000008 +#define RX_MSDU_START_UDP_PROTO_LSB 13 +#define RX_MSDU_START_UDP_PROTO_MSB 13 +#define RX_MSDU_START_UDP_PROTO_MASK 0x0000000000002000 + + + + +#define RX_MSDU_START_IP_FRAG_OFFSET 0x0000000000000008 +#define RX_MSDU_START_IP_FRAG_LSB 14 +#define RX_MSDU_START_IP_FRAG_MSB 14 +#define RX_MSDU_START_IP_FRAG_MASK 0x0000000000004000 + + + + +#define RX_MSDU_START_TCP_ONLY_ACK_OFFSET 0x0000000000000008 +#define RX_MSDU_START_TCP_ONLY_ACK_LSB 15 +#define RX_MSDU_START_TCP_ONLY_ACK_MSB 15 +#define RX_MSDU_START_TCP_ONLY_ACK_MASK 0x0000000000008000 + + + + +#define RX_MSDU_START_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000008 +#define RX_MSDU_START_DA_IS_BCAST_MCAST_LSB 16 +#define RX_MSDU_START_DA_IS_BCAST_MCAST_MSB 16 +#define RX_MSDU_START_DA_IS_BCAST_MCAST_MASK 0x0000000000010000 + + + + +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000008 +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_LSB 17 +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MSB 18 +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MASK 0x0000000000060000 + + + + +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000008 +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_LSB 19 +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MSB 19 +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MASK 0x0000000000080000 + + + + +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000008 +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_LSB 20 +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MSB 20 +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MASK 0x0000000000100000 + + + + +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000008 +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_LSB 21 +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MSB 21 +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MASK 0x0000000000200000 + + + + +#define RX_MSDU_START_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000008 +#define RX_MSDU_START_MESH_CONTROL_PRESENT_LSB 22 +#define RX_MSDU_START_MESH_CONTROL_PRESENT_MSB 22 +#define RX_MSDU_START_MESH_CONTROL_PRESENT_MASK 0x0000000000400000 + + + + +#define RX_MSDU_START_LDPC_OFFSET 0x0000000000000008 +#define RX_MSDU_START_LDPC_LSB 23 +#define RX_MSDU_START_LDPC_MSB 23 +#define RX_MSDU_START_LDPC_MASK 0x0000000000800000 + + + + +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000008 +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24 +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 31 +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0x00000000ff000000 + + + + +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000008 +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_LSB 32 +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MSB 63 +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000 + + + + +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000010 +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_LSB 0 +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MSB 31 +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MASK 0x00000000ffffffff + + + + +#define RX_MSDU_START_USER_RSSI_OFFSET 0x0000000000000010 +#define RX_MSDU_START_USER_RSSI_LSB 32 +#define RX_MSDU_START_USER_RSSI_MSB 39 +#define RX_MSDU_START_USER_RSSI_MASK 0x000000ff00000000 + + + + +#define RX_MSDU_START_PKT_TYPE_OFFSET 0x0000000000000010 +#define RX_MSDU_START_PKT_TYPE_LSB 40 +#define RX_MSDU_START_PKT_TYPE_MSB 43 +#define RX_MSDU_START_PKT_TYPE_MASK 0x00000f0000000000 + + + + +#define RX_MSDU_START_SGI_OFFSET 0x0000000000000010 +#define RX_MSDU_START_SGI_LSB 44 +#define RX_MSDU_START_SGI_MSB 45 +#define RX_MSDU_START_SGI_MASK 0x0000300000000000 + + + + +#define RX_MSDU_START_RATE_MCS_OFFSET 0x0000000000000010 +#define RX_MSDU_START_RATE_MCS_LSB 46 +#define RX_MSDU_START_RATE_MCS_MSB 49 +#define RX_MSDU_START_RATE_MCS_MASK 0x0003c00000000000 + + + + +#define RX_MSDU_START_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000010 +#define RX_MSDU_START_RECEIVE_BANDWIDTH_LSB 50 +#define RX_MSDU_START_RECEIVE_BANDWIDTH_MSB 52 +#define RX_MSDU_START_RECEIVE_BANDWIDTH_MASK 0x001c000000000000 + + + + +#define RX_MSDU_START_RECEPTION_TYPE_OFFSET 0x0000000000000010 +#define RX_MSDU_START_RECEPTION_TYPE_LSB 53 +#define RX_MSDU_START_RECEPTION_TYPE_MSB 55 +#define RX_MSDU_START_RECEPTION_TYPE_MASK 0x00e0000000000000 + + + + +#define RX_MSDU_START_MIMO_SS_BITMAP_OFFSET 0x0000000000000010 +#define RX_MSDU_START_MIMO_SS_BITMAP_LSB 56 +#define RX_MSDU_START_MIMO_SS_BITMAP_MSB 63 +#define RX_MSDU_START_MIMO_SS_BITMAP_MASK 0xff00000000000000 + + + + +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000018 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff + + + + +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000018 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 + + + + +#define RX_MSDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000020 +#define RX_MSDU_START_SW_PHY_META_DATA_LSB 0 +#define RX_MSDU_START_SW_PHY_META_DATA_MSB 31 +#define RX_MSDU_START_SW_PHY_META_DATA_MASK 0x00000000ffffffff + + + + +#define RX_MSDU_START_VLAN_CTAG_CI_OFFSET 0x0000000000000020 +#define RX_MSDU_START_VLAN_CTAG_CI_LSB 32 +#define RX_MSDU_START_VLAN_CTAG_CI_MSB 47 +#define RX_MSDU_START_VLAN_CTAG_CI_MASK 0x0000ffff00000000 + + + + +#define RX_MSDU_START_VLAN_STAG_CI_OFFSET 0x0000000000000020 +#define RX_MSDU_START_VLAN_STAG_CI_LSB 48 +#define RX_MSDU_START_VLAN_STAG_CI_MSB 63 +#define RX_MSDU_START_VLAN_STAG_CI_MASK 0xffff000000000000 + + + +#endif diff --git a/hw/qcn9224/rx_ppdu_end_user_stats.h b/hw/qcn9224/rx_ppdu_end_user_stats.h new file mode 100644 index 000000000000..d6425b36c475 --- /dev/null +++ b/hw/qcn9224/rx_ppdu_end_user_stats.h @@ -0,0 +1,858 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RX_PPDU_END_USER_STATS_H_ +#define _RX_PPDU_END_USER_STATS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_rxpcu_classification_overview.h" +#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 24 + +#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS 12 + + +struct rx_ppdu_end_user_stats { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t sta_full_aid : 13, + mcs : 4, + nss : 3, + expected_response_ack_or_ba : 1, + reserved_1a : 11; + uint32_t sw_peer_id : 16, + mpdu_cnt_fcs_err : 11, + sw2rxdma0_buf_source_used : 1, + fw2rxdma_pmac0_buf_source_used : 1, + sw2rxdma1_buf_source_used : 1, + sw2rxdma_exception_buf_source_used : 1, + fw2rxdma_pmac1_buf_source_used : 1; + uint32_t mpdu_cnt_fcs_ok : 11, + frame_control_info_valid : 1, + qos_control_info_valid : 1, + ht_control_info_valid : 1, + data_sequence_control_info_valid : 1, + ht_control_info_null_valid : 1, + rxdma2fw_pmac1_ring_used : 1, + rxdma2reo_ring_used : 1, + rxdma2fw_pmac0_ring_used : 1, + rxdma2sw_ring_used : 1, + rxdma_release_ring_used : 1, + ht_control_field_pkt_type : 4, + rxdma2reo_remote0_ring_used : 1, + rxdma2reo_remote1_ring_used : 1, + reserved_3b : 5; + uint32_t ast_index : 16, + frame_control_field : 16; + uint32_t first_data_seq_ctrl : 16, + qos_control_field : 16; + uint32_t ht_control_field : 32; + uint32_t fcs_ok_bitmap_31_0 : 32; + uint32_t fcs_ok_bitmap_63_32 : 32; + uint32_t udp_msdu_count : 16, + tcp_msdu_count : 16; + uint32_t other_msdu_count : 16, + tcp_ack_msdu_count : 16; + uint32_t sw_response_reference_ptr : 32; + uint32_t received_qos_data_tid_bitmap : 16, + received_qos_data_tid_eosp_bitmap : 16; + uint32_t qosctrl_15_8_tid0 : 8, + qosctrl_15_8_tid1 : 8, + qosctrl_15_8_tid2 : 8, + qosctrl_15_8_tid3 : 8; + uint32_t qosctrl_15_8_tid4 : 8, + qosctrl_15_8_tid5 : 8, + qosctrl_15_8_tid6 : 8, + qosctrl_15_8_tid7 : 8; + uint32_t qosctrl_15_8_tid8 : 8, + qosctrl_15_8_tid9 : 8, + qosctrl_15_8_tid10 : 8, + qosctrl_15_8_tid11 : 8; + uint32_t qosctrl_15_8_tid12 : 8, + qosctrl_15_8_tid13 : 8, + qosctrl_15_8_tid14 : 8, + qosctrl_15_8_tid15 : 8; + uint32_t mpdu_ok_byte_count : 25, + ampdu_delim_ok_count_6_0 : 7; + uint32_t ampdu_delim_err_count : 25, + ampdu_delim_ok_count_13_7 : 7; + uint32_t mpdu_err_byte_count : 25, + ampdu_delim_ok_count_20_14 : 7; + uint32_t non_consecutive_delimiter_err : 16, + retried_msdu_count : 16; + uint32_t ht_control_null_field : 32; + uint32_t sw_response_reference_ptr_ext : 32; + uint32_t corrupted_due_to_fifo_delay : 1, + frame_control_info_null_valid : 1, + frame_control_field_null : 16, + retried_mpdu_count : 11, + reserved_23a : 3; +#else + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t reserved_1a : 11, + expected_response_ack_or_ba : 1, + nss : 3, + mcs : 4, + sta_full_aid : 13; + uint32_t fw2rxdma_pmac1_buf_source_used : 1, + sw2rxdma_exception_buf_source_used : 1, + sw2rxdma1_buf_source_used : 1, + fw2rxdma_pmac0_buf_source_used : 1, + sw2rxdma0_buf_source_used : 1, + mpdu_cnt_fcs_err : 11, + sw_peer_id : 16; + uint32_t reserved_3b : 5, + rxdma2reo_remote1_ring_used : 1, + rxdma2reo_remote0_ring_used : 1, + ht_control_field_pkt_type : 4, + rxdma_release_ring_used : 1, + rxdma2sw_ring_used : 1, + rxdma2fw_pmac0_ring_used : 1, + rxdma2reo_ring_used : 1, + rxdma2fw_pmac1_ring_used : 1, + ht_control_info_null_valid : 1, + data_sequence_control_info_valid : 1, + ht_control_info_valid : 1, + qos_control_info_valid : 1, + frame_control_info_valid : 1, + mpdu_cnt_fcs_ok : 11; + uint32_t frame_control_field : 16, + ast_index : 16; + uint32_t qos_control_field : 16, + first_data_seq_ctrl : 16; + uint32_t ht_control_field : 32; + uint32_t fcs_ok_bitmap_31_0 : 32; + uint32_t fcs_ok_bitmap_63_32 : 32; + uint32_t tcp_msdu_count : 16, + udp_msdu_count : 16; + uint32_t tcp_ack_msdu_count : 16, + other_msdu_count : 16; + uint32_t sw_response_reference_ptr : 32; + uint32_t received_qos_data_tid_eosp_bitmap : 16, + received_qos_data_tid_bitmap : 16; + uint32_t qosctrl_15_8_tid3 : 8, + qosctrl_15_8_tid2 : 8, + qosctrl_15_8_tid1 : 8, + qosctrl_15_8_tid0 : 8; + uint32_t qosctrl_15_8_tid7 : 8, + qosctrl_15_8_tid6 : 8, + qosctrl_15_8_tid5 : 8, + qosctrl_15_8_tid4 : 8; + uint32_t qosctrl_15_8_tid11 : 8, + qosctrl_15_8_tid10 : 8, + qosctrl_15_8_tid9 : 8, + qosctrl_15_8_tid8 : 8; + uint32_t qosctrl_15_8_tid15 : 8, + qosctrl_15_8_tid14 : 8, + qosctrl_15_8_tid13 : 8, + qosctrl_15_8_tid12 : 8; + uint32_t ampdu_delim_ok_count_6_0 : 7, + mpdu_ok_byte_count : 25; + uint32_t ampdu_delim_ok_count_13_7 : 7, + ampdu_delim_err_count : 25; + uint32_t ampdu_delim_ok_count_20_14 : 7, + mpdu_err_byte_count : 25; + uint32_t retried_msdu_count : 16, + non_consecutive_delimiter_err : 16; + uint32_t ht_control_null_field : 32; + uint32_t sw_response_reference_ptr_ext : 32; + uint32_t reserved_23a : 3, + retried_mpdu_count : 11, + frame_control_field_null : 16, + frame_control_info_null_valid : 1, + corrupted_due_to_fifo_delay : 1; +#endif +}; + + + + + + + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 + + + + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 + + + + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 + + + + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 + + + + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 + + + + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 + + + + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 + + + + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080 + + + + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100 + + + + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000fe00 + + + + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 + + + + +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_LSB 32 +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MSB 44 +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MASK 0x00001fff00000000 + + + + +#define RX_PPDU_END_USER_STATS_MCS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_MCS_LSB 45 +#define RX_PPDU_END_USER_STATS_MCS_MSB 48 +#define RX_PPDU_END_USER_STATS_MCS_MASK 0x0001e00000000000 + + + + +#define RX_PPDU_END_USER_STATS_NSS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_NSS_LSB 49 +#define RX_PPDU_END_USER_STATS_NSS_MSB 51 +#define RX_PPDU_END_USER_STATS_NSS_MASK 0x000e000000000000 + + + + +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_LSB 52 +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MSB 52 +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MASK 0x0010000000000000 + + + + +#define RX_PPDU_END_USER_STATS_RESERVED_1A_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RESERVED_1A_LSB 53 +#define RX_PPDU_END_USER_STATS_RESERVED_1A_MSB 63 +#define RX_PPDU_END_USER_STATS_RESERVED_1A_MASK 0xffe0000000000000 + + + + +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_LSB 0 +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MSB 15 +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MASK 0x000000000000ffff + + + + +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_LSB 16 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MSB 26 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MASK 0x0000000007ff0000 + + + + +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_LSB 27 +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MSB 27 +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MASK 0x0000000008000000 + + + + +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_LSB 28 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MSB 28 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MASK 0x0000000010000000 + + + + +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_LSB 29 +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MSB 29 +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MASK 0x0000000020000000 + + + + +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_LSB 30 +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MSB 30 +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MASK 0x0000000040000000 + + + + +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_LSB 31 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MSB 31 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MASK 0x0000000080000000 + + + + +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_LSB 32 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MSB 42 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MASK 0x000007ff00000000 + + + + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_LSB 43 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MSB 43 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MASK 0x0000080000000000 + + + + +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_LSB 44 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MSB 44 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MASK 0x0000100000000000 + + + + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_LSB 45 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MSB 45 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MASK 0x0000200000000000 + + + + +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 46 +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MSB 46 +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x0000400000000000 + + + + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_LSB 47 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MSB 47 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MASK 0x0000800000000000 + + + + +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_LSB 48 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MSB 48 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MASK 0x0001000000000000 + + + + +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_LSB 49 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MSB 49 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MASK 0x0002000000000000 + + + + +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_LSB 50 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MSB 50 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MASK 0x0004000000000000 + + + + +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_LSB 51 +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MSB 51 +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MASK 0x0008000000000000 + + + + +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_LSB 52 +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MSB 52 +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MASK 0x0010000000000000 + + + + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_LSB 53 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MSB 56 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x01e0000000000000 + + + + +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_LSB 57 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MSB 57 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MASK 0x0200000000000000 + + + + +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_LSB 58 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MSB 58 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MASK 0x0400000000000000 + + + + +#define RX_PPDU_END_USER_STATS_RESERVED_3B_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RESERVED_3B_LSB 59 +#define RX_PPDU_END_USER_STATS_RESERVED_3B_MSB 63 +#define RX_PPDU_END_USER_STATS_RESERVED_3B_MASK 0xf800000000000000 + + + + +#define RX_PPDU_END_USER_STATS_AST_INDEX_OFFSET 0x0000000000000010 +#define RX_PPDU_END_USER_STATS_AST_INDEX_LSB 0 +#define RX_PPDU_END_USER_STATS_AST_INDEX_MSB 15 +#define RX_PPDU_END_USER_STATS_AST_INDEX_MASK 0x000000000000ffff + + + + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000010 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_LSB 16 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MSB 31 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MASK 0x00000000ffff0000 + + + + +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_OFFSET 0x0000000000000010 +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_LSB 32 +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MSB 47 +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff00000000 + + + + +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_OFFSET 0x0000000000000010 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_LSB 48 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MSB 63 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MASK 0xffff000000000000 + + + + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_OFFSET 0x0000000000000018 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_LSB 0 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MSB 31 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MASK 0x00000000ffffffff + + + + +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_OFFSET 0x0000000000000018 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_LSB 32 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MSB 63 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MASK 0xffffffff00000000 + + + + +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_OFFSET 0x0000000000000020 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_LSB 0 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MSB 31 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MASK 0x00000000ffffffff + + + + +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_OFFSET 0x0000000000000020 +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_LSB 32 +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MSB 47 +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MASK 0x0000ffff00000000 + + + + +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_OFFSET 0x0000000000000020 +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_LSB 48 +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MSB 63 +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MASK 0xffff000000000000 + + + + +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_OFFSET 0x0000000000000028 +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MSB 15 +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MASK 0x000000000000ffff + + + + +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_OFFSET 0x0000000000000028 +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MASK 0x00000000ffff0000 + + + + +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000000000000028 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_LSB 32 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MSB 63 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff00000000 + + + + +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x0000000000000030 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MSB 15 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x000000000000ffff + + + + +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x0000000000000030 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MSB 31 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0x00000000ffff0000 + + + + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_OFFSET 0x0000000000000030 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_LSB 32 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MSB 39 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MASK 0x000000ff00000000 + + + + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_OFFSET 0x0000000000000030 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_LSB 40 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MSB 47 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MASK 0x0000ff0000000000 + + + + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_OFFSET 0x0000000000000030 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_LSB 48 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MSB 55 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MASK 0x00ff000000000000 + + + + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_OFFSET 0x0000000000000030 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_LSB 56 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MSB 63 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MASK 0xff00000000000000 + + + + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_LSB 0 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MSB 7 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MASK 0x00000000000000ff + + + + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_LSB 8 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MSB 15 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MASK 0x000000000000ff00 + + + + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_LSB 16 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MSB 23 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MASK 0x0000000000ff0000 + + + + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_LSB 24 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MSB 31 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MASK 0x00000000ff000000 + + + + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_LSB 32 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MSB 39 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MASK 0x000000ff00000000 + + + + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_LSB 40 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MSB 47 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MASK 0x0000ff0000000000 + + + + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_LSB 48 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MSB 55 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MASK 0x00ff000000000000 + + + + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_LSB 56 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MSB 63 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MASK 0xff00000000000000 + + + + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_OFFSET 0x0000000000000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_LSB 0 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MSB 7 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MASK 0x00000000000000ff + + + + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_OFFSET 0x0000000000000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_LSB 8 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MSB 15 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MASK 0x000000000000ff00 + + + + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_OFFSET 0x0000000000000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_LSB 16 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MSB 23 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MASK 0x0000000000ff0000 + + + + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_OFFSET 0x0000000000000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_LSB 24 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MSB 31 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MASK 0x00000000ff000000 + + + + +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_OFFSET 0x0000000000000040 +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_LSB 32 +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MSB 56 +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff00000000 + + + + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x0000000000000040 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_LSB 57 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MSB 63 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe00000000000000 + + + + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_OFFSET 0x0000000000000048 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MSB 24 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MASK 0x0000000001ffffff + + + + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x0000000000000048 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_LSB 25 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MSB 31 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MASK 0x00000000fe000000 + + + + +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000000000000048 +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_LSB 32 +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MSB 56 +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff00000000 + + + + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000000000000048 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_LSB 57 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MSB 63 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe00000000000000 + + + + +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x0000000000000050 +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0 +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MSB 15 +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x000000000000ffff + + + + +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_OFFSET 0x0000000000000050 +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MASK 0x00000000ffff0000 + + + + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_OFFSET 0x0000000000000050 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_LSB 32 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MSB 63 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MASK 0xffffffff00000000 + + + + +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x0000000000000058 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MSB 31 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0x00000000ffffffff + + + + +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000058 +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 + + + + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000058 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_LSB 33 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MSB 33 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MASK 0x0000000200000000 + + + + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_OFFSET 0x0000000000000058 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_LSB 34 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MSB 49 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MASK 0x0003fffc00000000 + + + + +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_OFFSET 0x0000000000000058 +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_LSB 50 +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MSB 60 +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MASK 0x1ffc000000000000 + + + + +#define RX_PPDU_END_USER_STATS_RESERVED_23A_OFFSET 0x0000000000000058 +#define RX_PPDU_END_USER_STATS_RESERVED_23A_LSB 61 +#define RX_PPDU_END_USER_STATS_RESERVED_23A_MSB 63 +#define RX_PPDU_END_USER_STATS_RESERVED_23A_MASK 0xe000000000000000 + + + +#endif diff --git a/hw/qcn9224/rx_ppdu_end_user_stats_ext.h b/hw/qcn9224/rx_ppdu_end_user_stats_ext.h new file mode 100644 index 000000000000..5acff6f5d5f0 --- /dev/null +++ b/hw/qcn9224/rx_ppdu_end_user_stats_ext.h @@ -0,0 +1,218 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RX_PPDU_END_USER_STATS_EXT_H_ +#define _RX_PPDU_END_USER_STATS_EXT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_rxpcu_classification_overview.h" +#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 8 + +#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS_EXT 4 + + +struct rx_ppdu_end_user_stats_ext { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t fcs_ok_bitmap_95_64 : 32; + uint32_t fcs_ok_bitmap_127_96 : 32; + uint32_t fcs_ok_bitmap_159_128 : 32; + uint32_t fcs_ok_bitmap_191_160 : 32; + uint32_t fcs_ok_bitmap_223_192 : 32; + uint32_t fcs_ok_bitmap_255_224 : 32; + uint32_t corrupted_due_to_fifo_delay : 1, + reserved_7a : 31; +#else + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t fcs_ok_bitmap_95_64 : 32; + uint32_t fcs_ok_bitmap_127_96 : 32; + uint32_t fcs_ok_bitmap_159_128 : 32; + uint32_t fcs_ok_bitmap_191_160 : 32; + uint32_t fcs_ok_bitmap_223_192 : 32; + uint32_t fcs_ok_bitmap_255_224 : 32; + uint32_t reserved_7a : 31, + corrupted_due_to_fifo_delay : 1; +#endif +}; + + + + + + + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 + + + + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 + + + + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 + + + + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 + + + + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 + + + + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 + + + + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 + + + + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080 + + + + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100 + + + + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000fe00 + + + + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 + + + + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_LSB 32 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MSB 63 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MASK 0xffffffff00000000 + + + + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MASK 0x00000000ffffffff + + + + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_LSB 32 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MSB 63 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MASK 0xffffffff00000000 + + + + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_OFFSET 0x0000000000000010 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MASK 0x00000000ffffffff + + + + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_OFFSET 0x0000000000000010 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_LSB 32 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MSB 63 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MASK 0xffffffff00000000 + + + + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_OFFSET 0x0000000000000018 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MASK 0x00000000ffffffff + + + + +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000018 +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 + + + + +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_OFFSET 0x0000000000000018 +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_LSB 33 +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MSB 63 +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MASK 0xfffffffe00000000 + + + +#endif diff --git a/hw/qcn9224/rx_ppdu_start.h b/hw/qcn9224/rx_ppdu_start.h new file mode 100644 index 000000000000..e2185859fed5 --- /dev/null +++ b/hw/qcn9224/rx_ppdu_start.h @@ -0,0 +1,124 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RX_PPDU_START_H_ +#define _RX_PPDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_PPDU_START 6 + +#define NUM_OF_QWORDS_RX_PPDU_START 3 + + +struct rx_ppdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_ppdu_id : 16, + preamble_time_to_rxframe : 8, + reserved_0a : 8; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t rxframe_assert_timestamp : 32; + uint32_t tlv64_padding : 32; +#else + uint32_t reserved_0a : 8, + preamble_time_to_rxframe : 8, + phy_ppdu_id : 16; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t rxframe_assert_timestamp : 32; + uint32_t tlv64_padding : 32; +#endif +}; + + + + +#define RX_PPDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_PPDU_START_PHY_PPDU_ID_LSB 0 +#define RX_PPDU_START_PHY_PPDU_ID_MSB 15 +#define RX_PPDU_START_PHY_PPDU_ID_MASK 0x000000000000ffff + + + + +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000000 +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB 16 +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB 23 +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK 0x0000000000ff0000 + + + + +#define RX_PPDU_START_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_PPDU_START_RESERVED_0A_LSB 24 +#define RX_PPDU_START_RESERVED_0A_MSB 31 +#define RX_PPDU_START_RESERVED_0A_MASK 0x00000000ff000000 + + + + +#define RX_PPDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000000 +#define RX_PPDU_START_SW_PHY_META_DATA_LSB 32 +#define RX_PPDU_START_SW_PHY_META_DATA_MSB 63 +#define RX_PPDU_START_SW_PHY_META_DATA_MASK 0xffffffff00000000 + + + + +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000008 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff + + + + +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 + + + + +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET 0x0000000000000010 +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB 0 +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB 31 +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK 0x00000000ffffffff + + + + +#define RX_PPDU_START_TLV64_PADDING_OFFSET 0x0000000000000010 +#define RX_PPDU_START_TLV64_PADDING_LSB 32 +#define RX_PPDU_START_TLV64_PADDING_MSB 63 +#define RX_PPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif diff --git a/hw/qcn9224/rx_ppdu_start_user_info.h b/hw/qcn9224/rx_ppdu_start_user_info.h new file mode 100644 index 000000000000..f790bf676f83 --- /dev/null +++ b/hw/qcn9224/rx_ppdu_start_user_info.h @@ -0,0 +1,330 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RX_PPDU_START_USER_INFO_H_ +#define _RX_PPDU_START_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "receive_user_info.h" +#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 8 + +#define NUM_OF_QWORDS_RX_PPDU_START_USER_INFO 4 + + +struct rx_ppdu_start_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct receive_user_info receive_user_info_details; +#else + struct receive_user_info receive_user_info_details; +#endif +}; + + + + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x000000000000ffff + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x0000000000ff0000 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x0000000010000000 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0x00000000e0000000 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 32 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 35 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f00000000 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 36 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 37 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x0000003000000000 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_HE_RANGING_NDP_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_HE_RANGING_NDP_LSB 38 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_HE_RANGING_NDP_MSB 38 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_HE_RANGING_NDP_MASK 0x0000004000000000 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_LSB 39 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MSB 39 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 40 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 47 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff0000000000 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 48 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 50 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x0007000000000000 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 51 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 55 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f8000000000000 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 56 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 63 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff00000000000000 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x0000000000000001 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 7 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x00000000000000fe + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x0000000000000700 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x0000000000003800 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x0000000000004000 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x0000000000008000 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x00000000000f0000 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x0000000000f00000 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x000000000f000000 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0x00000000f0000000 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 32 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 37 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f00000000 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 38 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 39 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c000000000 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 40 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 45 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f0000000000 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 46 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 47 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c00000000000 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 48 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 53 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f000000000000 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 54 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 55 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c0000000000000 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 56 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 61 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f00000000000000 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 62 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 63 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0xc000000000000000 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET 0x0000000000000010 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK 0x00000000ffffffff + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET 0x0000000000000010 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB 32 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB 63 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK 0xffffffff00000000 + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET 0x0000000000000018 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK 0x00000000ffffffff + + + + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET 0x0000000000000018 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB 32 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB 63 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK 0xffffffff00000000 + + + +#endif diff --git a/hw/qcn9224/rx_reo_queue.h b/hw/qcn9224/rx_reo_queue.h new file mode 100644 index 000000000000..3839c80a74c2 --- /dev/null +++ b/hw/qcn9224/rx_reo_queue.h @@ -0,0 +1,732 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RX_REO_QUEUE_H_ +#define _RX_REO_QUEUE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" +#define NUM_OF_DWORDS_RX_REO_QUEUE 32 + + +struct rx_reo_queue { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_descriptor_header descriptor_header; + uint32_t receive_queue_number : 16, + reserved_1b : 16; + uint32_t vld : 1, + associated_link_descriptor_counter : 2, + disable_duplicate_detection : 1, + soft_reorder_enable : 1, + ac : 2, + bar : 1, + rty : 1, + chk_2k_mode : 1, + oor_mode : 1, + ba_window_size : 10, + pn_check_needed : 1, + pn_shall_be_even : 1, + pn_shall_be_uneven : 1, + pn_handling_enable : 1, + pn_size : 2, + ignore_ampdu_flag : 1, + reserved_2b : 4; + uint32_t svld : 1, + ssn : 12, + current_index : 10, + seq_2k_error_detected_flag : 1, + pn_error_detected_flag : 1, + reserved_3a : 6, + pn_valid : 1; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t last_rx_enqueue_timestamp : 32; + uint32_t last_rx_dequeue_timestamp : 32; + uint32_t ptr_to_next_aging_queue_31_0 : 32; + uint32_t ptr_to_next_aging_queue_39_32 : 8, + reserved_11a : 24; + uint32_t ptr_to_previous_aging_queue_31_0 : 32; + uint32_t ptr_to_previous_aging_queue_39_32 : 8, + statistics_counter_index : 6, + reserved_13a : 18; + uint32_t rx_bitmap_31_0 : 32; + uint32_t rx_bitmap_63_32 : 32; + uint32_t rx_bitmap_95_64 : 32; + uint32_t rx_bitmap_127_96 : 32; + uint32_t rx_bitmap_159_128 : 32; + uint32_t rx_bitmap_191_160 : 32; + uint32_t rx_bitmap_223_192 : 32; + uint32_t rx_bitmap_255_224 : 32; + uint32_t rx_bitmap_287_256 : 32; + uint32_t current_mpdu_count : 7, + current_msdu_count : 25; + uint32_t last_sn_reg_index : 4, + timeout_count : 6, + forward_due_to_bar_count : 6, + duplicate_count : 16; + uint32_t frames_in_order_count : 24, + bar_received_count : 8; + uint32_t mpdu_frames_processed_count : 32; + uint32_t msdu_frames_processed_count : 32; + uint32_t total_processed_byte_count : 32; + uint32_t late_receive_mpdu_count : 12, + window_jump_2k : 4, + hole_count : 16; + uint32_t aging_drop_mpdu_count : 16, + aging_drop_interval : 8, + reserved_30 : 8; + uint32_t reserved_31 : 32; +#else + struct uniform_descriptor_header descriptor_header; + uint32_t reserved_1b : 16, + receive_queue_number : 16; + uint32_t reserved_2b : 4, + ignore_ampdu_flag : 1, + pn_size : 2, + pn_handling_enable : 1, + pn_shall_be_uneven : 1, + pn_shall_be_even : 1, + pn_check_needed : 1, + ba_window_size : 10, + oor_mode : 1, + chk_2k_mode : 1, + rty : 1, + bar : 1, + ac : 2, + soft_reorder_enable : 1, + disable_duplicate_detection : 1, + associated_link_descriptor_counter : 2, + vld : 1; + uint32_t pn_valid : 1, + reserved_3a : 6, + pn_error_detected_flag : 1, + seq_2k_error_detected_flag : 1, + current_index : 10, + ssn : 12, + svld : 1; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t last_rx_enqueue_timestamp : 32; + uint32_t last_rx_dequeue_timestamp : 32; + uint32_t ptr_to_next_aging_queue_31_0 : 32; + uint32_t reserved_11a : 24, + ptr_to_next_aging_queue_39_32 : 8; + uint32_t ptr_to_previous_aging_queue_31_0 : 32; + uint32_t reserved_13a : 18, + statistics_counter_index : 6, + ptr_to_previous_aging_queue_39_32 : 8; + uint32_t rx_bitmap_31_0 : 32; + uint32_t rx_bitmap_63_32 : 32; + uint32_t rx_bitmap_95_64 : 32; + uint32_t rx_bitmap_127_96 : 32; + uint32_t rx_bitmap_159_128 : 32; + uint32_t rx_bitmap_191_160 : 32; + uint32_t rx_bitmap_223_192 : 32; + uint32_t rx_bitmap_255_224 : 32; + uint32_t rx_bitmap_287_256 : 32; + uint32_t current_msdu_count : 25, + current_mpdu_count : 7; + uint32_t duplicate_count : 16, + forward_due_to_bar_count : 6, + timeout_count : 6, + last_sn_reg_index : 4; + uint32_t bar_received_count : 8, + frames_in_order_count : 24; + uint32_t mpdu_frames_processed_count : 32; + uint32_t msdu_frames_processed_count : 32; + uint32_t total_processed_byte_count : 32; + uint32_t hole_count : 16, + window_jump_2k : 4, + late_receive_mpdu_count : 12; + uint32_t reserved_30 : 8, + aging_drop_interval : 8, + aging_drop_mpdu_count : 16; + uint32_t reserved_31 : 32; +#endif +}; + + + + + + + +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + + + + +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + + + + +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 + + + + +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 0 +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 15 +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + + + + +#define RX_REO_QUEUE_RESERVED_1B_OFFSET 0x00000004 +#define RX_REO_QUEUE_RESERVED_1B_LSB 16 +#define RX_REO_QUEUE_RESERVED_1B_MSB 31 +#define RX_REO_QUEUE_RESERVED_1B_MASK 0xffff0000 + + + + +#define RX_REO_QUEUE_VLD_OFFSET 0x00000008 +#define RX_REO_QUEUE_VLD_LSB 0 +#define RX_REO_QUEUE_VLD_MSB 0 +#define RX_REO_QUEUE_VLD_MASK 0x00000001 + + + + +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1 +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 2 +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006 + + + + +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 3 +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 3 +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008 + + + + +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x00000008 +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 4 +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 4 +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x00000010 + + + + +#define RX_REO_QUEUE_AC_OFFSET 0x00000008 +#define RX_REO_QUEUE_AC_LSB 5 +#define RX_REO_QUEUE_AC_MSB 6 +#define RX_REO_QUEUE_AC_MASK 0x00000060 + + + + +#define RX_REO_QUEUE_BAR_OFFSET 0x00000008 +#define RX_REO_QUEUE_BAR_LSB 7 +#define RX_REO_QUEUE_BAR_MSB 7 +#define RX_REO_QUEUE_BAR_MASK 0x00000080 + + + + +#define RX_REO_QUEUE_RTY_OFFSET 0x00000008 +#define RX_REO_QUEUE_RTY_LSB 8 +#define RX_REO_QUEUE_RTY_MSB 8 +#define RX_REO_QUEUE_RTY_MASK 0x00000100 + + + + +#define RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x00000008 +#define RX_REO_QUEUE_CHK_2K_MODE_LSB 9 +#define RX_REO_QUEUE_CHK_2K_MODE_MSB 9 +#define RX_REO_QUEUE_CHK_2K_MODE_MASK 0x00000200 + + + + +#define RX_REO_QUEUE_OOR_MODE_OFFSET 0x00000008 +#define RX_REO_QUEUE_OOR_MODE_LSB 10 +#define RX_REO_QUEUE_OOR_MODE_MSB 10 +#define RX_REO_QUEUE_OOR_MODE_MASK 0x00000400 + + + + +#define RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x00000008 +#define RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 11 +#define RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 20 +#define RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x001ff800 + + + + +#define RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 21 +#define RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 21 +#define RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x00200000 + + + + +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 22 +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 22 +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x00400000 + + + + +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 23 +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 23 +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x00800000 + + + + +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 24 +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 24 +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x01000000 + + + + +#define RX_REO_QUEUE_PN_SIZE_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_SIZE_LSB 25 +#define RX_REO_QUEUE_PN_SIZE_MSB 26 +#define RX_REO_QUEUE_PN_SIZE_MASK 0x06000000 + + + + +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 27 +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 27 +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x08000000 + + + + +#define RX_REO_QUEUE_RESERVED_2B_OFFSET 0x00000008 +#define RX_REO_QUEUE_RESERVED_2B_LSB 28 +#define RX_REO_QUEUE_RESERVED_2B_MSB 31 +#define RX_REO_QUEUE_RESERVED_2B_MASK 0xf0000000 + + + + +#define RX_REO_QUEUE_SVLD_OFFSET 0x0000000c +#define RX_REO_QUEUE_SVLD_LSB 0 +#define RX_REO_QUEUE_SVLD_MSB 0 +#define RX_REO_QUEUE_SVLD_MASK 0x00000001 + + + + +#define RX_REO_QUEUE_SSN_OFFSET 0x0000000c +#define RX_REO_QUEUE_SSN_LSB 1 +#define RX_REO_QUEUE_SSN_MSB 12 +#define RX_REO_QUEUE_SSN_MASK 0x00001ffe + + + + +#define RX_REO_QUEUE_CURRENT_INDEX_OFFSET 0x0000000c +#define RX_REO_QUEUE_CURRENT_INDEX_LSB 13 +#define RX_REO_QUEUE_CURRENT_INDEX_MSB 22 +#define RX_REO_QUEUE_CURRENT_INDEX_MASK 0x007fe000 + + + + +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 23 +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 23 +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00800000 + + + + +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 24 +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 24 +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x01000000 + + + + +#define RX_REO_QUEUE_RESERVED_3A_OFFSET 0x0000000c +#define RX_REO_QUEUE_RESERVED_3A_LSB 25 +#define RX_REO_QUEUE_RESERVED_3A_MSB 30 +#define RX_REO_QUEUE_RESERVED_3A_MASK 0x7e000000 + + + + +#define RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000c +#define RX_REO_QUEUE_PN_VALID_LSB 31 +#define RX_REO_QUEUE_PN_VALID_MSB 31 +#define RX_REO_QUEUE_PN_VALID_MASK 0x80000000 + + + + +#define RX_REO_QUEUE_PN_31_0_OFFSET 0x00000010 +#define RX_REO_QUEUE_PN_31_0_LSB 0 +#define RX_REO_QUEUE_PN_31_0_MSB 31 +#define RX_REO_QUEUE_PN_31_0_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_PN_63_32_OFFSET 0x00000014 +#define RX_REO_QUEUE_PN_63_32_LSB 0 +#define RX_REO_QUEUE_PN_63_32_MSB 31 +#define RX_REO_QUEUE_PN_63_32_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_PN_95_64_OFFSET 0x00000018 +#define RX_REO_QUEUE_PN_95_64_LSB 0 +#define RX_REO_QUEUE_PN_95_64_MSB 31 +#define RX_REO_QUEUE_PN_95_64_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_PN_127_96_OFFSET 0x0000001c +#define RX_REO_QUEUE_PN_127_96_LSB 0 +#define RX_REO_QUEUE_PN_127_96_MSB 31 +#define RX_REO_QUEUE_PN_127_96_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MSB 31 +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31 +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MSB 31 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MSB 7 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff + + + + +#define RX_REO_QUEUE_RESERVED_11A_OFFSET 0x0000002c +#define RX_REO_QUEUE_RESERVED_11A_LSB 8 +#define RX_REO_QUEUE_RESERVED_11A_MSB 31 +#define RX_REO_QUEUE_RESERVED_11A_MASK 0xffffff00 + + + + +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MSB 31 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MSB 7 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff + + + + +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_OFFSET 0x00000034 +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_LSB 8 +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MSB 13 +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MASK 0x00003f00 + + + + +#define RX_REO_QUEUE_RESERVED_13A_OFFSET 0x00000034 +#define RX_REO_QUEUE_RESERVED_13A_LSB 14 +#define RX_REO_QUEUE_RESERVED_13A_MSB 31 +#define RX_REO_QUEUE_RESERVED_13A_MASK 0xffffc000 + + + + +#define RX_REO_QUEUE_RX_BITMAP_31_0_OFFSET 0x00000038 +#define RX_REO_QUEUE_RX_BITMAP_31_0_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_31_0_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_31_0_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_RX_BITMAP_63_32_OFFSET 0x0000003c +#define RX_REO_QUEUE_RX_BITMAP_63_32_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_63_32_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_63_32_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_RX_BITMAP_95_64_OFFSET 0x00000040 +#define RX_REO_QUEUE_RX_BITMAP_95_64_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_95_64_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_95_64_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_RX_BITMAP_127_96_OFFSET 0x00000044 +#define RX_REO_QUEUE_RX_BITMAP_127_96_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_127_96_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_127_96_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_RX_BITMAP_159_128_OFFSET 0x00000048 +#define RX_REO_QUEUE_RX_BITMAP_159_128_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_159_128_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_159_128_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_RX_BITMAP_191_160_OFFSET 0x0000004c +#define RX_REO_QUEUE_RX_BITMAP_191_160_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_191_160_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_191_160_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_RX_BITMAP_223_192_OFFSET 0x00000050 +#define RX_REO_QUEUE_RX_BITMAP_223_192_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_223_192_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_223_192_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_RX_BITMAP_255_224_OFFSET 0x00000054 +#define RX_REO_QUEUE_RX_BITMAP_255_224_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_255_224_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_255_224_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_RX_BITMAP_287_256_OFFSET 0x00000058 +#define RX_REO_QUEUE_RX_BITMAP_287_256_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_287_256_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_287_256_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MSB 6 +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MASK 0x0000007f + + + + +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_LSB 7 +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MSB 31 +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MASK 0xffffff80 + + + + +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_OFFSET 0x00000060 +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_LSB 0 +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_MSB 3 +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_MASK 0x0000000f + + + + +#define RX_REO_QUEUE_TIMEOUT_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_TIMEOUT_COUNT_LSB 4 +#define RX_REO_QUEUE_TIMEOUT_COUNT_MSB 9 +#define RX_REO_QUEUE_TIMEOUT_COUNT_MASK 0x000003f0 + + + + +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_LSB 10 +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MSB 15 +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 + + + + +#define RX_REO_QUEUE_DUPLICATE_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_DUPLICATE_COUNT_LSB 16 +#define RX_REO_QUEUE_DUPLICATE_COUNT_MSB 31 +#define RX_REO_QUEUE_DUPLICATE_COUNT_MASK 0xffff0000 + + + + +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000064 +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_LSB 0 +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MSB 23 +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff + + + + +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_OFFSET 0x00000064 +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_LSB 24 +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MSB 31 +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MASK 0xff000000 + + + + +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068 +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MSB 31 +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000006c +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MSB 31 +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000070 +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MSB 31 +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000074 +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MSB 11 +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff + + + + +#define RX_REO_QUEUE_WINDOW_JUMP_2K_OFFSET 0x00000074 +#define RX_REO_QUEUE_WINDOW_JUMP_2K_LSB 12 +#define RX_REO_QUEUE_WINDOW_JUMP_2K_MSB 15 +#define RX_REO_QUEUE_WINDOW_JUMP_2K_MASK 0x0000f000 + + + + +#define RX_REO_QUEUE_HOLE_COUNT_OFFSET 0x00000074 +#define RX_REO_QUEUE_HOLE_COUNT_LSB 16 +#define RX_REO_QUEUE_HOLE_COUNT_MSB 31 +#define RX_REO_QUEUE_HOLE_COUNT_MASK 0xffff0000 + + + + +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_OFFSET 0x00000078 +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MSB 15 +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MASK 0x0000ffff + + + + +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_OFFSET 0x00000078 +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_LSB 16 +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_MSB 23 +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_MASK 0x00ff0000 + + + + +#define RX_REO_QUEUE_RESERVED_30_OFFSET 0x00000078 +#define RX_REO_QUEUE_RESERVED_30_LSB 24 +#define RX_REO_QUEUE_RESERVED_30_MSB 31 +#define RX_REO_QUEUE_RESERVED_30_MASK 0xff000000 + + + + +#define RX_REO_QUEUE_RESERVED_31_OFFSET 0x0000007c +#define RX_REO_QUEUE_RESERVED_31_LSB 0 +#define RX_REO_QUEUE_RESERVED_31_MSB 31 +#define RX_REO_QUEUE_RESERVED_31_MASK 0xffffffff + + + +#endif diff --git a/hw/qcn9224/rx_reo_queue_ext.h b/hw/qcn9224/rx_reo_queue_ext.h new file mode 100644 index 000000000000..1d5b6b4f0983 --- /dev/null +++ b/hw/qcn9224/rx_reo_queue_ext.h @@ -0,0 +1,683 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RX_REO_QUEUE_EXT_H_ +#define _RX_REO_QUEUE_EXT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_link_ptr.h" +#include "uniform_descriptor_header.h" +#define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32 + + +struct rx_reo_queue_ext { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_descriptor_header descriptor_header; + uint32_t reserved_1a : 32; + struct rx_mpdu_link_ptr mpdu_link_pointer_0; + struct rx_mpdu_link_ptr mpdu_link_pointer_1; + struct rx_mpdu_link_ptr mpdu_link_pointer_2; + struct rx_mpdu_link_ptr mpdu_link_pointer_3; + struct rx_mpdu_link_ptr mpdu_link_pointer_4; + struct rx_mpdu_link_ptr mpdu_link_pointer_5; + struct rx_mpdu_link_ptr mpdu_link_pointer_6; + struct rx_mpdu_link_ptr mpdu_link_pointer_7; + struct rx_mpdu_link_ptr mpdu_link_pointer_8; + struct rx_mpdu_link_ptr mpdu_link_pointer_9; + struct rx_mpdu_link_ptr mpdu_link_pointer_10; + struct rx_mpdu_link_ptr mpdu_link_pointer_11; + struct rx_mpdu_link_ptr mpdu_link_pointer_12; + struct rx_mpdu_link_ptr mpdu_link_pointer_13; + struct rx_mpdu_link_ptr mpdu_link_pointer_14; +#else + struct uniform_descriptor_header descriptor_header; + uint32_t reserved_1a : 32; + struct rx_mpdu_link_ptr mpdu_link_pointer_0; + struct rx_mpdu_link_ptr mpdu_link_pointer_1; + struct rx_mpdu_link_ptr mpdu_link_pointer_2; + struct rx_mpdu_link_ptr mpdu_link_pointer_3; + struct rx_mpdu_link_ptr mpdu_link_pointer_4; + struct rx_mpdu_link_ptr mpdu_link_pointer_5; + struct rx_mpdu_link_ptr mpdu_link_pointer_6; + struct rx_mpdu_link_ptr mpdu_link_pointer_7; + struct rx_mpdu_link_ptr mpdu_link_pointer_8; + struct rx_mpdu_link_ptr mpdu_link_pointer_9; + struct rx_mpdu_link_ptr mpdu_link_pointer_10; + struct rx_mpdu_link_ptr mpdu_link_pointer_11; + struct rx_mpdu_link_ptr mpdu_link_pointer_12; + struct rx_mpdu_link_ptr mpdu_link_pointer_13; + struct rx_mpdu_link_ptr mpdu_link_pointer_14; +#endif +}; + + + + + + + +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + + + + +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + + + + +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 + + + + +#define RX_REO_QUEUE_EXT_RESERVED_1A_OFFSET 0x00000004 +#define RX_REO_QUEUE_EXT_RESERVED_1A_LSB 0 +#define RX_REO_QUEUE_EXT_RESERVED_1A_MSB 31 +#define RX_REO_QUEUE_EXT_RESERVED_1A_MASK 0xffffffff + + + + + + + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + + + + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + + + + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + + + + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + + + + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + + + + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + + + + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + + + + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + + + + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + + + + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + + + + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + + + + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + + + + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + + + + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + + + + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + +#endif diff --git a/hw/qcn9224/rx_reo_queue_reference.h b/hw/qcn9224/rx_reo_queue_reference.h new file mode 100644 index 000000000000..1c2beac8a1e1 --- /dev/null +++ b/hw/qcn9224/rx_reo_queue_reference.h @@ -0,0 +1,82 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RX_REO_QUEUE_REFERENCE_H_ +#define _RX_REO_QUEUE_REFERENCE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_REO_QUEUE_REFERENCE 2 + + +struct rx_reo_queue_reference { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + reserved_1 : 8, + receive_queue_number : 16; +#else + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t receive_queue_number : 16, + reserved_1 : 8, + rx_reo_queue_desc_addr_39_32 : 8; +#endif +}; + + + + +#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000000 +#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + + + + +#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000004 +#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + + + + +#define RX_REO_QUEUE_REFERENCE_RESERVED_1_OFFSET 0x00000004 +#define RX_REO_QUEUE_REFERENCE_RESERVED_1_LSB 8 +#define RX_REO_QUEUE_REFERENCE_RESERVED_1_MSB 15 +#define RX_REO_QUEUE_REFERENCE_RESERVED_1_MASK 0x0000ff00 + + + + +#define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 +#define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_LSB 16 +#define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_MSB 31 +#define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_MASK 0xffff0000 + + + +#endif diff --git a/hw/qcn9224/rx_rxpcu_classification_overview.h b/hw/qcn9224/rx_rxpcu_classification_overview.h new file mode 100644 index 000000000000..08269e544960 --- /dev/null +++ b/hw/qcn9224/rx_rxpcu_classification_overview.h @@ -0,0 +1,152 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ +#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1 + + +struct rx_rxpcu_classification_overview { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t filter_pass_mpdus : 1, + filter_pass_mpdus_fcs_ok : 1, + monitor_direct_mpdus : 1, + monitor_direct_mpdus_fcs_ok : 1, + monitor_other_mpdus : 1, + monitor_other_mpdus_fcs_ok : 1, + phyrx_abort_received : 1, + filter_pass_monitor_ovrd_mpdus : 1, + filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, + reserved_0 : 7, + phy_ppdu_id : 16; +#else + uint32_t phy_ppdu_id : 16, + reserved_0 : 7, + filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, + filter_pass_monitor_ovrd_mpdus : 1, + phyrx_abort_received : 1, + monitor_other_mpdus_fcs_ok : 1, + monitor_other_mpdus : 1, + monitor_direct_mpdus_fcs_ok : 1, + monitor_direct_mpdus : 1, + filter_pass_mpdus_fcs_ok : 1, + filter_pass_mpdus : 1; +#endif +}; + + + + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_LSB 0 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MSB 0 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MASK 0x00000001 + + + + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MSB 1 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 + + + + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MSB 2 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MASK 0x00000004 + + + + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 + + + + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MSB 4 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MASK 0x00000010 + + + + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 + + + + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MSB 6 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MASK 0x00000040 + + + + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x00000080 + + + + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100 + + + + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_LSB 9 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MSB 15 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MASK 0x0000fe00 + + + + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_LSB 16 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MSB 31 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MASK 0xffff0000 + + + +#endif diff --git a/hw/qcn9224/rx_timing_offset_info.h b/hw/qcn9224/rx_timing_offset_info.h new file mode 100644 index 000000000000..afc3420616fa --- /dev/null +++ b/hw/qcn9224/rx_timing_offset_info.h @@ -0,0 +1,62 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RX_TIMING_OFFSET_INFO_H_ +#define _RX_TIMING_OFFSET_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_TIMING_OFFSET_INFO 1 + + +struct rx_timing_offset_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t residual_phase_offset : 12, + reserved : 20; +#else + uint32_t reserved : 20, + residual_phase_offset : 12; +#endif +}; + + + + +#define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000000 +#define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_LSB 0 +#define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_MSB 11 +#define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + + + + +#define RX_TIMING_OFFSET_INFO_RESERVED_OFFSET 0x00000000 +#define RX_TIMING_OFFSET_INFO_RESERVED_LSB 12 +#define RX_TIMING_OFFSET_INFO_RESERVED_MSB 31 +#define RX_TIMING_OFFSET_INFO_RESERVED_MASK 0xfffff000 + + + +#endif diff --git a/hw/qcn9224/rxpcu_ppdu_end_info.h b/hw/qcn9224/rxpcu_ppdu_end_info.h new file mode 100644 index 000000000000..919ee795bce4 --- /dev/null +++ b/hw/qcn9224/rxpcu_ppdu_end_info.h @@ -0,0 +1,1180 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RXPCU_PPDU_END_INFO_H_ +#define _RXPCU_PPDU_END_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phyrx_abort_request_info.h" +#include "macrx_abort_request_info.h" +#include "rxpcu_ppdu_end_layout_info.h" +#define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 28 + +#define NUM_OF_QWORDS_RXPCU_PPDU_END_INFO 14 + + +struct rxpcu_ppdu_end_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t wb_timestamp_lower_32 : 32; + uint32_t wb_timestamp_upper_32 : 32; + uint32_t rx_antenna : 24, + tx_ht_vht_ack : 1, + unsupported_mu_nc : 1, + otp_txbf_disable : 1, + previous_tlv_corrupted : 1, + phyrx_abort_request_info_valid : 1, + macrx_abort_request_info_valid : 1, + reserved : 2; + uint32_t coex_bt_tx_from_start_of_rx : 1, + coex_bt_tx_after_start_of_rx : 1, + coex_wan_tx_from_start_of_rx : 1, + coex_wan_tx_after_start_of_rx : 1, + coex_wlan_tx_from_start_of_rx : 1, + coex_wlan_tx_after_start_of_rx : 1, + mpdu_delimiter_errors_seen : 1, + ftm_tm : 2, + dialog_token : 8, + follow_up_dialog_token : 8, + bb_captured_channel : 1, + bb_captured_reason : 3, + bb_captured_timeout : 1, + reserved_3 : 2; + uint32_t before_mpdu_count_passing_fcs : 10, + before_mpdu_count_failing_fcs : 10, + after_mpdu_count_passing_fcs : 10, + reserved_4 : 2; + uint32_t after_mpdu_count_failing_fcs : 10, + reserved_5 : 22; + uint32_t phy_timestamp_tx_lower_32 : 32; + uint32_t phy_timestamp_tx_upper_32 : 32; + uint32_t bb_length : 16, + bb_data : 1, + reserved_8 : 3, + first_bt_broadcast_status_details : 12; + uint32_t rx_ppdu_duration : 24, + reserved_9 : 8; + uint32_t ast_index : 16, + ast_index_valid : 1, + reserved_10 : 3, + second_bt_broadcast_status_details : 12; + struct phyrx_abort_request_info phyrx_abort_request_info_details; + struct macrx_abort_request_info macrx_abort_request_info_details; + uint16_t pre_bt_broadcast_status_details : 12, + reserved_12a : 4; + uint32_t non_qos_sn_info_valid : 1, + reserved_13a : 5, + non_qos_sn_highest : 12, + non_qos_sn_highest_retry_setting : 1, + non_qos_sn_lowest : 12, + non_qos_sn_lowest_retry_setting : 1; + uint32_t qos_sn_1_info_valid : 1, + reserved_14a : 1, + qos_sn_1_tid : 4, + qos_sn_1_highest : 12, + qos_sn_1_highest_retry_setting : 1, + qos_sn_1_lowest : 12, + qos_sn_1_lowest_retry_setting : 1; + uint32_t qos_sn_2_info_valid : 1, + reserved_15a : 1, + qos_sn_2_tid : 4, + qos_sn_2_highest : 12, + qos_sn_2_highest_retry_setting : 1, + qos_sn_2_lowest : 12, + qos_sn_2_lowest_retry_setting : 1; + struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; + uint32_t corrupted_due_to_fifo_delay : 1, + qos_sn_1_more_frag_state : 1, + qos_sn_1_frag_num_state : 4, + qos_sn_2_more_frag_state : 1, + qos_sn_2_frag_num_state : 4, + reserved_26a : 21; + uint32_t rx_ppdu_end_marker : 32; +#else + uint32_t wb_timestamp_lower_32 : 32; + uint32_t wb_timestamp_upper_32 : 32; + uint32_t reserved : 2, + macrx_abort_request_info_valid : 1, + phyrx_abort_request_info_valid : 1, + previous_tlv_corrupted : 1, + otp_txbf_disable : 1, + unsupported_mu_nc : 1, + tx_ht_vht_ack : 1, + rx_antenna : 24; + uint32_t reserved_3 : 2, + bb_captured_timeout : 1, + bb_captured_reason : 3, + bb_captured_channel : 1, + follow_up_dialog_token : 8, + dialog_token : 8, + ftm_tm : 2, + mpdu_delimiter_errors_seen : 1, + coex_wlan_tx_after_start_of_rx : 1, + coex_wlan_tx_from_start_of_rx : 1, + coex_wan_tx_after_start_of_rx : 1, + coex_wan_tx_from_start_of_rx : 1, + coex_bt_tx_after_start_of_rx : 1, + coex_bt_tx_from_start_of_rx : 1; + uint32_t reserved_4 : 2, + after_mpdu_count_passing_fcs : 10, + before_mpdu_count_failing_fcs : 10, + before_mpdu_count_passing_fcs : 10; + uint32_t reserved_5 : 22, + after_mpdu_count_failing_fcs : 10; + uint32_t phy_timestamp_tx_lower_32 : 32; + uint32_t phy_timestamp_tx_upper_32 : 32; + uint32_t first_bt_broadcast_status_details : 12, + reserved_8 : 3, + bb_data : 1, + bb_length : 16; + uint32_t reserved_9 : 8, + rx_ppdu_duration : 24; + uint32_t second_bt_broadcast_status_details : 12, + reserved_10 : 3, + ast_index_valid : 1, + ast_index : 16; + struct phyrx_abort_request_info phyrx_abort_request_info_details; + uint32_t reserved_12a : 4, + pre_bt_broadcast_status_details : 12; + struct macrx_abort_request_info macrx_abort_request_info_details; + uint32_t non_qos_sn_lowest_retry_setting : 1, + non_qos_sn_lowest : 12, + non_qos_sn_highest_retry_setting : 1, + non_qos_sn_highest : 12, + reserved_13a : 5, + non_qos_sn_info_valid : 1; + uint32_t qos_sn_1_lowest_retry_setting : 1, + qos_sn_1_lowest : 12, + qos_sn_1_highest_retry_setting : 1, + qos_sn_1_highest : 12, + qos_sn_1_tid : 4, + reserved_14a : 1, + qos_sn_1_info_valid : 1; + uint32_t qos_sn_2_lowest_retry_setting : 1, + qos_sn_2_lowest : 12, + qos_sn_2_highest_retry_setting : 1, + qos_sn_2_highest : 12, + qos_sn_2_tid : 4, + reserved_15a : 1, + qos_sn_2_info_valid : 1; + struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; + uint32_t reserved_26a : 21, + qos_sn_2_frag_num_state : 4, + qos_sn_2_more_frag_state : 1, + qos_sn_1_frag_num_state : 4, + qos_sn_1_more_frag_state : 1, + corrupted_due_to_fifo_delay : 1; + uint32_t rx_ppdu_end_marker : 32; +#endif +}; + + + + +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MSB 31 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff + + + + +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_LSB 32 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MSB 63 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 + + + + +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_LSB 0 +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MSB 23 +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MASK 0x0000000000ffffff + + + + +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_LSB 24 +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MSB 24 +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MASK 0x0000000001000000 + + + + +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_LSB 25 +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MSB 25 +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MASK 0x0000000002000000 + + + + +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_LSB 26 +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MSB 26 +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MASK 0x0000000004000000 + + + + +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_LSB 27 +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MSB 27 +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MASK 0x0000000008000000 + + + + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MSB 28 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000010000000 + + + + +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MSB 29 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000020000000 + + + + +#define RXPCU_PPDU_END_INFO_RESERVED_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_RESERVED_LSB 30 +#define RXPCU_PPDU_END_INFO_RESERVED_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_MASK 0x00000000c0000000 + + + + +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_LSB 32 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MSB 32 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MASK 0x0000000100000000 + + + + +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_LSB 33 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MSB 33 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x0000000200000000 + + + + +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_LSB 34 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MSB 34 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x0000000400000000 + + + + +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_LSB 35 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MSB 35 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x0000000800000000 + + + + +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_LSB 36 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MSB 36 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x0000001000000000 + + + + +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 37 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MSB 37 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x0000002000000000 + + + + +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_LSB 38 +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MSB 38 +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x0000004000000000 + + + + +#define RXPCU_PPDU_END_INFO_FTM_TM_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_FTM_TM_LSB 39 +#define RXPCU_PPDU_END_INFO_FTM_TM_MSB 40 +#define RXPCU_PPDU_END_INFO_FTM_TM_MASK 0x0000018000000000 + + + + +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_LSB 41 +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MSB 48 +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MASK 0x0001fe0000000000 + + + + +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_LSB 49 +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MSB 56 +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe000000000000 + + + + +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_LSB 57 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MSB 57 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MASK 0x0200000000000000 + + + + +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_LSB 58 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MSB 60 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MASK 0x1c00000000000000 + + + + +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_LSB 61 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MSB 61 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MASK 0x2000000000000000 + + + + +#define RXPCU_PPDU_END_INFO_RESERVED_3_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_RESERVED_3_LSB 62 +#define RXPCU_PPDU_END_INFO_RESERVED_3_MSB 63 +#define RXPCU_PPDU_END_INFO_RESERVED_3_MASK 0xc000000000000000 + + + + +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MSB 9 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x00000000000003ff + + + + +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MSB 19 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x00000000000ffc00 + + + + +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MSB 29 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x000000003ff00000 + + + + +#define RXPCU_PPDU_END_INFO_RESERVED_4_OFFSET 0x0000000000000010 +#define RXPCU_PPDU_END_INFO_RESERVED_4_LSB 30 +#define RXPCU_PPDU_END_INFO_RESERVED_4_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_4_MASK 0x00000000c0000000 + + + + +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_LSB 32 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MSB 41 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff00000000 + + + + +#define RXPCU_PPDU_END_INFO_RESERVED_5_OFFSET 0x0000000000000010 +#define RXPCU_PPDU_END_INFO_RESERVED_5_LSB 42 +#define RXPCU_PPDU_END_INFO_RESERVED_5_MSB 63 +#define RXPCU_PPDU_END_INFO_RESERVED_5_MASK 0xfffffc0000000000 + + + + +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x0000000000000018 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MSB 31 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MASK 0x00000000ffffffff + + + + +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000000000000018 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_LSB 32 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MSB 63 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff00000000 + + + + +#define RXPCU_PPDU_END_INFO_BB_LENGTH_OFFSET 0x0000000000000020 +#define RXPCU_PPDU_END_INFO_BB_LENGTH_LSB 0 +#define RXPCU_PPDU_END_INFO_BB_LENGTH_MSB 15 +#define RXPCU_PPDU_END_INFO_BB_LENGTH_MASK 0x000000000000ffff + + + + +#define RXPCU_PPDU_END_INFO_BB_DATA_OFFSET 0x0000000000000020 +#define RXPCU_PPDU_END_INFO_BB_DATA_LSB 16 +#define RXPCU_PPDU_END_INFO_BB_DATA_MSB 16 +#define RXPCU_PPDU_END_INFO_BB_DATA_MASK 0x0000000000010000 + + + + +#define RXPCU_PPDU_END_INFO_RESERVED_8_OFFSET 0x0000000000000020 +#define RXPCU_PPDU_END_INFO_RESERVED_8_LSB 17 +#define RXPCU_PPDU_END_INFO_RESERVED_8_MSB 19 +#define RXPCU_PPDU_END_INFO_RESERVED_8_MASK 0x00000000000e0000 + + + + +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000020 +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 31 +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 + + + + +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 0x0000000000000020 +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 32 +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MSB 55 +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 0x00ffffff00000000 + + + + +#define RXPCU_PPDU_END_INFO_RESERVED_9_OFFSET 0x0000000000000020 +#define RXPCU_PPDU_END_INFO_RESERVED_9_LSB 56 +#define RXPCU_PPDU_END_INFO_RESERVED_9_MSB 63 +#define RXPCU_PPDU_END_INFO_RESERVED_9_MASK 0xff00000000000000 + + + + +#define RXPCU_PPDU_END_INFO_AST_INDEX_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_AST_INDEX_LSB 0 +#define RXPCU_PPDU_END_INFO_AST_INDEX_MSB 15 +#define RXPCU_PPDU_END_INFO_AST_INDEX_MASK 0x000000000000ffff + + + + +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_LSB 16 +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MSB 16 +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MASK 0x0000000000010000 + + + + +#define RXPCU_PPDU_END_INFO_RESERVED_10_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_RESERVED_10_LSB 17 +#define RXPCU_PPDU_END_INFO_RESERVED_10_MSB 19 +#define RXPCU_PPDU_END_INFO_RESERVED_10_MASK 0x00000000000e0000 + + + + +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 31 +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 + + + + + + + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 32 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MSB 39 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff00000000 + + + + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 40 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MSB 40 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x0000010000000000 + + + + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 41 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MSB 41 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x0000020000000000 + + + + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 42 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 47 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000fc0000000000 + + + + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 48 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MSB 63 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff000000000000 + + + + + + + +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MSB 7 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000ff + + + + +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 15 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x000000000000ff00 + + + + +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 16 +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 27 +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x000000000fff0000 + + + + +#define RXPCU_PPDU_END_INFO_RESERVED_12A_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_RESERVED_12A_LSB 28 +#define RXPCU_PPDU_END_INFO_RESERVED_12A_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_12A_MASK 0x00000000f0000000 + + + + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_LSB 32 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MSB 32 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MASK 0x0000000100000000 + + + + +#define RXPCU_PPDU_END_INFO_RESERVED_13A_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_RESERVED_13A_LSB 33 +#define RXPCU_PPDU_END_INFO_RESERVED_13A_MSB 37 +#define RXPCU_PPDU_END_INFO_RESERVED_13A_MASK 0x0000003e00000000 + + + + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_LSB 38 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MSB 49 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MASK 0x0003ffc000000000 + + + + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_LSB 50 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MSB 50 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 + + + + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_LSB 51 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MSB 62 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MASK 0x7ff8000000000000 + + + + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_LSB 63 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MSB 63 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 + + + + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_LSB 0 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MSB 0 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MASK 0x0000000000000001 + + + + +#define RXPCU_PPDU_END_INFO_RESERVED_14A_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_RESERVED_14A_LSB 1 +#define RXPCU_PPDU_END_INFO_RESERVED_14A_MSB 1 +#define RXPCU_PPDU_END_INFO_RESERVED_14A_MASK 0x0000000000000002 + + + + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_LSB 2 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MSB 5 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MASK 0x000000000000003c + + + + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_LSB 6 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MSB 17 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MASK 0x000000000003ffc0 + + + + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_LSB 18 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MSB 18 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MASK 0x0000000000040000 + + + + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_LSB 19 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MSB 30 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MASK 0x000000007ff80000 + + + + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_LSB 31 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MSB 31 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MASK 0x0000000080000000 + + + + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_LSB 32 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MSB 32 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MASK 0x0000000100000000 + + + + +#define RXPCU_PPDU_END_INFO_RESERVED_15A_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_RESERVED_15A_LSB 33 +#define RXPCU_PPDU_END_INFO_RESERVED_15A_MSB 33 +#define RXPCU_PPDU_END_INFO_RESERVED_15A_MASK 0x0000000200000000 + + + + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_LSB 34 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MSB 37 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MASK 0x0000003c00000000 + + + + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_LSB 38 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MSB 49 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MASK 0x0003ffc000000000 + + + + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_LSB 50 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MSB 50 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 + + + + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_LSB 51 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MSB 62 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MASK 0x7ff8000000000000 + + + + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_LSB 63 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MSB 63 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 + + + + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MSB 1 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MASK 0x0000000000000003 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_LSB 2 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MASK 0x00000000000000fc + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_LSB 8 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MSB 13 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MASK 0x0000000000003f00 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_LSB 14 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MSB 19 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MASK 0x00000000000fc000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_LSB 20 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MSB 25 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MASK 0x0000000003f00000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_LSB 26 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MASK 0x00000000fc000000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_LSB 32 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MSB 37 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MASK 0x0000003f00000000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_LSB 38 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MSB 43 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc000000000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_LSB 44 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MSB 49 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f00000000000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_LSB 50 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MSB 55 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MASK 0x00fc000000000000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_LSB 56 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MSB 62 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MASK 0x7f00000000000000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_LSB 63 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MSB 63 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MASK 0x8000000000000000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MSB 6 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MASK 0x000000000000007f + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_LSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MSB 13 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MASK 0x0000000000003f80 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_LSB 14 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MSB 20 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MASK 0x00000000001fc000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_LSB 21 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MSB 27 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MASK 0x000000000fe00000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_LSB 28 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MASK 0x00000000f0000000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_LSB 32 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MSB 38 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f00000000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_LSB 39 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MSB 45 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f8000000000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_LSB 46 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MSB 52 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc00000000000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_LSB 53 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MSB 59 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe0000000000000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_LSB 60 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MSB 63 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MASK 0xf000000000000000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MSB 6 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MASK 0x000000000000007f + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_LSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MSB 13 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MASK 0x0000000000003f80 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_LSB 14 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MSB 20 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MASK 0x00000000001fc000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x000000000fe00000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x0000000010000000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_LSB 29 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MASK 0x00000000e0000000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_LSB 32 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MSB 38 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MASK 0x0000007f00000000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_LSB 39 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MSB 46 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f8000000000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 47 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 47 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x0000800000000000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 48 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 55 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff000000000000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 56 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 56 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x0100000000000000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_LSB 57 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MSB 63 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MASK 0xfe00000000000000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MASK 0x00000000000000ff + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_LSB 8 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MSB 15 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MASK 0x000000000000ff00 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_LSB 16 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MSB 23 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MASK 0x0000000000ff0000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_LSB 24 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MASK 0x00000000ff000000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_LSB 32 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_MSB 39 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_MASK 0x000000ff00000000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_LSB 40 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MSB 47 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MASK 0x0000ff0000000000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_LSB 48 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MSB 55 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff000000000000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_LSB 56 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MSB 63 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MASK 0xff00000000000000 + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_OFFSET 0x0000000000000060 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MASK 0x00000000ffffffff + + + + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_OFFSET 0x0000000000000060 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_LSB 32 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MSB 63 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MASK 0xffffffff00000000 + + + + +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0 +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0 +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000000000001 + + + + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_LSB 1 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MSB 1 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MASK 0x0000000000000002 + + + + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_LSB 2 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MSB 5 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MASK 0x000000000000003c + + + + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_LSB 6 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MSB 6 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MASK 0x0000000000000040 + + + + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_LSB 7 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MSB 10 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MASK 0x0000000000000780 + + + + +#define RXPCU_PPDU_END_INFO_RESERVED_26A_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_RESERVED_26A_LSB 11 +#define RXPCU_PPDU_END_INFO_RESERVED_26A_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_26A_MASK 0x00000000fffff800 + + + + +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_LSB 32 +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MSB 63 +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MASK 0xffffffff00000000 + + + +#endif diff --git a/hw/qcn9224/rxpcu_ppdu_end_layout_info.h b/hw/qcn9224/rxpcu_ppdu_end_layout_info.h new file mode 100644 index 000000000000..2a34c5d8fab9 --- /dev/null +++ b/hw/qcn9224/rxpcu_ppdu_end_layout_info.h @@ -0,0 +1,482 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RXPCU_PPDU_END_LAYOUT_INFO_H_ +#define _RXPCU_PPDU_END_LAYOUT_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RXPCU_PPDU_END_LAYOUT_INFO 10 + + +struct rxpcu_ppdu_end_layout_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rssi_legacy_offset : 2, + l_sig_a_offset : 6, + l_sig_b_offset : 6, + ht_sig_offset : 6, + vht_sig_a_offset : 6, + repeat_l_sig_a_offset : 6; + uint32_t he_sig_a_su_offset : 6, + he_sig_a_mu_dl_offset : 6, + he_sig_a_mu_ul_offset : 6, + generic_u_sig_offset : 6, + rssi_ht_offset : 7, + reserved_1a : 1; + uint32_t vht_sig_b_su20_offset : 7, + vht_sig_b_su40_offset : 7, + vht_sig_b_su80_offset : 7, + vht_sig_b_su160_offset : 7, + reserved_2a : 4; + uint32_t vht_sig_b_mu20_offset : 7, + vht_sig_b_mu40_offset : 7, + vht_sig_b_mu80_offset : 7, + vht_sig_b_mu160_offset : 7, + reserved_3a : 4; + uint32_t he_sig_b1_mu_offset : 7, + he_sig_b2_mu_offset : 7, + he_sig_b2_ofdma_offset : 7, + first_generic_eht_sig_offset : 7, + multiple_generic_eht_sig_included : 1, + reserved_4a : 3; + uint32_t common_user_info_offset : 7, + first_debug_info_offset : 8, + multiple_debug_info_included : 1, + first_other_receive_info_offset : 8, + multiple_other_receive_info_included : 1, + reserved_5a : 7; + uint32_t data_done_offset : 8, + generated_cbf_details_offset : 8, + pkt_end_part1_offset : 8, + location_offset : 8; + uint32_t az_integrity_data_offset : 8, + pkt_end_offset : 8, + abort_request_ack_offset : 8, + reserved_7a : 8; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; +#else + uint32_t repeat_l_sig_a_offset : 6, + vht_sig_a_offset : 6, + ht_sig_offset : 6, + l_sig_b_offset : 6, + l_sig_a_offset : 6, + rssi_legacy_offset : 2; + uint32_t reserved_1a : 1, + rssi_ht_offset : 7, + generic_u_sig_offset : 6, + he_sig_a_mu_ul_offset : 6, + he_sig_a_mu_dl_offset : 6, + he_sig_a_su_offset : 6; + uint32_t reserved_2a : 4, + vht_sig_b_su160_offset : 7, + vht_sig_b_su80_offset : 7, + vht_sig_b_su40_offset : 7, + vht_sig_b_su20_offset : 7; + uint32_t reserved_3a : 4, + vht_sig_b_mu160_offset : 7, + vht_sig_b_mu80_offset : 7, + vht_sig_b_mu40_offset : 7, + vht_sig_b_mu20_offset : 7; + uint32_t reserved_4a : 3, + multiple_generic_eht_sig_included : 1, + first_generic_eht_sig_offset : 7, + he_sig_b2_ofdma_offset : 7, + he_sig_b2_mu_offset : 7, + he_sig_b1_mu_offset : 7; + uint32_t reserved_5a : 7, + multiple_other_receive_info_included : 1, + first_other_receive_info_offset : 8, + multiple_debug_info_included : 1, + first_debug_info_offset : 8, + common_user_info_offset : 7; + uint32_t location_offset : 8, + pkt_end_part1_offset : 8, + generated_cbf_details_offset : 8, + data_done_offset : 8; + uint32_t reserved_7a : 8, + abort_request_ack_offset : 8, + pkt_end_offset : 8, + az_integrity_data_offset : 8; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; +#endif +}; + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MSB 1 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MASK 0x00000003 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_LSB 2 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MASK 0x000000fc + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_LSB 8 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MASK 0x00003f00 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MSB 19 +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MASK 0x000fc000 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_LSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MSB 25 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MASK 0x03f00000 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_LSB 26 +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MASK 0xfc000000 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MSB 5 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MASK 0x0000003f + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_LSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MSB 11 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc0 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_LSB 12 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MSB 17 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f000 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_LSB 18 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MASK 0x00fc0000 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MSB 30 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MASK 0x7f000000 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_LSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MASK 0x80000000 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MASK 0x0000007f + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MASK 0x00003f80 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MASK 0x001fc000 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_LSB 21 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MSB 27 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MASK 0x0fe00000 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_LSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MASK 0xf0000000 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f80 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc000 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_LSB 21 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MSB 27 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe00000 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_LSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MASK 0xf0000000 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MASK 0x0000007f + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MASK 0x00003f80 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MASK 0x001fc000 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x0fe00000 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x10000000 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_LSB 29 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MASK 0xe0000000 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MASK 0x0000007f + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f80 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x00008000 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 16 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff0000 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x01000000 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_LSB 25 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MASK 0xfe000000 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MASK 0x000000ff + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_LSB 8 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MASK 0x0000ff00 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_LSB 16 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MASK 0x00ff0000 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MASK 0xff000000 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_OFFSET 0x0000001c +#define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_MSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_MASK 0x000000ff + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_OFFSET 0x0000001c +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_LSB 8 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MASK 0x0000ff00 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000001c +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_LSB 16 +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff0000 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_OFFSET 0x0000001c +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MASK 0xff000000 + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_OFFSET 0x00000020 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MASK 0xffffffff + + + + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_OFFSET 0x00000024 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MASK 0xffffffff + + + +#endif diff --git a/hw/qcn9224/rxpt_classify_info.h b/hw/qcn9224/rxpt_classify_info.h new file mode 100644 index 000000000000..333ec3a50f7e --- /dev/null +++ b/hw/qcn9224/rxpt_classify_info.h @@ -0,0 +1,182 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _RXPT_CLASSIFY_INFO_H_ +#define _RXPT_CLASSIFY_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1 + + +struct rxpt_classify_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_destination_indication : 5, + lmac_peer_id_msb : 2, + use_flow_id_toeplitz_clfy : 1, + pkt_selection_fp_ucast_data : 1, + pkt_selection_fp_mcast_data : 1, + pkt_selection_fp_1000 : 1, + rxdma0_source_ring_selection : 3, + rxdma0_destination_ring_selection : 3, + mcast_echo_drop_enable : 1, + wds_learning_detect_en : 1, + intrabss_check_en : 1, + use_ppe : 1, + ppe_routing_enable : 1, + reserved_0b : 10; +#else + uint32_t reserved_0b : 10, + ppe_routing_enable : 1, + use_ppe : 1, + intrabss_check_en : 1, + wds_learning_detect_en : 1, + mcast_echo_drop_enable : 1, + rxdma0_destination_ring_selection : 3, + rxdma0_source_ring_selection : 3, + pkt_selection_fp_1000 : 1, + pkt_selection_fp_mcast_data : 1, + pkt_selection_fp_ucast_data : 1, + use_flow_id_toeplitz_clfy : 1, + lmac_peer_id_msb : 2, + reo_destination_indication : 5; +#endif +}; + + + + +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_LSB 0 +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MSB 4 +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f + + + + +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_LSB 5 +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MSB 6 +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MASK 0x00000060 + + + + +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + + + + +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MSB 8 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + + + + +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MSB 9 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + + + + +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_LSB 10 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MSB 10 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MASK 0x00000400 + + + + +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MSB 13 +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 + + + + +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 + + + + +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_LSB 17 +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MSB 17 +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 + + + + +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_LSB 18 +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MSB 18 +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MASK 0x00040000 + + + + +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_LSB 19 +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MSB 19 +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MASK 0x00080000 + + + + +#define RXPT_CLASSIFY_INFO_USE_PPE_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_USE_PPE_LSB 20 +#define RXPT_CLASSIFY_INFO_USE_PPE_MSB 20 +#define RXPT_CLASSIFY_INFO_USE_PPE_MASK 0x00100000 + + + + +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_LSB 21 +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MSB 21 +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MASK 0x00200000 + + + + +#define RXPT_CLASSIFY_INFO_RESERVED_0B_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_RESERVED_0B_LSB 22 +#define RXPT_CLASSIFY_INFO_RESERVED_0B_MSB 31 +#define RXPT_CLASSIFY_INFO_RESERVED_0B_MASK 0xffc00000 + + + +#endif diff --git a/hw/qcn9224/seq_hwio.h b/hw/qcn9224/seq_hwio.h new file mode 100644 index 000000000000..c060acdcd43b --- /dev/null +++ b/hw/qcn9224/seq_hwio.h @@ -0,0 +1,90 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef __SEQ_H__ +#define __SEQ_H__ + +#include "HALhwio.h" + + + + +#define SEQ_INH(base, regtype, reg) \ + SEQ_##regtype##_INH(base, reg) + + +#define SEQ_INMH(base, regtype, reg, mask) \ + SEQ_##regtype##_INMH(base, reg, mask) + + + +#define SEQ_INFH(base, regtype, reg, fld) \ + (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld)) + + + +#define SEQ_OUTH(base, regtype, reg, val) \ + SEQ_##regtype##_OUTH(base, reg, val) + + +#define SEQ_OUTMH(base, regtype, reg, mask, val) \ + SEQ_##regtype##_OUTMH(base, reg, mask, val) + + + +#define SEQ_OUTFH(base, regtype, reg, fld, val) \ + SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld)) + + + + + + +typedef enum { + SEC, + MS, + US, + NS +} SEQ_TimeUnit; + +extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit); + + + +extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt); + +#endif + + + + + + + + + + + + + + + + + + + diff --git a/hw/qcn9224/sw_monitor_ring.h b/hw/qcn9224/sw_monitor_ring.h new file mode 100644 index 000000000000..9aefc7ae27b6 --- /dev/null +++ b/hw/qcn9224/sw_monitor_ring.h @@ -0,0 +1,330 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _SW_MONITOR_RING_H_ +#define _SW_MONITOR_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#include "rx_mpdu_details.h" +#define NUM_OF_DWORDS_SW_MONITOR_RING 8 + + +struct sw_monitor_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_mpdu_details reo_level_mpdu_frame_info; + struct buffer_addr_info status_buff_addr_info; + uint32_t rxdma_push_reason : 2, + rxdma_error_code : 5, + mpdu_fragment_number : 4, + frameless_bar : 1, + status_buf_count : 4, + end_of_ppdu : 1, + reserved_6a : 15; + uint32_t phy_ppdu_id : 16, + reserved_7a : 4, + ring_id : 8, + looping_count : 4; +#else + struct rx_mpdu_details reo_level_mpdu_frame_info; + struct buffer_addr_info status_buff_addr_info; + uint32_t reserved_6a : 15, + end_of_ppdu : 1, + status_buf_count : 4, + frameless_bar : 1, + mpdu_fragment_number : 4, + rxdma_error_code : 5, + rxdma_push_reason : 2; + uint32_t looping_count : 4, + ring_id : 8, + reserved_7a : 4, + phy_ppdu_id : 16; +#endif +}; + + + + + + + + + + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + + + + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + + + + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + + + + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + + + + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + + + + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + + + + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + + + + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + + + + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + + + + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + + + + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + + + + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + + + + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + + + + + + + +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + +#define SW_MONITOR_RING_RXDMA_PUSH_REASON_OFFSET 0x00000018 +#define SW_MONITOR_RING_RXDMA_PUSH_REASON_LSB 0 +#define SW_MONITOR_RING_RXDMA_PUSH_REASON_MSB 1 +#define SW_MONITOR_RING_RXDMA_PUSH_REASON_MASK 0x00000003 + + + + +#define SW_MONITOR_RING_RXDMA_ERROR_CODE_OFFSET 0x00000018 +#define SW_MONITOR_RING_RXDMA_ERROR_CODE_LSB 2 +#define SW_MONITOR_RING_RXDMA_ERROR_CODE_MSB 6 +#define SW_MONITOR_RING_RXDMA_ERROR_CODE_MASK 0x0000007c + + + + +#define SW_MONITOR_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018 +#define SW_MONITOR_RING_MPDU_FRAGMENT_NUMBER_LSB 7 +#define SW_MONITOR_RING_MPDU_FRAGMENT_NUMBER_MSB 10 +#define SW_MONITOR_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 + + + + +#define SW_MONITOR_RING_FRAMELESS_BAR_OFFSET 0x00000018 +#define SW_MONITOR_RING_FRAMELESS_BAR_LSB 11 +#define SW_MONITOR_RING_FRAMELESS_BAR_MSB 11 +#define SW_MONITOR_RING_FRAMELESS_BAR_MASK 0x00000800 + + + + +#define SW_MONITOR_RING_STATUS_BUF_COUNT_OFFSET 0x00000018 +#define SW_MONITOR_RING_STATUS_BUF_COUNT_LSB 12 +#define SW_MONITOR_RING_STATUS_BUF_COUNT_MSB 15 +#define SW_MONITOR_RING_STATUS_BUF_COUNT_MASK 0x0000f000 + + + + +#define SW_MONITOR_RING_END_OF_PPDU_OFFSET 0x00000018 +#define SW_MONITOR_RING_END_OF_PPDU_LSB 16 +#define SW_MONITOR_RING_END_OF_PPDU_MSB 16 +#define SW_MONITOR_RING_END_OF_PPDU_MASK 0x00010000 + + + + +#define SW_MONITOR_RING_RESERVED_6A_OFFSET 0x00000018 +#define SW_MONITOR_RING_RESERVED_6A_LSB 17 +#define SW_MONITOR_RING_RESERVED_6A_MSB 31 +#define SW_MONITOR_RING_RESERVED_6A_MASK 0xfffe0000 + + + + +#define SW_MONITOR_RING_PHY_PPDU_ID_OFFSET 0x0000001c +#define SW_MONITOR_RING_PHY_PPDU_ID_LSB 0 +#define SW_MONITOR_RING_PHY_PPDU_ID_MSB 15 +#define SW_MONITOR_RING_PHY_PPDU_ID_MASK 0x0000ffff + + + + +#define SW_MONITOR_RING_RESERVED_7A_OFFSET 0x0000001c +#define SW_MONITOR_RING_RESERVED_7A_LSB 16 +#define SW_MONITOR_RING_RESERVED_7A_MSB 19 +#define SW_MONITOR_RING_RESERVED_7A_MASK 0x000f0000 + + + + +#define SW_MONITOR_RING_RING_ID_OFFSET 0x0000001c +#define SW_MONITOR_RING_RING_ID_LSB 20 +#define SW_MONITOR_RING_RING_ID_MSB 27 +#define SW_MONITOR_RING_RING_ID_MASK 0x0ff00000 + + + + +#define SW_MONITOR_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define SW_MONITOR_RING_LOOPING_COUNT_LSB 28 +#define SW_MONITOR_RING_LOOPING_COUNT_MSB 31 +#define SW_MONITOR_RING_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif diff --git a/hw/qcn9224/tcl_data_cmd.h b/hw/qcn9224/tcl_data_cmd.h new file mode 100644 index 000000000000..f524e601aac8 --- /dev/null +++ b/hw/qcn9224/tcl_data_cmd.h @@ -0,0 +1,420 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _TCL_DATA_CMD_H_ +#define _TCL_DATA_CMD_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_TCL_DATA_CMD 8 + + +struct tcl_data_cmd { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buf_addr_info; + uint32_t tcl_cmd_type : 1, + buf_or_ext_desc_type : 1, + bank_id : 6, + tx_notify_frame : 3, + header_length_read_sel : 1, + buffer_timestamp : 19, + buffer_timestamp_valid : 1; + uint32_t reserved_3a : 16, + tcl_cmd_number : 16; + uint32_t data_length : 16, + ipv4_checksum_en : 1, + udp_over_ipv4_checksum_en : 1, + udp_over_ipv6_checksum_en : 1, + tcp_over_ipv4_checksum_en : 1, + tcp_over_ipv6_checksum_en : 1, + to_fw : 1, + reserved_4a : 1, + packet_offset : 9; + uint32_t hlos_tid_overwrite : 1, + flow_override_enable : 1, + who_classify_info_sel : 2, + hlos_tid : 4, + flow_override : 1, + pmac_id : 2, + msdu_color : 2, + reserved_5a : 11, + vdev_id : 8; + uint32_t search_index : 20, + cache_set_num : 4, + index_lookup_override : 1, + reserved_6a : 7; + uint32_t reserved_7a : 20, + ring_id : 8, + looping_count : 4; +#else + struct buffer_addr_info buf_addr_info; + uint32_t buffer_timestamp_valid : 1, + buffer_timestamp : 19, + header_length_read_sel : 1, + tx_notify_frame : 3, + bank_id : 6, + buf_or_ext_desc_type : 1, + tcl_cmd_type : 1; + uint32_t tcl_cmd_number : 16, + reserved_3a : 16; + uint32_t packet_offset : 9, + reserved_4a : 1, + to_fw : 1, + tcp_over_ipv6_checksum_en : 1, + tcp_over_ipv4_checksum_en : 1, + udp_over_ipv6_checksum_en : 1, + udp_over_ipv4_checksum_en : 1, + ipv4_checksum_en : 1, + data_length : 16; + uint32_t vdev_id : 8, + reserved_5a : 11, + msdu_color : 2, + pmac_id : 2, + flow_override : 1, + hlos_tid : 4, + who_classify_info_sel : 2, + flow_override_enable : 1, + hlos_tid_overwrite : 1; + uint32_t reserved_6a : 7, + index_lookup_override : 1, + cache_set_num : 4, + search_index : 20; + uint32_t looping_count : 4, + ring_id : 8, + reserved_7a : 20; +#endif +}; + + + + + + + +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + +#define TCL_DATA_CMD_TCL_CMD_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_TCL_CMD_TYPE_LSB 0 +#define TCL_DATA_CMD_TCL_CMD_TYPE_MSB 0 +#define TCL_DATA_CMD_TCL_CMD_TYPE_MASK 0x00000001 + + + + +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 1 +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MSB 1 +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 0x00000002 + + + + +#define TCL_DATA_CMD_BANK_ID_OFFSET 0x00000008 +#define TCL_DATA_CMD_BANK_ID_LSB 2 +#define TCL_DATA_CMD_BANK_ID_MSB 7 +#define TCL_DATA_CMD_BANK_ID_MASK 0x000000fc + + + + +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_OFFSET 0x00000008 +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_LSB 8 +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MSB 10 +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MASK 0x00000700 + + + + +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_OFFSET 0x00000008 +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_LSB 11 +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MSB 11 +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MASK 0x00000800 + + + + +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_OFFSET 0x00000008 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_LSB 12 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MSB 30 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MASK 0x7ffff000 + + + + +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000008 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_LSB 31 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MSB 31 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MASK 0x80000000 + + + + +#define TCL_DATA_CMD_RESERVED_3A_OFFSET 0x0000000c +#define TCL_DATA_CMD_RESERVED_3A_LSB 0 +#define TCL_DATA_CMD_RESERVED_3A_MSB 15 +#define TCL_DATA_CMD_RESERVED_3A_MASK 0x0000ffff + + + + +#define TCL_DATA_CMD_TCL_CMD_NUMBER_OFFSET 0x0000000c +#define TCL_DATA_CMD_TCL_CMD_NUMBER_LSB 16 +#define TCL_DATA_CMD_TCL_CMD_NUMBER_MSB 31 +#define TCL_DATA_CMD_TCL_CMD_NUMBER_MASK 0xffff0000 + + + + +#define TCL_DATA_CMD_DATA_LENGTH_OFFSET 0x00000010 +#define TCL_DATA_CMD_DATA_LENGTH_LSB 0 +#define TCL_DATA_CMD_DATA_LENGTH_MSB 15 +#define TCL_DATA_CMD_DATA_LENGTH_MASK 0x0000ffff + + + + +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_LSB 16 +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MSB 16 +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MASK 0x00010000 + + + + +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_LSB 17 +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MSB 17 +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00020000 + + + + +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_LSB 18 +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MSB 18 +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00040000 + + + + +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_LSB 19 +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MSB 19 +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00080000 + + + + +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_LSB 20 +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MSB 20 +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00100000 + + + + +#define TCL_DATA_CMD_TO_FW_OFFSET 0x00000010 +#define TCL_DATA_CMD_TO_FW_LSB 21 +#define TCL_DATA_CMD_TO_FW_MSB 21 +#define TCL_DATA_CMD_TO_FW_MASK 0x00200000 + + + + +#define TCL_DATA_CMD_RESERVED_4A_OFFSET 0x00000010 +#define TCL_DATA_CMD_RESERVED_4A_LSB 22 +#define TCL_DATA_CMD_RESERVED_4A_MSB 22 +#define TCL_DATA_CMD_RESERVED_4A_MASK 0x00400000 + + + + +#define TCL_DATA_CMD_PACKET_OFFSET_OFFSET 0x00000010 +#define TCL_DATA_CMD_PACKET_OFFSET_LSB 23 +#define TCL_DATA_CMD_PACKET_OFFSET_MSB 31 +#define TCL_DATA_CMD_PACKET_OFFSET_MASK 0xff800000 + + + + +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_OFFSET 0x00000014 +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_LSB 0 +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MSB 0 +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MASK 0x00000001 + + + + +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_OFFSET 0x00000014 +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_LSB 1 +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MSB 1 +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MASK 0x00000002 + + + + +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_OFFSET 0x00000014 +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_LSB 2 +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MSB 3 +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MASK 0x0000000c + + + + +#define TCL_DATA_CMD_HLOS_TID_OFFSET 0x00000014 +#define TCL_DATA_CMD_HLOS_TID_LSB 4 +#define TCL_DATA_CMD_HLOS_TID_MSB 7 +#define TCL_DATA_CMD_HLOS_TID_MASK 0x000000f0 + + + + +#define TCL_DATA_CMD_FLOW_OVERRIDE_OFFSET 0x00000014 +#define TCL_DATA_CMD_FLOW_OVERRIDE_LSB 8 +#define TCL_DATA_CMD_FLOW_OVERRIDE_MSB 8 +#define TCL_DATA_CMD_FLOW_OVERRIDE_MASK 0x00000100 + + + + +#define TCL_DATA_CMD_PMAC_ID_OFFSET 0x00000014 +#define TCL_DATA_CMD_PMAC_ID_LSB 9 +#define TCL_DATA_CMD_PMAC_ID_MSB 10 +#define TCL_DATA_CMD_PMAC_ID_MASK 0x00000600 + + + + +#define TCL_DATA_CMD_MSDU_COLOR_OFFSET 0x00000014 +#define TCL_DATA_CMD_MSDU_COLOR_LSB 11 +#define TCL_DATA_CMD_MSDU_COLOR_MSB 12 +#define TCL_DATA_CMD_MSDU_COLOR_MASK 0x00001800 + + + + +#define TCL_DATA_CMD_RESERVED_5A_OFFSET 0x00000014 +#define TCL_DATA_CMD_RESERVED_5A_LSB 13 +#define TCL_DATA_CMD_RESERVED_5A_MSB 23 +#define TCL_DATA_CMD_RESERVED_5A_MASK 0x00ffe000 + + + + +#define TCL_DATA_CMD_VDEV_ID_OFFSET 0x00000014 +#define TCL_DATA_CMD_VDEV_ID_LSB 24 +#define TCL_DATA_CMD_VDEV_ID_MSB 31 +#define TCL_DATA_CMD_VDEV_ID_MASK 0xff000000 + + + + +#define TCL_DATA_CMD_SEARCH_INDEX_OFFSET 0x00000018 +#define TCL_DATA_CMD_SEARCH_INDEX_LSB 0 +#define TCL_DATA_CMD_SEARCH_INDEX_MSB 19 +#define TCL_DATA_CMD_SEARCH_INDEX_MASK 0x000fffff + + + + +#define TCL_DATA_CMD_CACHE_SET_NUM_OFFSET 0x00000018 +#define TCL_DATA_CMD_CACHE_SET_NUM_LSB 20 +#define TCL_DATA_CMD_CACHE_SET_NUM_MSB 23 +#define TCL_DATA_CMD_CACHE_SET_NUM_MASK 0x00f00000 + + + + +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_OFFSET 0x00000018 +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_LSB 24 +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MSB 24 +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MASK 0x01000000 + + + + +#define TCL_DATA_CMD_RESERVED_6A_OFFSET 0x00000018 +#define TCL_DATA_CMD_RESERVED_6A_LSB 25 +#define TCL_DATA_CMD_RESERVED_6A_MSB 31 +#define TCL_DATA_CMD_RESERVED_6A_MASK 0xfe000000 + + + + +#define TCL_DATA_CMD_RESERVED_7A_OFFSET 0x0000001c +#define TCL_DATA_CMD_RESERVED_7A_LSB 0 +#define TCL_DATA_CMD_RESERVED_7A_MSB 19 +#define TCL_DATA_CMD_RESERVED_7A_MASK 0x000fffff + + + + +#define TCL_DATA_CMD_RING_ID_OFFSET 0x0000001c +#define TCL_DATA_CMD_RING_ID_LSB 20 +#define TCL_DATA_CMD_RING_ID_MSB 27 +#define TCL_DATA_CMD_RING_ID_MASK 0x0ff00000 + + + + +#define TCL_DATA_CMD_LOOPING_COUNT_OFFSET 0x0000001c +#define TCL_DATA_CMD_LOOPING_COUNT_LSB 28 +#define TCL_DATA_CMD_LOOPING_COUNT_MSB 31 +#define TCL_DATA_CMD_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif diff --git a/hw/qcn9224/tcl_entrance_from_ppe_ring.h b/hw/qcn9224/tcl_entrance_from_ppe_ring.h new file mode 100644 index 000000000000..ed6445507c57 --- /dev/null +++ b/hw/qcn9224/tcl_entrance_from_ppe_ring.h @@ -0,0 +1,382 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _TCL_ENTRANCE_FROM_PPE_RING_H_ +#define _TCL_ENTRANCE_FROM_PPE_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TCL_ENTRANCE_FROM_PPE_RING 8 + + +struct tcl_entrance_from_ppe_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_addr_lo : 32; + uint32_t buffer_addr_hi : 8, + drop_prec : 2, + fake_mac_header : 1, + known_ind : 1, + cpu_code_valid : 1, + tunnel_term_ind : 1, + tunnel_type : 1, + wifi_qos_flag : 1, + service_code : 9, + reserved_1b : 1, + int_pri : 4, + more : 1, + reserved_1a : 1; + uint32_t opaque_lo : 32; + uint32_t opaque_hi : 32; + uint32_t src_info : 16, + dst_info : 16; + uint32_t data_length : 18, + pool_id : 6, + wifi_qos : 8; + uint32_t data_offset : 12, + l4_csum_status : 1, + l3_csum_status : 1, + hash_flag : 2, + hash_value : 16; + uint32_t dscp : 8, + valid_toggle : 1, + pppoe_flag : 1, + svlan_flag : 1, + cvlan_flag : 1, + pid : 4, + l3_offset : 8, + l4_offset : 8; +#else + uint32_t buffer_addr_lo : 32; + uint32_t reserved_1a : 1, + more : 1, + int_pri : 4, + reserved_1b : 1, + service_code : 9, + wifi_qos_flag : 1, + tunnel_type : 1, + tunnel_term_ind : 1, + cpu_code_valid : 1, + known_ind : 1, + fake_mac_header : 1, + drop_prec : 2, + buffer_addr_hi : 8; + uint32_t opaque_lo : 32; + uint32_t opaque_hi : 32; + uint32_t dst_info : 16, + src_info : 16; + uint32_t wifi_qos : 8, + pool_id : 6, + data_length : 18; + uint32_t hash_value : 16, + hash_flag : 2, + l3_csum_status : 1, + l4_csum_status : 1, + data_offset : 12; + uint32_t l4_offset : 8, + l3_offset : 8, + pid : 4, + cvlan_flag : 1, + svlan_flag : 1, + pppoe_flag : 1, + valid_toggle : 1, + dscp : 8; +#endif +}; + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_OFFSET 0x00000000 +#define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_LSB 0 +#define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_MSB 31 +#define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_MASK 0xffffffff + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_LSB 0 +#define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_MSB 7 +#define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_MASK 0x000000ff + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_LSB 8 +#define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_MSB 9 +#define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_MASK 0x00000300 + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_LSB 10 +#define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_MSB 10 +#define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_MASK 0x00000400 + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_LSB 11 +#define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_MSB 11 +#define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_MASK 0x00000800 + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_LSB 12 +#define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_MSB 12 +#define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_MASK 0x00001000 + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_LSB 13 +#define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_MSB 13 +#define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_MASK 0x00002000 + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_LSB 14 +#define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_MSB 14 +#define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_MASK 0x00004000 + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_LSB 15 +#define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_MSB 15 +#define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_MASK 0x00008000 + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_LSB 16 +#define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_MSB 24 +#define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_MASK 0x01ff0000 + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_LSB 25 +#define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_MSB 25 +#define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_MASK 0x02000000 + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_LSB 26 +#define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_MSB 29 +#define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_MASK 0x3c000000 + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_MORE_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_MORE_LSB 30 +#define TCL_ENTRANCE_FROM_PPE_RING_MORE_MSB 30 +#define TCL_ENTRANCE_FROM_PPE_RING_MORE_MASK 0x40000000 + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_LSB 31 +#define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_MSB 31 +#define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_MASK 0x80000000 + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_OFFSET 0x00000008 +#define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_LSB 0 +#define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_MSB 31 +#define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_MASK 0xffffffff + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_OFFSET 0x0000000c +#define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_LSB 0 +#define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_MSB 31 +#define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_MASK 0xffffffff + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_OFFSET 0x00000010 +#define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_LSB 0 +#define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_MSB 15 +#define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_MASK 0x0000ffff + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_OFFSET 0x00000010 +#define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_LSB 16 +#define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_MSB 31 +#define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_MASK 0xffff0000 + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_OFFSET 0x00000014 +#define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_LSB 0 +#define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_MSB 17 +#define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_MASK 0x0003ffff + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_OFFSET 0x00000014 +#define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_LSB 18 +#define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_MSB 23 +#define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_MASK 0x00fc0000 + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_OFFSET 0x00000014 +#define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_LSB 24 +#define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_MSB 31 +#define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_MASK 0xff000000 + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_OFFSET 0x00000018 +#define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_LSB 0 +#define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_MSB 11 +#define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_MASK 0x00000fff + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_OFFSET 0x00000018 +#define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_LSB 12 +#define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_MSB 12 +#define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_MASK 0x00001000 + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_OFFSET 0x00000018 +#define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_LSB 13 +#define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_MSB 13 +#define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_MASK 0x00002000 + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_OFFSET 0x00000018 +#define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_LSB 14 +#define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_MSB 15 +#define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_MASK 0x0000c000 + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_OFFSET 0x00000018 +#define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_LSB 16 +#define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_MSB 31 +#define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_MASK 0xffff0000 + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_DSCP_OFFSET 0x0000001c +#define TCL_ENTRANCE_FROM_PPE_RING_DSCP_LSB 0 +#define TCL_ENTRANCE_FROM_PPE_RING_DSCP_MSB 7 +#define TCL_ENTRANCE_FROM_PPE_RING_DSCP_MASK 0x000000ff + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_OFFSET 0x0000001c +#define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_LSB 8 +#define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_MSB 8 +#define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_MASK 0x00000100 + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_OFFSET 0x0000001c +#define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_LSB 9 +#define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_MSB 9 +#define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_MASK 0x00000200 + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_OFFSET 0x0000001c +#define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_LSB 10 +#define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_MSB 10 +#define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_MASK 0x00000400 + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_OFFSET 0x0000001c +#define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_LSB 11 +#define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_MSB 11 +#define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_MASK 0x00000800 + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_PID_OFFSET 0x0000001c +#define TCL_ENTRANCE_FROM_PPE_RING_PID_LSB 12 +#define TCL_ENTRANCE_FROM_PPE_RING_PID_MSB 15 +#define TCL_ENTRANCE_FROM_PPE_RING_PID_MASK 0x0000f000 + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_OFFSET 0x0000001c +#define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_LSB 16 +#define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_MSB 23 +#define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_MASK 0x00ff0000 + + + + +#define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_OFFSET 0x0000001c +#define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_LSB 24 +#define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_MSB 31 +#define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_MASK 0xff000000 + + + +#endif diff --git a/hw/qcn9224/tcl_gse_cmd.h b/hw/qcn9224/tcl_gse_cmd.h new file mode 100644 index 000000000000..def5d977e129 --- /dev/null +++ b/hw/qcn9224/tcl_gse_cmd.h @@ -0,0 +1,222 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _TCL_GSE_CMD_H_ +#define _TCL_GSE_CMD_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TCL_GSE_CMD 8 + + +struct tcl_gse_cmd { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t control_buffer_addr_31_0 : 32; + uint32_t control_buffer_addr_39_32 : 8, + gse_ctrl : 4, + gse_sel : 1, + status_destination_ring_id : 1, + swap : 1, + index_search_en : 1, + cache_set_num : 4, + reserved_1a : 12; + uint32_t tcl_cmd_type : 1, + reserved_2a : 31; + uint32_t cmd_meta_data_31_0 : 32; + uint32_t cmd_meta_data_63_32 : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 20, + ring_id : 8, + looping_count : 4; +#else + uint32_t control_buffer_addr_31_0 : 32; + uint32_t reserved_1a : 12, + cache_set_num : 4, + index_search_en : 1, + swap : 1, + status_destination_ring_id : 1, + gse_sel : 1, + gse_ctrl : 4, + control_buffer_addr_39_32 : 8; + uint32_t reserved_2a : 31, + tcl_cmd_type : 1; + uint32_t cmd_meta_data_31_0 : 32; + uint32_t cmd_meta_data_63_32 : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t looping_count : 4, + ring_id : 8, + reserved_7a : 20; +#endif +}; + + + + +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_LSB 0 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MSB 31 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_LSB 0 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MSB 7 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define TCL_GSE_CMD_GSE_CTRL_OFFSET 0x00000004 +#define TCL_GSE_CMD_GSE_CTRL_LSB 8 +#define TCL_GSE_CMD_GSE_CTRL_MSB 11 +#define TCL_GSE_CMD_GSE_CTRL_MASK 0x00000f00 + + + + +#define TCL_GSE_CMD_GSE_SEL_OFFSET 0x00000004 +#define TCL_GSE_CMD_GSE_SEL_LSB 12 +#define TCL_GSE_CMD_GSE_SEL_MSB 12 +#define TCL_GSE_CMD_GSE_SEL_MASK 0x00001000 + + + + +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004 +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_LSB 13 +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MSB 13 +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MASK 0x00002000 + + + + +#define TCL_GSE_CMD_SWAP_OFFSET 0x00000004 +#define TCL_GSE_CMD_SWAP_LSB 14 +#define TCL_GSE_CMD_SWAP_MSB 14 +#define TCL_GSE_CMD_SWAP_MASK 0x00004000 + + + + +#define TCL_GSE_CMD_INDEX_SEARCH_EN_OFFSET 0x00000004 +#define TCL_GSE_CMD_INDEX_SEARCH_EN_LSB 15 +#define TCL_GSE_CMD_INDEX_SEARCH_EN_MSB 15 +#define TCL_GSE_CMD_INDEX_SEARCH_EN_MASK 0x00008000 + + + + +#define TCL_GSE_CMD_CACHE_SET_NUM_OFFSET 0x00000004 +#define TCL_GSE_CMD_CACHE_SET_NUM_LSB 16 +#define TCL_GSE_CMD_CACHE_SET_NUM_MSB 19 +#define TCL_GSE_CMD_CACHE_SET_NUM_MASK 0x000f0000 + + + + +#define TCL_GSE_CMD_RESERVED_1A_OFFSET 0x00000004 +#define TCL_GSE_CMD_RESERVED_1A_LSB 20 +#define TCL_GSE_CMD_RESERVED_1A_MSB 31 +#define TCL_GSE_CMD_RESERVED_1A_MASK 0xfff00000 + + + + +#define TCL_GSE_CMD_TCL_CMD_TYPE_OFFSET 0x00000008 +#define TCL_GSE_CMD_TCL_CMD_TYPE_LSB 0 +#define TCL_GSE_CMD_TCL_CMD_TYPE_MSB 0 +#define TCL_GSE_CMD_TCL_CMD_TYPE_MASK 0x00000001 + + + + +#define TCL_GSE_CMD_RESERVED_2A_OFFSET 0x00000008 +#define TCL_GSE_CMD_RESERVED_2A_LSB 1 +#define TCL_GSE_CMD_RESERVED_2A_MSB 31 +#define TCL_GSE_CMD_RESERVED_2A_MASK 0xfffffffe + + + + +#define TCL_GSE_CMD_CMD_META_DATA_31_0_OFFSET 0x0000000c +#define TCL_GSE_CMD_CMD_META_DATA_31_0_LSB 0 +#define TCL_GSE_CMD_CMD_META_DATA_31_0_MSB 31 +#define TCL_GSE_CMD_CMD_META_DATA_31_0_MASK 0xffffffff + + + + +#define TCL_GSE_CMD_CMD_META_DATA_63_32_OFFSET 0x00000010 +#define TCL_GSE_CMD_CMD_META_DATA_63_32_LSB 0 +#define TCL_GSE_CMD_CMD_META_DATA_63_32_MSB 31 +#define TCL_GSE_CMD_CMD_META_DATA_63_32_MASK 0xffffffff + + + + +#define TCL_GSE_CMD_RESERVED_5A_OFFSET 0x00000014 +#define TCL_GSE_CMD_RESERVED_5A_LSB 0 +#define TCL_GSE_CMD_RESERVED_5A_MSB 31 +#define TCL_GSE_CMD_RESERVED_5A_MASK 0xffffffff + + + + +#define TCL_GSE_CMD_RESERVED_6A_OFFSET 0x00000018 +#define TCL_GSE_CMD_RESERVED_6A_LSB 0 +#define TCL_GSE_CMD_RESERVED_6A_MSB 31 +#define TCL_GSE_CMD_RESERVED_6A_MASK 0xffffffff + + + + +#define TCL_GSE_CMD_RESERVED_7A_OFFSET 0x0000001c +#define TCL_GSE_CMD_RESERVED_7A_LSB 0 +#define TCL_GSE_CMD_RESERVED_7A_MSB 19 +#define TCL_GSE_CMD_RESERVED_7A_MASK 0x000fffff + + + + +#define TCL_GSE_CMD_RING_ID_OFFSET 0x0000001c +#define TCL_GSE_CMD_RING_ID_LSB 20 +#define TCL_GSE_CMD_RING_ID_MSB 27 +#define TCL_GSE_CMD_RING_ID_MASK 0x0ff00000 + + + + +#define TCL_GSE_CMD_LOOPING_COUNT_OFFSET 0x0000001c +#define TCL_GSE_CMD_LOOPING_COUNT_LSB 28 +#define TCL_GSE_CMD_LOOPING_COUNT_MSB 31 +#define TCL_GSE_CMD_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif diff --git a/hw/qcn9224/tcl_status_ring.h b/hw/qcn9224/tcl_status_ring.h new file mode 100644 index 000000000000..b2eea3a04ee6 --- /dev/null +++ b/hw/qcn9224/tcl_status_ring.h @@ -0,0 +1,202 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _TCL_STATUS_RING_H_ +#define _TCL_STATUS_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TCL_STATUS_RING 8 + + +struct tcl_status_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t gse_ctrl : 4, + ase_fse_sel : 1, + cache_op_res : 2, + index_search_en : 1, + msdu_cnt_n : 24; + uint32_t msdu_byte_cnt_n : 32; + uint32_t msdu_timestmp_n : 32; + uint32_t cmd_meta_data_31_0 : 32; + uint32_t cmd_meta_data_63_32 : 32; + uint32_t hash_indx_val : 20, + cache_set_num : 4, + reserved_5a : 8; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 20, + ring_id : 8, + looping_count : 4; +#else + uint32_t msdu_cnt_n : 24, + index_search_en : 1, + cache_op_res : 2, + ase_fse_sel : 1, + gse_ctrl : 4; + uint32_t msdu_byte_cnt_n : 32; + uint32_t msdu_timestmp_n : 32; + uint32_t cmd_meta_data_31_0 : 32; + uint32_t cmd_meta_data_63_32 : 32; + uint32_t reserved_5a : 8, + cache_set_num : 4, + hash_indx_val : 20; + uint32_t reserved_6a : 32; + uint32_t looping_count : 4, + ring_id : 8, + reserved_7a : 20; +#endif +}; + + + + +#define TCL_STATUS_RING_GSE_CTRL_OFFSET 0x00000000 +#define TCL_STATUS_RING_GSE_CTRL_LSB 0 +#define TCL_STATUS_RING_GSE_CTRL_MSB 3 +#define TCL_STATUS_RING_GSE_CTRL_MASK 0x0000000f + + + + +#define TCL_STATUS_RING_ASE_FSE_SEL_OFFSET 0x00000000 +#define TCL_STATUS_RING_ASE_FSE_SEL_LSB 4 +#define TCL_STATUS_RING_ASE_FSE_SEL_MSB 4 +#define TCL_STATUS_RING_ASE_FSE_SEL_MASK 0x00000010 + + + + +#define TCL_STATUS_RING_CACHE_OP_RES_OFFSET 0x00000000 +#define TCL_STATUS_RING_CACHE_OP_RES_LSB 5 +#define TCL_STATUS_RING_CACHE_OP_RES_MSB 6 +#define TCL_STATUS_RING_CACHE_OP_RES_MASK 0x00000060 + + + + +#define TCL_STATUS_RING_INDEX_SEARCH_EN_OFFSET 0x00000000 +#define TCL_STATUS_RING_INDEX_SEARCH_EN_LSB 7 +#define TCL_STATUS_RING_INDEX_SEARCH_EN_MSB 7 +#define TCL_STATUS_RING_INDEX_SEARCH_EN_MASK 0x00000080 + + + + +#define TCL_STATUS_RING_MSDU_CNT_N_OFFSET 0x00000000 +#define TCL_STATUS_RING_MSDU_CNT_N_LSB 8 +#define TCL_STATUS_RING_MSDU_CNT_N_MSB 31 +#define TCL_STATUS_RING_MSDU_CNT_N_MASK 0xffffff00 + + + + +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_OFFSET 0x00000004 +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_LSB 0 +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MSB 31 +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MASK 0xffffffff + + + + +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_OFFSET 0x00000008 +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_LSB 0 +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MSB 31 +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MASK 0xffffffff + + + + +#define TCL_STATUS_RING_CMD_META_DATA_31_0_OFFSET 0x0000000c +#define TCL_STATUS_RING_CMD_META_DATA_31_0_LSB 0 +#define TCL_STATUS_RING_CMD_META_DATA_31_0_MSB 31 +#define TCL_STATUS_RING_CMD_META_DATA_31_0_MASK 0xffffffff + + + + +#define TCL_STATUS_RING_CMD_META_DATA_63_32_OFFSET 0x00000010 +#define TCL_STATUS_RING_CMD_META_DATA_63_32_LSB 0 +#define TCL_STATUS_RING_CMD_META_DATA_63_32_MSB 31 +#define TCL_STATUS_RING_CMD_META_DATA_63_32_MASK 0xffffffff + + + + +#define TCL_STATUS_RING_HASH_INDX_VAL_OFFSET 0x00000014 +#define TCL_STATUS_RING_HASH_INDX_VAL_LSB 0 +#define TCL_STATUS_RING_HASH_INDX_VAL_MSB 19 +#define TCL_STATUS_RING_HASH_INDX_VAL_MASK 0x000fffff + + + + +#define TCL_STATUS_RING_CACHE_SET_NUM_OFFSET 0x00000014 +#define TCL_STATUS_RING_CACHE_SET_NUM_LSB 20 +#define TCL_STATUS_RING_CACHE_SET_NUM_MSB 23 +#define TCL_STATUS_RING_CACHE_SET_NUM_MASK 0x00f00000 + + + + +#define TCL_STATUS_RING_RESERVED_5A_OFFSET 0x00000014 +#define TCL_STATUS_RING_RESERVED_5A_LSB 24 +#define TCL_STATUS_RING_RESERVED_5A_MSB 31 +#define TCL_STATUS_RING_RESERVED_5A_MASK 0xff000000 + + + + +#define TCL_STATUS_RING_RESERVED_6A_OFFSET 0x00000018 +#define TCL_STATUS_RING_RESERVED_6A_LSB 0 +#define TCL_STATUS_RING_RESERVED_6A_MSB 31 +#define TCL_STATUS_RING_RESERVED_6A_MASK 0xffffffff + + + + +#define TCL_STATUS_RING_RESERVED_7A_OFFSET 0x0000001c +#define TCL_STATUS_RING_RESERVED_7A_LSB 0 +#define TCL_STATUS_RING_RESERVED_7A_MSB 19 +#define TCL_STATUS_RING_RESERVED_7A_MASK 0x000fffff + + + + +#define TCL_STATUS_RING_RING_ID_OFFSET 0x0000001c +#define TCL_STATUS_RING_RING_ID_LSB 20 +#define TCL_STATUS_RING_RING_ID_MSB 27 +#define TCL_STATUS_RING_RING_ID_MASK 0x0ff00000 + + + + +#define TCL_STATUS_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define TCL_STATUS_RING_LOOPING_COUNT_LSB 28 +#define TCL_STATUS_RING_LOOPING_COUNT_MSB 31 +#define TCL_STATUS_RING_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif diff --git a/hw/qcn9224/tlv_hdr.h b/hw/qcn9224/tlv_hdr.h new file mode 100644 index 000000000000..43967c640bb7 --- /dev/null +++ b/hw/qcn9224/tlv_hdr.h @@ -0,0 +1,632 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + +#ifndef _TLV_HDR_H_ +#define _TLV_HDR_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define _TLV_USERID_WIDTH_ 6 +#define _TLV_DATA_WIDTH_ 32 +#define _TLV_TAG_WIDTH_ 9 + +#define _TLV_MRV_EN_LEN_WIDTH_ 9 +#define _TLV_MRV_DIS_LEN_WIDTH_ 12 + +#define _TLV_16_DATA_WIDTH_ 16 +#define _TLV_16_TAG_WIDTH_ 5 +#define _TLV_16_LEN_WIDTH_ 4 +#define _TLV_CTAG_WIDTH_ 5 +#define _TLV_44_DATA_WIDTH_ 44 +#define _TLV_64_DATA_WIDTH_ 64 +#define _TLV_76_DATA_WIDTH_ 64 +#define _TLV_CDATA_WIDTH_ 32 +#define _TLV_CDATA_76_WIDTH_ 64 + +struct tlv_usr_16_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint16_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_16_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t tlv_cflg_reserved : 1, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_reserved : 6; +#else + uint16_t tlv_reserved : 6, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + + + + + + + +struct tlv_mlo_usr_32_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_mlo_32_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 6; +#else + uint32_t tlv_reserved : 6, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_mlo_usr_64_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, +#endif + tlv_reserved : 32; +}; + +struct tlv_mlo_64_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 38; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, + tlv_reserved : 32; +#endif +}; + +struct tlv_mlo_usr_44_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_reserved : 10, + pad_44to64_bit : 22; +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + pad_44to64_bit : 22, + tlv_reserved : 10; +#endif +}; + +struct tlv_mlo_44_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 16, + pad_44to64_bit : 22; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + pad_44to64_bit : 22, + tlv_reserved : 10; +#endif +}; + +struct tlv_mlo_usr_76_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, +#endif + tlv_reserved : 32; + uint64_t pad_64to128_bit : 64; +}; + +struct tlv_mlo_76_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 38; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + tlv_reserved : 32; +#endif + uint64_t pad_64to128_bit : 64; +}; + + + + + + +struct tlv_mac_usr_32_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_mac_32_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 6; +#else + uint32_t tlv_reserved : 6, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_mac_usr_64_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, +#endif + tlv_reserved : 32; +}; + +struct tlv_mac_64_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 38; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, + tlv_reserved : 32; +#endif +}; + +struct tlv_mac_usr_44_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_reserved : 10, + pad_44to64_bit : 22; +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + pad_44to64_bit : 22, + tlv_reserved : 10; +#endif +}; + +struct tlv_mac_44_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 16, + pad_44to64_bit : 22; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + pad_44to64_bit : 22, + tlv_reserved : 10; +#endif +}; + +struct tlv_mac_usr_76_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, +#endif + tlv_reserved : 32; + uint64_t pad_64to128_bit : 64; +}; + +struct tlv_mac_76_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 38; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + tlv_reserved : 32; +#endif + uint64_t pad_64to128_bit : 64; +}; + + + + + +struct tlv_usr_c_44_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata : _TLV_CDATA_WIDTH_, + pad_44to64_bit : 20; +#else + uint64_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1, + pad_44to64_bit : 20, + tlv_cdata_upper_12 : 12; +#endif +}; + +struct tlv_usr_c_76_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata_lower_52 : 52; + uint64_t tlv_cdata_upper_12 : 12, + pad_76to128_bit : 52; +#else + uint64_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1, + tlv_cdata_middle_32 : 32; + uint64_t pad_76to96_bit : 20, + tlv_cdata_upper_12 : 12, + pad_96to128_bit : 32; +#endif +}; + + + + + + + +struct tlv_usr_32_hdr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, +#endif + tlv_reserved : 32; +}; + +struct tlv_32_hdr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 38; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, + tlv_reserved : 32; +#endif +}; + + + + + + + + +struct tlv_mlo_usr_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + +struct tlv_mlo_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + +struct tlv_mac_usr_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + +struct tlv_mac_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + + + + + +struct tlv_usr_c_44_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata_lower_20 : 20; + uint32_t tlv_cdata_upper_12 : 12, + pad_44to64_bit : 20; +#else + uint32_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1; + uint32_t pad_44to64_bit : 20, + tlv_cdata_upper_12 : 12; +#endif +}; + +struct tlv_usr_c_76_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata_lower_20 : 20; + uint32_t tlv_cdata_middle_32 : 32; + uint32_t tlv_cdata_upper_12 : 12, + pad_76to96_bit : 20; + uint32_t pad_96to128_bit : 32; +#else + uint32_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1; + uint32_t tlv_cdata_middle_32 : 32; + uint32_t pad_76to96_bit : 20, + tlv_cdata_upper_12 : 12; + uint32_t pad_96to128_bit : 32; +#endif +}; + + + +#endif diff --git a/hw/qcn9224/tlv_tag_def.h b/hw/qcn9224/tlv_tag_def.h new file mode 100644 index 000000000000..92cb997d8ebf --- /dev/null +++ b/hw/qcn9224/tlv_tag_def.h @@ -0,0 +1,506 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _TLV_TAG_DEF_ +#define _TLV_TAG_DEF_ + +typedef enum tlv_tag_def { + WIFIMACTX_CBF_START_E = 0 , + WIFIPHYRX_DATA_E = 1 , + WIFIPHYRX_CBF_DATA_RESP_E = 2 , + WIFIPHYRX_ABORT_REQUEST_E = 3 , + WIFIPHYRX_USER_ABORT_NOTIFICATION_E = 4 , + WIFIMACTX_DATA_RESP_E = 5 , + WIFIMACTX_CBF_DATA_E = 6 , + WIFIMACTX_CBF_DONE_E = 7 , + WIFIPHYRX_LMR_DATA_RESP_E = 8 , + WIFIRXPCU_TO_UCODE_START_E = 9 , + WIFIRXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E = 10 , + WIFIRXPCU_TO_UCODE_FULL_MPDU_DATA_E = 11 , + WIFIRXPCU_TO_UCODE_FCS_STATUS_E = 12 , + WIFIRXPCU_TO_UCODE_MPDU_DELIMITER_E = 13 , + WIFIRXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E = 14 , + WIFIRXPCU_TO_UCODE_MPDU_HEADER_DATA_E = 15 , + WIFIRXPCU_TO_UCODE_END_E = 16 , + WIFIMACRX_CBF_READ_REQUEST_E = 32 , + WIFIMACRX_CBF_DATA_REQUEST_E = 33 , + WIFIMACRX_EXPECT_NDP_RECEPTION_E = 34 , + WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E = 35 , + WIFIMACRX_NDP_TIMEOUT_E = 36 , + WIFIMACRX_ABORT_ACK_E = 37 , + WIFIMACRX_REQ_IMPLICIT_FB_E = 38 , + WIFIMACRX_CHAIN_MASK_E = 39 , + WIFIMACRX_NAP_USER_E = 40 , + WIFIMACRX_ABORT_REQUEST_E = 41 , + WIFIPHYTX_OTHER_TRANSMIT_INFO16_E = 42 , + WIFIPHYTX_ABORT_ACK_E = 43 , + WIFIPHYTX_ABORT_REQUEST_E = 44 , + WIFIPHYTX_PKT_END_E = 45 , + WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E = 46 , + WIFIPHYTX_REQUEST_CTRL_INFO_E = 47 , + WIFIPHYTX_DATA_REQUEST_E = 48 , + WIFIPHYTX_BF_CV_LOADING_DONE_E = 49 , + WIFIPHYTX_NAP_ACK_E = 50 , + WIFIPHYTX_NAP_DONE_E = 51 , + WIFIPHYTX_OFF_ACK_E = 52 , + WIFIPHYTX_ON_ACK_E = 53 , + WIFIPHYTX_SYNTH_OFF_ACK_E = 54 , + WIFIPHYTX_DEBUG16_E = 55 , + WIFIMACTX_ABORT_REQUEST_E = 56 , + WIFIMACTX_ABORT_ACK_E = 57 , + WIFIMACTX_PKT_END_E = 58 , + WIFIMACTX_PRE_PHY_DESC_E = 59 , + WIFIMACTX_BF_PARAMS_COMMON_E = 60 , + WIFIMACTX_BF_PARAMS_PER_USER_E = 61 , + WIFIMACTX_PREFETCH_CV_E = 62 , + WIFIMACTX_USER_DESC_COMMON_E = 63 , + WIFIMACTX_USER_DESC_PER_USER_E = 64 , + WIFIEXAMPLE_USER_TLV_16_E = 65 , + WIFIEXAMPLE_TLV_16_E = 66 , + WIFIMACTX_PHY_OFF_E = 67 , + WIFIMACTX_PHY_ON_E = 68 , + WIFIMACTX_SYNTH_OFF_E = 69 , + WIFIMACTX_EXPECT_CBF_COMMON_E = 70 , + WIFIMACTX_EXPECT_CBF_PER_USER_E = 71 , + WIFIMACTX_PHY_DESC_E = 72 , + WIFIMACTX_L_SIG_A_E = 73 , + WIFIMACTX_L_SIG_B_E = 74 , + WIFIMACTX_HT_SIG_E = 75 , + WIFIMACTX_VHT_SIG_A_E = 76 , + WIFIMACTX_VHT_SIG_B_SU20_E = 77 , + WIFIMACTX_VHT_SIG_B_SU40_E = 78 , + WIFIMACTX_VHT_SIG_B_SU80_E = 79 , + WIFIMACTX_VHT_SIG_B_SU160_E = 80 , + WIFIMACTX_VHT_SIG_B_MU20_E = 81 , + WIFIMACTX_VHT_SIG_B_MU40_E = 82 , + WIFIMACTX_VHT_SIG_B_MU80_E = 83 , + WIFIMACTX_VHT_SIG_B_MU160_E = 84 , + WIFIMACTX_SERVICE_E = 85 , + WIFIMACTX_HE_SIG_A_SU_E = 86 , + WIFIMACTX_HE_SIG_A_MU_DL_E = 87 , + WIFIMACTX_HE_SIG_A_MU_UL_E = 88 , + WIFIMACTX_HE_SIG_B1_MU_E = 89 , + WIFIMACTX_HE_SIG_B2_MU_E = 90 , + WIFIMACTX_HE_SIG_B2_OFDMA_E = 91 , + WIFIMACTX_DELETE_CV_E = 92 , + WIFIMACTX_MU_UPLINK_COMMON_E = 93 , + WIFIMACTX_MU_UPLINK_USER_SETUP_E = 94 , + WIFIMACTX_OTHER_TRANSMIT_INFO_E = 95 , + WIFIMACTX_PHY_NAP_E = 96 , + WIFIMACTX_DEBUG_E = 97 , + WIFIPHYRX_ABORT_ACK_E = 98 , + WIFIPHYRX_GENERATED_CBF_DETAILS_E = 99 , + WIFIPHYRX_RSSI_LEGACY_E = 100 , + WIFIPHYRX_RSSI_HT_E = 101 , + WIFIPHYRX_USER_INFO_E = 102 , + WIFIPHYRX_PKT_END_E = 103 , + WIFIPHYRX_DEBUG_E = 104 , + WIFIPHYRX_CBF_TRANSFER_DONE_E = 105 , + WIFIPHYRX_CBF_TRANSFER_ABORT_E = 106 , + WIFIPHYRX_L_SIG_A_E = 107 , + WIFIPHYRX_L_SIG_B_E = 108 , + WIFIPHYRX_HT_SIG_E = 109 , + WIFIPHYRX_VHT_SIG_A_E = 110 , + WIFIPHYRX_VHT_SIG_B_SU20_E = 111 , + WIFIPHYRX_VHT_SIG_B_SU40_E = 112 , + WIFIPHYRX_VHT_SIG_B_SU80_E = 113 , + WIFIPHYRX_VHT_SIG_B_SU160_E = 114 , + WIFIPHYRX_VHT_SIG_B_MU20_E = 115 , + WIFIPHYRX_VHT_SIG_B_MU40_E = 116 , + WIFIPHYRX_VHT_SIG_B_MU80_E = 117 , + WIFIPHYRX_VHT_SIG_B_MU160_E = 118 , + WIFIPHYRX_HE_SIG_A_SU_E = 119 , + WIFIPHYRX_HE_SIG_A_MU_DL_E = 120 , + WIFIPHYRX_HE_SIG_A_MU_UL_E = 121 , + WIFIPHYRX_HE_SIG_B1_MU_E = 122 , + WIFIPHYRX_HE_SIG_B2_MU_E = 123 , + WIFIPHYRX_HE_SIG_B2_OFDMA_E = 124 , + WIFIPHYRX_OTHER_RECEIVE_INFO_E = 125 , + WIFIPHYRX_COMMON_USER_INFO_E = 126 , + WIFIPHYRX_DATA_DONE_E = 127 , + WIFICOEX_TX_REQ_E = 128 , + WIFIDUMMY_E = 129 , + WIFIEXAMPLE_TLV_32_NAME_E = 130 , + WIFIMPDU_LIMIT_E = 131 , + WIFINA_LENGTH_END_E = 132 , + WIFIOLE_BUF_STATUS_E = 133 , + WIFIPCU_PPDU_SETUP_DONE_E = 134 , + WIFIPCU_PPDU_SETUP_END_E = 135 , + WIFIPCU_PPDU_SETUP_INIT_E = 136 , + WIFIPCU_PPDU_SETUP_START_E = 137 , + WIFIPDG_FES_SETUP_E = 138 , + WIFIPDG_RESPONSE_E = 139 , + WIFIPDG_TX_REQ_E = 140 , + WIFISCH_WAIT_INSTR_E = 141 , + WIFITQM_FLOW_EMPTY_STATUS_E = 143 , + WIFITQM_FLOW_NOT_EMPTY_STATUS_E = 144 , + WIFITQM_GEN_MPDU_LENGTH_LIST_E = 145 , + WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 146 , + WIFITQM_GEN_MPDUS_E = 147 , + WIFITQM_GEN_MPDUS_STATUS_E = 148 , + WIFITQM_REMOVE_MPDU_E = 149 , + WIFITQM_REMOVE_MPDU_STATUS_E = 150 , + WIFITQM_REMOVE_MSDU_E = 151 , + WIFITQM_REMOVE_MSDU_STATUS_E = 152 , + WIFITQM_UPDATE_TX_MPDU_COUNT_E = 153 , + WIFITQM_WRITE_CMD_E = 154 , + WIFIOFDMA_TRIGGER_DETAILS_E = 155 , + WIFITX_DATA_E = 156 , + WIFITX_FES_SETUP_E = 157 , + WIFIRX_PACKET_E = 158 , + WIFIEXPECTED_RESPONSE_E = 159 , + WIFITX_MPDU_END_E = 160 , + WIFITX_MPDU_START_E = 161 , + WIFITX_MSDU_END_E = 162 , + WIFITX_MSDU_START_E = 163 , + WIFITX_SW_MODE_SETUP_E = 164 , + WIFITXPCU_BUFFER_STATUS_E = 165 , + WIFITXPCU_USER_BUFFER_STATUS_E = 166 , + WIFIDATA_TO_TIME_CONFIG_E = 167 , + WIFIEXAMPLE_USER_TLV_32_E = 168 , + WIFIMPDU_INFO_E = 169 , + WIFIPDG_USER_SETUP_E = 170 , + WIFITX_11AH_SETUP_E = 171 , + WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E = 172 , + WIFITX_PEER_ENTRY_E = 173 , + WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E = 174 , + WIFIEXAMPLE_USER_TLV_44_E = 175 , + WIFITX_FLUSH_E = 176 , + WIFITX_FLUSH_REQ_E = 177 , + WIFITQM_WRITE_CMD_STATUS_E = 178 , + WIFITQM_GET_MPDU_QUEUE_STATS_E = 179 , + WIFITQM_GET_MSDU_FLOW_STATS_E = 180 , + WIFIEXAMPLE_USER_CTLV_44_E = 181 , + WIFITX_FES_STATUS_START_E = 182 , + WIFITX_FES_STATUS_USER_PPDU_E = 183 , + WIFITX_FES_STATUS_USER_RESPONSE_E = 184 , + WIFITX_FES_STATUS_END_E = 185 , + WIFIRX_TRIG_INFO_E = 186 , + WIFIRXPCU_TX_SETUP_CLEAR_E = 187 , + WIFIRX_FRAME_BITMAP_REQ_E = 188 , + WIFIRX_FRAME_BITMAP_ACK_E = 189 , + WIFICOEX_RX_STATUS_E = 190 , + WIFIRX_START_PARAM_E = 191 , + WIFIRX_PPDU_START_E = 192 , + WIFIRX_PPDU_END_E = 193 , + WIFIRX_MPDU_START_E = 194 , + WIFIRX_MPDU_END_E = 195 , + WIFIRX_MSDU_START_E = 196 , + WIFIRX_MSDU_END_E = 197 , + WIFIRX_ATTENTION_E = 198 , + WIFIRECEIVED_RESPONSE_INFO_E = 199 , + WIFIRX_PHY_SLEEP_E = 200 , + WIFIRX_HEADER_E = 201 , + WIFIRX_PEER_ENTRY_E = 202 , + WIFIRX_FLUSH_E = 203 , + WIFIRX_RESPONSE_REQUIRED_INFO_E = 204 , + WIFIRX_FRAMELESS_BAR_DETAILS_E = 205 , + WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E = 206 , + WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E = 207 , + WIFITX_CBF_INFO_E = 208 , + WIFIPCU_PPDU_SETUP_USER_E = 209 , + WIFIRX_MPDU_PCU_START_E = 210 , + WIFIRX_PM_INFO_E = 211 , + WIFIRX_USER_PPDU_END_E = 212 , + WIFIRX_PRE_PPDU_START_E = 213 , + WIFIRX_PREAMBLE_E = 214 , + WIFITX_FES_SETUP_COMPLETE_E = 215 , + WIFITX_LAST_MPDU_FETCHED_E = 216 , + WIFITXDMA_STOP_REQUEST_E = 217 , + WIFIRXPCU_SETUP_E = 218 , + WIFIRXPCU_USER_SETUP_E = 219 , + WIFITX_FES_STATUS_ACK_OR_BA_E = 220 , + WIFITQM_ACKED_MPDU_E = 221 , + WIFICOEX_TX_RESP_E = 222 , + WIFICOEX_TX_STATUS_E = 223 , + WIFIMACTX_COEX_PHY_CTRL_E = 224 , + WIFICOEX_STATUS_BROADCAST_E = 225 , + WIFIRESPONSE_START_STATUS_E = 226 , + WIFIRESPONSE_END_STATUS_E = 227 , + WIFICRYPTO_STATUS_E = 228 , + WIFIRECEIVED_TRIGGER_INFO_E = 229 , + WIFICOEX_TX_STOP_CTRL_E = 230 , + WIFIRX_PPDU_ACK_REPORT_E = 231 , + WIFIRX_PPDU_NO_ACK_REPORT_E = 232 , + WIFISCH_COEX_STATUS_E = 233 , + WIFISCHEDULER_COMMAND_STATUS_E = 234 , + WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 235 , + WIFITX_FES_STATUS_PROT_E = 236 , + WIFITX_FES_STATUS_START_PPDU_E = 237 , + WIFITX_FES_STATUS_START_PROT_E = 238 , + WIFITXPCU_PHYTX_DEBUG32_E = 239 , + WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 240 , + WIFITX_MPDU_COUNT_TRANSFER_END_E = 241 , + WIFIWHO_ANCHOR_OFFSET_E = 242 , + WIFIWHO_ANCHOR_VALUE_E = 243 , + WIFIWHO_CCE_INFO_E = 244 , + WIFIWHO_COMMIT_E = 245 , + WIFIWHO_COMMIT_DONE_E = 246 , + WIFIWHO_FLUSH_E = 247 , + WIFIWHO_L2_LLC_E = 248 , + WIFIWHO_L2_PAYLOAD_E = 249 , + WIFIWHO_L3_CHECKSUM_E = 250 , + WIFIWHO_L3_INFO_E = 251 , + WIFIWHO_L4_CHECKSUM_E = 252 , + WIFIWHO_L4_INFO_E = 253 , + WIFIWHO_MSDU_E = 254 , + WIFIWHO_MSDU_MISC_E = 255 , + WIFIWHO_PACKET_DATA_E = 256 , + WIFIWHO_PACKET_HDR_E = 257 , + WIFIWHO_PPDU_END_E = 258 , + WIFIWHO_PPDU_START_E = 259 , + WIFIWHO_TSO_E = 260 , + WIFIWHO_WMAC_HEADER_PV0_E = 261 , + WIFIWHO_WMAC_HEADER_PV1_E = 262 , + WIFIWHO_WMAC_IV_E = 263 , + WIFIMPDU_INFO_END_E = 264 , + WIFIMPDU_INFO_BITMAP_E = 265 , + WIFITX_QUEUE_EXTENSION_E = 266 , + WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E = 267 , + WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 268 , + WIFITQM_ACKED_MPDU_STATUS_E = 269 , + WIFITQM_ADD_MSDU_STATUS_E = 270 , + WIFITQM_LIST_GEN_DONE_E = 271 , + WIFIWHO_TERMINATE_E = 272 , + WIFITX_LAST_MPDU_END_E = 273 , + WIFITX_CV_DATA_E = 274 , + WIFIPPDU_TX_END_E = 275 , + WIFIPROT_TX_END_E = 276 , + WIFIMPDU_INFO_GLOBAL_END_E = 277 , + WIFITQM_SCH_INSTR_GLOBAL_END_E = 278 , + WIFIRX_PPDU_END_USER_STATS_E = 279 , + WIFIRX_PPDU_END_USER_STATS_EXT_E = 280 , + WIFIREO_GET_QUEUE_STATS_E = 281 , + WIFIREO_FLUSH_QUEUE_E = 282 , + WIFIREO_FLUSH_CACHE_E = 283 , + WIFIREO_UNBLOCK_CACHE_E = 284 , + WIFIREO_GET_QUEUE_STATS_STATUS_E = 285 , + WIFIREO_FLUSH_QUEUE_STATUS_E = 286 , + WIFIREO_FLUSH_CACHE_STATUS_E = 287 , + WIFIREO_UNBLOCK_CACHE_STATUS_E = 288 , + WIFITQM_FLUSH_CACHE_E = 289 , + WIFITQM_UNBLOCK_CACHE_E = 290 , + WIFITQM_FLUSH_CACHE_STATUS_E = 291 , + WIFITQM_UNBLOCK_CACHE_STATUS_E = 292 , + WIFIRX_PPDU_END_STATUS_DONE_E = 293 , + WIFIRX_STATUS_BUFFER_DONE_E = 294 , + WIFITX_DATA_SYNC_E = 297 , + WIFIPHYRX_CBF_READ_REQUEST_ACK_E = 298 , + WIFITQM_GET_MPDU_HEAD_INFO_E = 299 , + WIFITQM_SYNC_CMD_E = 300 , + WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E = 301 , + WIFITQM_SYNC_CMD_STATUS_E = 302 , + WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 303 , + WIFITQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 304 , + WIFIREO_FLUSH_TIMEOUT_LIST_E = 305 , + WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E = 306 , + WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 307 , + WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 308 , + WIFIEXAMPLE_USER_TLV_32_NAME_E = 309 , + WIFIRX_PPDU_START_USER_INFO_E = 310 , + WIFIRX_RING_MASK_E = 311 , + WIFICOEX_MAC_NAP_E = 312 , + WIFIRXPCU_PPDU_END_INFO_E = 313 , + WIFIWHO_MESH_CONTROL_E = 314 , + WIFIPDG_SW_MODE_BW_START_E = 315 , + WIFIPDG_SW_MODE_BW_END_E = 316 , + WIFIPDG_WAIT_FOR_MAC_REQUEST_E = 317 , + WIFIPDG_WAIT_FOR_PHY_REQUEST_E = 318 , + WIFISCHEDULER_END_E = 319 , + WIFIRX_PPDU_START_DROPPED_E = 320 , + WIFIRX_PPDU_END_DROPPED_E = 321 , + WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E = 322 , + WIFIRX_MPDU_START_DROPPED_E = 323 , + WIFIRX_MSDU_START_DROPPED_E = 324 , + WIFIRX_MSDU_END_DROPPED_E = 325 , + WIFIRX_MPDU_END_DROPPED_E = 326 , + WIFIRX_ATTENTION_DROPPED_E = 327 , + WIFITXPCU_USER_SETUP_E = 328 , + WIFIRXPCU_USER_SETUP_EXT_E = 329 , + WIFICMD_PART_0_END_E = 330 , + WIFIMACTX_SYNTH_ON_E = 331 , + WIFISCH_CRITICAL_TLV_REFERENCE_E = 332 , + WIFITQM_MPDU_GLOBAL_START_E = 333 , + WIFIEXAMPLE_TLV_32_E = 334 , + WIFITQM_UPDATE_TX_MSDU_FLOW_E = 335 , + WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 336 , + WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 337 , + WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 338 , + WIFIREO_UPDATE_RX_REO_QUEUE_E = 339 , + WIFITQM_MPDU_QUEUE_EMPTY_STATUS_E = 340 , + WIFITQM_2_SCH_MPDU_AVAILABLE_E = 341 , + WIFIPDG_TRIG_RESPONSE_E = 342 , + WIFITRIGGER_RESPONSE_TX_DONE_E = 343 , + WIFIABORT_FROM_PHYRX_DETAILS_E = 344 , + WIFISCH_TQM_CMD_WRAPPER_E = 345 , + WIFIMPDUS_AVAILABLE_E = 346 , + WIFIRECEIVED_RESPONSE_INFO_PART2_E = 347 , + WIFIPHYRX_TX_START_TIMING_E = 348 , + WIFITXPCU_PREAMBLE_DONE_E = 349 , + WIFINDP_PREAMBLE_DONE_E = 350 , + WIFISCH_TQM_CMD_WRAPPER_RBO_DROP_E = 351 , + WIFISCH_TQM_CMD_WRAPPER_CONT_DROP_E = 352 , + WIFIMACTX_CLEAR_PREV_TX_INFO_E = 353 , + WIFITX_PUNCTURE_SETUP_E = 354 , + WIFIR2R_STATUS_END_E = 355 , + WIFIMACTX_PREFETCH_CV_COMMON_E = 356 , + WIFIEND_OF_FLUSH_MARKER_E = 357 , + WIFIMACTX_MU_UPLINK_COMMON_PUNC_E = 358 , + WIFIMACTX_MU_UPLINK_USER_SETUP_PUNC_E = 359 , + WIFIRECEIVED_RESPONSE_USER_7_0_E = 360 , + WIFIRECEIVED_RESPONSE_USER_15_8_E = 361 , + WIFIRECEIVED_RESPONSE_USER_23_16_E = 362 , + WIFIRECEIVED_RESPONSE_USER_31_24_E = 363 , + WIFIRECEIVED_RESPONSE_USER_36_32_E = 364 , + WIFITX_LOOPBACK_SETUP_E = 365 , + WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 366 , + WIFISCH_WAIT_INSTR_TX_PATH_E = 367 , + WIFIMACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 368 , + WIFIMACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 369 , + WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 370 , + WIFITX_WUR_DATA_E = 371 , + WIFIRX_PPDU_END_START_E = 372 , + WIFIRX_PPDU_END_MIDDLE_E = 373 , + WIFIRX_PPDU_END_LAST_E = 374 , + WIFIMACTX_BACKOFF_BASED_TRANSMISSION_E = 375 , + WIFIMACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 376 , + WIFISRP_INFO_E = 377 , + WIFIOBSS_SR_INFO_E = 378 , + WIFISCHEDULER_SW_MSG_STATUS_E = 379 , + WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 380 , + WIFIRXPCU_SETUP_COMPLETE_E = 381 , + WIFISNOOP_PPDU_START_E = 382 , + WIFISNOOP_MPDU_USR_DBG_INFO_E = 383 , + WIFISNOOP_MSDU_USR_DBG_INFO_E = 384 , + WIFISNOOP_MSDU_USR_DATA_E = 385 , + WIFISNOOP_MPDU_USR_STAT_INFO_E = 386 , + WIFISNOOP_PPDU_END_E = 387 , + WIFISNOOP_SPARE_E = 388 , + WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 390 , + WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 391 , + WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 392 , + WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 393 , + WIFISCH_TLV_WRAPPER_E = 394 , + WIFISCHEDULER_STATUS_WRAPPER_E = 395 , + WIFIMPDU_INFO_6X_E = 396 , + WIFIMACTX_11AZ_USER_DESC_PER_USER_E = 397 , + WIFIMACTX_U_SIG_EHT_SU_MU_E = 398 , + WIFIMACTX_U_SIG_EHT_TB_E = 399 , + WIFIPHYRX_U_SIG_EHT_SU_MU_E = 403 , + WIFIPHYRX_U_SIG_EHT_TB_E = 404 , + WIFIMACRX_LMR_READ_REQUEST_E = 408 , + WIFIMACRX_LMR_DATA_REQUEST_E = 409 , + WIFIPHYRX_LMR_TRANSFER_DONE_E = 410 , + WIFIPHYRX_LMR_TRANSFER_ABORT_E = 411 , + WIFIPHYRX_LMR_READ_REQUEST_ACK_E = 412 , + WIFIMACRX_SECURE_LTF_SEQ_PTR_E = 413 , + WIFIPHYRX_USER_INFO_MU_UL_E = 414 , + WIFIMPDU_QUEUE_OVERVIEW_E = 415 , + WIFISCHEDULER_NAV_INFO_E = 416 , + WIFILMR_PEER_ENTRY_E = 418 , + WIFILMR_MPDU_START_E = 419 , + WIFILMR_DATA_E = 420 , + WIFILMR_MPDU_END_E = 421 , + WIFIREO_GET_QUEUE_1K_STATS_STATUS_E = 422 , + WIFIRX_FRAME_1K_BITMAP_ACK_E = 423 , + WIFITX_FES_STATUS_1K_BA_E = 424 , + WIFITQM_ACKED_1K_MPDU_E = 425 , + WIFIMACRX_INBSS_OBSS_IND_E = 426 , + WIFIPHYRX_LOCATION_E = 427 , + WIFIMLO_TX_NOTIFICATION_SU_E = 428 , + WIFIMLO_TX_NOTIFICATION_MU_E = 429 , + WIFIMLO_TX_REQ_SU_E = 430 , + WIFIMLO_TX_REQ_MU_E = 431 , + WIFIMLO_TX_RESP_E = 432 , + WIFIMLO_RX_NOTIFICATION_E = 433 , + WIFIMLO_BKOFF_TRUNC_REQ_E = 434 , + WIFIMLO_TBTT_NOTIFICATION_E = 435 , + WIFIMLO_MESSAGE_E = 436 , + WIFIMLO_TS_SYNC_MSG_E = 437 , + WIFIMLO_FES_SETUP_E = 438 , + WIFIMLO_PDG_FES_SETUP_SU_E = 439 , + WIFIMLO_PDG_FES_SETUP_MU_E = 440 , + WIFIMPDU_INFO_1K_BITMAP_E = 441 , + WIFIMON_BUFFER_ADDR_E = 442 , + WIFITX_FRAG_STATE_E = 443 , + WIFIMACTX_EHT_SIG_USR_OFDMA_E = 446 , + WIFIPHYRX_EHT_SIG_CMN_PUNC_E = 448 , + WIFIPHYRX_EHT_SIG_CMN_OFDMA_E = 450 , + WIFIPHYRX_EHT_SIG_USR_OFDMA_E = 454 , + WIFIPHYRX_PKT_END_PART1_E = 456 , + WIFIMACTX_EXPECT_NDP_RECEPTION_E = 457 , + WIFIMACTX_SECURE_LTF_SEQ_PTR_E = 458 , + WIFIMLO_PDG_BKOFF_TRUNC_NOTIFY_E = 460 , + WIFIPHYRX_11AZ_INTEGRITY_DATA_E = 461 , + WIFIPHYTX_LOCATION_E = 462 , + WIFIPHYTX_11AZ_INTEGRITY_DATA_E = 463 , + WIFIMACTX_EHT_SIG_USR_SU_E = 466 , + WIFIMACTX_EHT_SIG_USR_MU_MIMO_E = 467 , + WIFIPHYRX_EHT_SIG_USR_SU_E = 468 , + WIFIPHYRX_EHT_SIG_USR_MU_MIMO_E = 469 , + WIFIPHYRX_GENERIC_U_SIG_E = 470 , + WIFIPHYRX_GENERIC_EHT_SIG_E = 471 , + WIFIOVERWRITE_RESP_START_E = 472 , + WIFIOVERWRITE_RESP_PREAMBLE_INFO_E = 473 , + WIFIOVERWRITE_RESP_FRAME_INFO_E = 474 , + WIFIOVERWRITE_RESP_END_E = 475 , + WIFIRXPCU_EARLY_RX_INDICATION_E = 476 , + WIFIMON_DROP_E = 477 , + WIFIMACRX_MU_UPLINK_COMMON_SNIFF_E = 478 , + WIFIMACRX_MU_UPLINK_USER_SETUP_SNIFF_E = 479 , + WIFIMACRX_MU_UPLINK_USER_SEL_SNIFF_E = 480 , + WIFIMACRX_MU_UPLINK_FCS_STATUS_SNIFF_E = 481 , + WIFIMACTX_PREFETCH_CV_DMA_E = 482 , + WIFIMACTX_PREFETCH_CV_PER_USER_E = 483 , + WIFIPHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E = 484 , + WIFIMACTX_BF_PARAMS_UPDATE_COMMON_E = 485 , + WIFIMACTX_BF_PARAMS_UPDATE_PER_USER_E = 486 , + WIFIRANGING_USER_DETAILS_E = 487 , + WIFIPHYTX_CV_CORR_STATUS_E = 488 , + WIFIPHYTX_CV_CORR_COMMON_E = 489 , + WIFIPHYTX_CV_CORR_USER_E = 490 , + WIFIMACTX_CV_CORR_COMMON_E = 491 , + WIFIMACTX_CV_CORR_MAC_INFO_GROUP_E = 492 , + WIFIBW_PUNCTURE_EVAL_WRAPPER_E = 493 , + WIFIMACTX_RX_NOTIFICATION_FOR_PHY_E = 494 , + WIFIMACTX_TX_NOTIFICATION_FOR_PHY_E = 495 , + WIFIMACTX_MU_UPLINK_COMMON_PER_BW_E = 496 , + WIFIMACTX_MU_UPLINK_USER_SETUP_PER_BW_E = 497 , + WIFIRX_PPDU_END_USER_STATS_EXT2_E = 498 , + WIFIFW2SW_MON_E = 499 , + WIFIWSI_DIRECT_MESSAGE_E = 500 , + WIFIMACTX_EMLSR_PRE_SWITCH_E = 501 , + WIFIMACTX_EMLSR_SWITCH_E = 502 , + WIFIMACTX_EMLSR_SWITCH_BACK_E = 503 , + WIFIPHYTX_EMLSR_SWITCH_ACK_E = 504 , + WIFIPHYTX_EMLSR_SWITCH_BACK_ACK_E = 505 , + WIFISPARE_REUSE_TAG_0_E = 506 , + WIFISPARE_REUSE_TAG_1_E = 507 , + WIFISPARE_REUSE_TAG_2_E = 508 , + WIFISPARE_REUSE_TAG_3_E = 509 +} tlv_tag_def__e; + + +#endif diff --git a/hw/qcn9224/tx_msdu_extension.h b/hw/qcn9224/tx_msdu_extension.h new file mode 100644 index 000000000000..02d0d7c08c1f --- /dev/null +++ b/hw/qcn9224/tx_msdu_extension.h @@ -0,0 +1,532 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _TX_MSDU_EXTENSION_H_ +#define _TX_MSDU_EXTENSION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 + + +struct tx_msdu_extension { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tso_enable : 1, + reserved_0a : 6, + tcp_flag : 9, + tcp_flag_mask : 9, + reserved_0b : 7; + uint32_t l2_length : 16, + ip_length : 16; + uint32_t tcp_seq_number : 32; + uint32_t ip_identification : 16, + udp_length : 16; + uint32_t checksum_offset : 14, + partial_checksum_en : 1, + reserved_4a : 1, + payload_start_offset : 14, + reserved_4b : 2; + uint32_t payload_end_offset : 14, + reserved_5a : 2, + wds : 1, + reserved_5b : 15; + uint32_t buf0_ptr_31_0 : 32; + uint32_t buf0_ptr_39_32 : 8, + extn_override : 1, + encap_type : 2, + encrypt_type : 4, + tqm_no_drop : 1, + buf0_len : 16; + uint32_t buf1_ptr_31_0 : 32; + uint32_t buf1_ptr_39_32 : 8, + epd : 1, + mesh_enable : 2, + reserved_9a : 5, + buf1_len : 16; + uint32_t buf2_ptr_31_0 : 32; + uint32_t buf2_ptr_39_32 : 8, + dscp_tid_table_num : 6, + reserved_11a : 2, + buf2_len : 16; + uint32_t buf3_ptr_31_0 : 32; + uint32_t buf3_ptr_39_32 : 8, + reserved_13a : 8, + buf3_len : 16; + uint32_t buf4_ptr_31_0 : 32; + uint32_t buf4_ptr_39_32 : 8, + reserved_15a : 8, + buf4_len : 16; + uint32_t buf5_ptr_31_0 : 32; + uint32_t buf5_ptr_39_32 : 8, + reserved_17a : 8, + buf5_len : 16; +#else + uint32_t reserved_0b : 7, + tcp_flag_mask : 9, + tcp_flag : 9, + reserved_0a : 6, + tso_enable : 1; + uint32_t ip_length : 16, + l2_length : 16; + uint32_t tcp_seq_number : 32; + uint32_t udp_length : 16, + ip_identification : 16; + uint32_t reserved_4b : 2, + payload_start_offset : 14, + reserved_4a : 1, + partial_checksum_en : 1, + checksum_offset : 14; + uint32_t reserved_5b : 15, + wds : 1, + reserved_5a : 2, + payload_end_offset : 14; + uint32_t buf0_ptr_31_0 : 32; + uint32_t buf0_len : 16, + tqm_no_drop : 1, + encrypt_type : 4, + encap_type : 2, + extn_override : 1, + buf0_ptr_39_32 : 8; + uint32_t buf1_ptr_31_0 : 32; + uint32_t buf1_len : 16, + reserved_9a : 5, + mesh_enable : 2, + epd : 1, + buf1_ptr_39_32 : 8; + uint32_t buf2_ptr_31_0 : 32; + uint32_t buf2_len : 16, + reserved_11a : 2, + dscp_tid_table_num : 6, + buf2_ptr_39_32 : 8; + uint32_t buf3_ptr_31_0 : 32; + uint32_t buf3_len : 16, + reserved_13a : 8, + buf3_ptr_39_32 : 8; + uint32_t buf4_ptr_31_0 : 32; + uint32_t buf4_len : 16, + reserved_15a : 8, + buf4_ptr_39_32 : 8; + uint32_t buf5_ptr_31_0 : 32; + uint32_t buf5_len : 16, + reserved_17a : 8, + buf5_ptr_39_32 : 8; +#endif +}; + + + + +#define TX_MSDU_EXTENSION_TSO_ENABLE_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_TSO_ENABLE_LSB 0 +#define TX_MSDU_EXTENSION_TSO_ENABLE_MSB 0 +#define TX_MSDU_EXTENSION_TSO_ENABLE_MASK 0x00000001 + + + + +#define TX_MSDU_EXTENSION_RESERVED_0A_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_RESERVED_0A_LSB 1 +#define TX_MSDU_EXTENSION_RESERVED_0A_MSB 6 +#define TX_MSDU_EXTENSION_RESERVED_0A_MASK 0x0000007e + + + + +#define TX_MSDU_EXTENSION_TCP_FLAG_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_TCP_FLAG_LSB 7 +#define TX_MSDU_EXTENSION_TCP_FLAG_MSB 15 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK 0x0000ff80 + + + + +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_LSB 16 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MSB 24 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MASK 0x01ff0000 + + + + +#define TX_MSDU_EXTENSION_RESERVED_0B_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_RESERVED_0B_LSB 25 +#define TX_MSDU_EXTENSION_RESERVED_0B_MSB 31 +#define TX_MSDU_EXTENSION_RESERVED_0B_MASK 0xfe000000 + + + + +#define TX_MSDU_EXTENSION_L2_LENGTH_OFFSET 0x00000004 +#define TX_MSDU_EXTENSION_L2_LENGTH_LSB 0 +#define TX_MSDU_EXTENSION_L2_LENGTH_MSB 15 +#define TX_MSDU_EXTENSION_L2_LENGTH_MASK 0x0000ffff + + + + +#define TX_MSDU_EXTENSION_IP_LENGTH_OFFSET 0x00000004 +#define TX_MSDU_EXTENSION_IP_LENGTH_LSB 16 +#define TX_MSDU_EXTENSION_IP_LENGTH_MSB 31 +#define TX_MSDU_EXTENSION_IP_LENGTH_MASK 0xffff0000 + + + + +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_OFFSET 0x00000008 +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_LSB 0 +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MSB 31 +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MASK 0xffffffff + + + + +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_OFFSET 0x0000000c +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_LSB 0 +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MSB 15 +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MASK 0x0000ffff + + + + +#define TX_MSDU_EXTENSION_UDP_LENGTH_OFFSET 0x0000000c +#define TX_MSDU_EXTENSION_UDP_LENGTH_LSB 16 +#define TX_MSDU_EXTENSION_UDP_LENGTH_MSB 31 +#define TX_MSDU_EXTENSION_UDP_LENGTH_MASK 0xffff0000 + + + + +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_LSB 0 +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MSB 13 +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MASK 0x00003fff + + + + +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_LSB 14 +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MSB 14 +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MASK 0x00004000 + + + + +#define TX_MSDU_EXTENSION_RESERVED_4A_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_RESERVED_4A_LSB 15 +#define TX_MSDU_EXTENSION_RESERVED_4A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_4A_MASK 0x00008000 + + + + +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_LSB 16 +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MSB 29 +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MASK 0x3fff0000 + + + + +#define TX_MSDU_EXTENSION_RESERVED_4B_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_RESERVED_4B_LSB 30 +#define TX_MSDU_EXTENSION_RESERVED_4B_MSB 31 +#define TX_MSDU_EXTENSION_RESERVED_4B_MASK 0xc0000000 + + + + +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_LSB 0 +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MSB 13 +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MASK 0x00003fff + + + + +#define TX_MSDU_EXTENSION_RESERVED_5A_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_RESERVED_5A_LSB 14 +#define TX_MSDU_EXTENSION_RESERVED_5A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_5A_MASK 0x0000c000 + + + + +#define TX_MSDU_EXTENSION_WDS_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_WDS_LSB 16 +#define TX_MSDU_EXTENSION_WDS_MSB 16 +#define TX_MSDU_EXTENSION_WDS_MASK 0x00010000 + + + + +#define TX_MSDU_EXTENSION_RESERVED_5B_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_RESERVED_5B_LSB 17 +#define TX_MSDU_EXTENSION_RESERVED_5B_MSB 31 +#define TX_MSDU_EXTENSION_RESERVED_5B_MASK 0xfffe0000 + + + + +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_OFFSET 0x00000018 +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MASK 0xffffffff + + + + +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MASK 0x000000ff + + + + +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_LSB 8 +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MSB 8 +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MASK 0x00000100 + + + + +#define TX_MSDU_EXTENSION_ENCAP_TYPE_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_ENCAP_TYPE_LSB 9 +#define TX_MSDU_EXTENSION_ENCAP_TYPE_MSB 10 +#define TX_MSDU_EXTENSION_ENCAP_TYPE_MASK 0x00000600 + + + + +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_LSB 11 +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MSB 14 +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MASK 0x00007800 + + + + +#define TX_MSDU_EXTENSION_TQM_NO_DROP_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_TQM_NO_DROP_LSB 15 +#define TX_MSDU_EXTENSION_TQM_NO_DROP_MSB 15 +#define TX_MSDU_EXTENSION_TQM_NO_DROP_MASK 0x00008000 + + + + +#define TX_MSDU_EXTENSION_BUF0_LEN_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_BUF0_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF0_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF0_LEN_MASK 0xffff0000 + + + + +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_OFFSET 0x00000020 +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MASK 0xffffffff + + + + +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MASK 0x000000ff + + + + +#define TX_MSDU_EXTENSION_EPD_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_EPD_LSB 8 +#define TX_MSDU_EXTENSION_EPD_MSB 8 +#define TX_MSDU_EXTENSION_EPD_MASK 0x00000100 + + + + +#define TX_MSDU_EXTENSION_MESH_ENABLE_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_MESH_ENABLE_LSB 9 +#define TX_MSDU_EXTENSION_MESH_ENABLE_MSB 10 +#define TX_MSDU_EXTENSION_MESH_ENABLE_MASK 0x00000600 + + + + +#define TX_MSDU_EXTENSION_RESERVED_9A_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_RESERVED_9A_LSB 11 +#define TX_MSDU_EXTENSION_RESERVED_9A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_9A_MASK 0x0000f800 + + + + +#define TX_MSDU_EXTENSION_BUF1_LEN_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_BUF1_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF1_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF1_LEN_MASK 0xffff0000 + + + + +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_OFFSET 0x00000028 +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MASK 0xffffffff + + + + +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MASK 0x000000ff + + + + +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_LSB 8 +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_MSB 13 +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_MASK 0x00003f00 + + + + +#define TX_MSDU_EXTENSION_RESERVED_11A_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_RESERVED_11A_LSB 14 +#define TX_MSDU_EXTENSION_RESERVED_11A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_11A_MASK 0x0000c000 + + + + +#define TX_MSDU_EXTENSION_BUF2_LEN_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_BUF2_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF2_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF2_LEN_MASK 0xffff0000 + + + + +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_OFFSET 0x00000030 +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MASK 0xffffffff + + + + +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MASK 0x000000ff + + + + +#define TX_MSDU_EXTENSION_RESERVED_13A_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_RESERVED_13A_LSB 8 +#define TX_MSDU_EXTENSION_RESERVED_13A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_13A_MASK 0x0000ff00 + + + + +#define TX_MSDU_EXTENSION_BUF3_LEN_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_BUF3_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF3_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF3_LEN_MASK 0xffff0000 + + + + +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_OFFSET 0x00000038 +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MASK 0xffffffff + + + + +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MASK 0x000000ff + + + + +#define TX_MSDU_EXTENSION_RESERVED_15A_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_RESERVED_15A_LSB 8 +#define TX_MSDU_EXTENSION_RESERVED_15A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_15A_MASK 0x0000ff00 + + + + +#define TX_MSDU_EXTENSION_BUF4_LEN_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_BUF4_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF4_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF4_LEN_MASK 0xffff0000 + + + + +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_OFFSET 0x00000040 +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MASK 0xffffffff + + + + +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MASK 0x000000ff + + + + +#define TX_MSDU_EXTENSION_RESERVED_17A_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_RESERVED_17A_LSB 8 +#define TX_MSDU_EXTENSION_RESERVED_17A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_17A_MASK 0x0000ff00 + + + + +#define TX_MSDU_EXTENSION_BUF5_LEN_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_BUF5_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF5_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF5_LEN_MASK 0xffff0000 + + + +#endif diff --git a/hw/qcn9224/tx_rate_stats_info.h b/hw/qcn9224/tx_rate_stats_info.h new file mode 100644 index 000000000000..b381ed9d0c3a --- /dev/null +++ b/hw/qcn9224/tx_rate_stats_info.h @@ -0,0 +1,152 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _TX_RATE_STATS_INFO_H_ +#define _TX_RATE_STATS_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2 + + +struct tx_rate_stats_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_rate_stats_info_valid : 1, + transmit_bw : 3, + transmit_pkt_type : 4, + transmit_stbc : 1, + transmit_ldpc : 1, + transmit_sgi : 2, + transmit_mcs : 4, + ofdma_transmission : 1, + tones_in_ru : 12, + reserved_0a : 3; + uint32_t ppdu_transmission_tsf : 32; +#else + uint32_t reserved_0a : 3, + tones_in_ru : 12, + ofdma_transmission : 1, + transmit_mcs : 4, + transmit_sgi : 2, + transmit_ldpc : 1, + transmit_stbc : 1, + transmit_pkt_type : 4, + transmit_bw : 3, + tx_rate_stats_info_valid : 1; + uint32_t ppdu_transmission_tsf : 32; +#endif +}; + + + + +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_LSB 0 +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MSB 0 +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + + + + +#define TX_RATE_STATS_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_BW_LSB 1 +#define TX_RATE_STATS_INFO_TRANSMIT_BW_MSB 3 +#define TX_RATE_STATS_INFO_TRANSMIT_BW_MASK 0x0000000e + + + + +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_LSB 4 +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MSB 7 +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MASK 0x000000f0 + + + + +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_LSB 8 +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MSB 8 +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MASK 0x00000100 + + + + +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_LSB 9 +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MSB 9 +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MASK 0x00000200 + + + + +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_LSB 10 +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MSB 11 +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MASK 0x00000c00 + + + + +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_LSB 12 +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MSB 15 +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MASK 0x0000f000 + + + + +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_LSB 16 +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MSB 16 +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MASK 0x00010000 + + + + +#define TX_RATE_STATS_INFO_TONES_IN_RU_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TONES_IN_RU_LSB 17 +#define TX_RATE_STATS_INFO_TONES_IN_RU_MSB 28 +#define TX_RATE_STATS_INFO_TONES_IN_RU_MASK 0x1ffe0000 + + + + +#define TX_RATE_STATS_INFO_RESERVED_0A_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_RESERVED_0A_LSB 29 +#define TX_RATE_STATS_INFO_RESERVED_0A_MSB 31 +#define TX_RATE_STATS_INFO_RESERVED_0A_MASK 0xe0000000 + + + + +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_OFFSET 0x00000004 +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_LSB 0 +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MSB 31 +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + + + +#endif diff --git a/hw/qcn9224/uniform_descriptor_header.h b/hw/qcn9224/uniform_descriptor_header.h new file mode 100644 index 000000000000..5422df551847 --- /dev/null +++ b/hw/qcn9224/uniform_descriptor_header.h @@ -0,0 +1,72 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_ +#define _UNIFORM_DESCRIPTOR_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1 + + +struct uniform_descriptor_header { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t owner : 4, + buffer_type : 4, + reserved_0a : 24; +#else + uint32_t reserved_0a : 24, + buffer_type : 4, + owner : 4; +#endif +}; + + + + +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + + + + +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + + + + +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 + + + +#endif diff --git a/hw/qcn9224/uniform_reo_cmd_header.h b/hw/qcn9224/uniform_reo_cmd_header.h new file mode 100644 index 000000000000..013e34593364 --- /dev/null +++ b/hw/qcn9224/uniform_reo_cmd_header.h @@ -0,0 +1,72 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _UNIFORM_REO_CMD_HEADER_H_ +#define _UNIFORM_REO_CMD_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER 1 + + +struct uniform_reo_cmd_header { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_cmd_number : 16, + reo_status_required : 1, + reserved_0a : 15; +#else + uint32_t reserved_0a : 15, + reo_status_required : 1, + reo_cmd_number : 16; +#endif +}; + + + + +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + + + + +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + + + + +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_LSB 17 +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_MSB 31 +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + + + +#endif diff --git a/hw/qcn9224/uniform_reo_status_header.h b/hw/qcn9224/uniform_reo_status_header.h new file mode 100644 index 000000000000..0ec6b3bef489 --- /dev/null +++ b/hw/qcn9224/uniform_reo_status_header.h @@ -0,0 +1,92 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _UNIFORM_REO_STATUS_HEADER_H_ +#define _UNIFORM_REO_STATUS_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_UNIFORM_REO_STATUS_HEADER 2 + + +struct uniform_reo_status_header { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_status_number : 16, + cmd_execution_time : 10, + reo_cmd_execution_status : 2, + reserved_0a : 4; + uint32_t timestamp : 32; +#else + uint32_t reserved_0a : 4, + reo_cmd_execution_status : 2, + cmd_execution_time : 10, + reo_status_number : 16; + uint32_t timestamp : 32; +#endif +}; + + + + +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + + + + +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + + + + +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + + + + +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_LSB 28 +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_MSB 31 +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + + + + +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_LSB 0 +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_MSB 31 +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + + + +#endif diff --git a/hw/qcn9224/vht_sig_a_info.h b/hw/qcn9224/vht_sig_a_info.h new file mode 100644 index 000000000000..fb6360d80069 --- /dev/null +++ b/hw/qcn9224/vht_sig_a_info.h @@ -0,0 +1,222 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _VHT_SIG_A_INFO_H_ +#define _VHT_SIG_A_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_A_INFO 2 + + +struct vht_sig_a_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t bandwidth : 2, + vhta_reserved_0 : 1, + stbc : 1, + group_id : 6, + n_sts : 12, + txop_ps_not_allowed : 1, + vhta_reserved_0b : 1, + reserved_0 : 8; + uint32_t gi_setting : 2, + su_mu_coding : 1, + ldpc_extra_symbol : 1, + mcs : 4, + beamformed : 1, + vhta_reserved_1 : 1, + crc : 8, + tail : 6, + reserved_1 : 7, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0 : 8, + vhta_reserved_0b : 1, + txop_ps_not_allowed : 1, + n_sts : 12, + group_id : 6, + stbc : 1, + vhta_reserved_0 : 1, + bandwidth : 2; + uint32_t rx_integrity_check_passed : 1, + reserved_1 : 7, + tail : 6, + crc : 8, + vhta_reserved_1 : 1, + beamformed : 1, + mcs : 4, + ldpc_extra_symbol : 1, + su_mu_coding : 1, + gi_setting : 2; +#endif +}; + + + + +#define VHT_SIG_A_INFO_BANDWIDTH_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_BANDWIDTH_LSB 0 +#define VHT_SIG_A_INFO_BANDWIDTH_MSB 1 +#define VHT_SIG_A_INFO_BANDWIDTH_MASK 0x00000003 + + + + +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_LSB 2 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MSB 2 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MASK 0x00000004 + + + + +#define VHT_SIG_A_INFO_STBC_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_STBC_LSB 3 +#define VHT_SIG_A_INFO_STBC_MSB 3 +#define VHT_SIG_A_INFO_STBC_MASK 0x00000008 + + + + +#define VHT_SIG_A_INFO_GROUP_ID_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_GROUP_ID_LSB 4 +#define VHT_SIG_A_INFO_GROUP_ID_MSB 9 +#define VHT_SIG_A_INFO_GROUP_ID_MASK 0x000003f0 + + + + +#define VHT_SIG_A_INFO_N_STS_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_N_STS_LSB 10 +#define VHT_SIG_A_INFO_N_STS_MSB 21 +#define VHT_SIG_A_INFO_N_STS_MASK 0x003ffc00 + + + + +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_LSB 22 +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MSB 22 +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MASK 0x00400000 + + + + +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_LSB 23 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MSB 23 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MASK 0x00800000 + + + + +#define VHT_SIG_A_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_RESERVED_0_LSB 24 +#define VHT_SIG_A_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_A_INFO_RESERVED_0_MASK 0xff000000 + + + + +#define VHT_SIG_A_INFO_GI_SETTING_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_GI_SETTING_LSB 0 +#define VHT_SIG_A_INFO_GI_SETTING_MSB 1 +#define VHT_SIG_A_INFO_GI_SETTING_MASK 0x00000003 + + + + +#define VHT_SIG_A_INFO_SU_MU_CODING_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_SU_MU_CODING_LSB 2 +#define VHT_SIG_A_INFO_SU_MU_CODING_MSB 2 +#define VHT_SIG_A_INFO_SU_MU_CODING_MASK 0x00000004 + + + + +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_LSB 3 +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MSB 3 +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000008 + + + + +#define VHT_SIG_A_INFO_MCS_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_MCS_LSB 4 +#define VHT_SIG_A_INFO_MCS_MSB 7 +#define VHT_SIG_A_INFO_MCS_MASK 0x000000f0 + + + + +#define VHT_SIG_A_INFO_BEAMFORMED_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_BEAMFORMED_LSB 8 +#define VHT_SIG_A_INFO_BEAMFORMED_MSB 8 +#define VHT_SIG_A_INFO_BEAMFORMED_MASK 0x00000100 + + + + +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_LSB 9 +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MSB 9 +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MASK 0x00000200 + + + + +#define VHT_SIG_A_INFO_CRC_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_CRC_LSB 10 +#define VHT_SIG_A_INFO_CRC_MSB 17 +#define VHT_SIG_A_INFO_CRC_MASK 0x0003fc00 + + + + +#define VHT_SIG_A_INFO_TAIL_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_TAIL_LSB 18 +#define VHT_SIG_A_INFO_TAIL_MSB 23 +#define VHT_SIG_A_INFO_TAIL_MASK 0x00fc0000 + + + + +#define VHT_SIG_A_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_RESERVED_1_LSB 24 +#define VHT_SIG_A_INFO_RESERVED_1_MSB 30 +#define VHT_SIG_A_INFO_RESERVED_1_MASK 0x7f000000 + + + + +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif diff --git a/hw/qcn9224/wbm2sw_completion_ring_rx.h b/hw/qcn9224/wbm2sw_completion_ring_rx.h new file mode 100644 index 000000000000..6a21d1fbadd0 --- /dev/null +++ b/hw/qcn9224/wbm2sw_completion_ring_rx.h @@ -0,0 +1,466 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _WBM2SW_COMPLETION_RING_RX_H_ +#define _WBM2SW_COMPLETION_RING_RX_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_msdu_desc_info.h" +#include "rx_mpdu_desc_info.h" +#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_RX 8 + + +struct wbm2sw_completion_ring_rx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t release_source_module : 3, + bm_action : 3, + buffer_or_desc_type : 3, + return_buffer_manager : 4, + reserved_2a : 2, + cache_id : 1, + cookie_conversion_status : 1, + rxdma_push_reason : 2, + rxdma_error_code : 5, + reo_push_reason : 2, + reo_error_code : 5, + wbm_internal_error : 1; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_phys_addr_31_0 : 32; + uint32_t buffer_phys_addr_39_32 : 8, + sw_buffer_cookie : 20, + looping_count : 4; +#else + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t wbm_internal_error : 1, + reo_error_code : 5, + reo_push_reason : 2, + rxdma_error_code : 5, + rxdma_push_reason : 2, + cookie_conversion_status : 1, + cache_id : 1, + reserved_2a : 2, + return_buffer_manager : 4, + buffer_or_desc_type : 3, + bm_action : 3, + release_source_module : 3; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_phys_addr_31_0 : 32; + uint32_t looping_count : 4, + sw_buffer_cookie : 20, + buffer_phys_addr_39_32 : 8; +#endif +}; + + + + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + + + + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + + + + +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + + + + +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_LSB 3 +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MSB 5 +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MASK 0x00000038 + + + + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + + + + +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_LSB 9 +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MSB 12 +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 + + + + +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_LSB 13 +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MSB 14 +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MASK 0x00006000 + + + + +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_LSB 15 +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MSB 15 +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MASK 0x00008000 + + + + +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 + + + + +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_LSB 17 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MSB 18 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 + + + + +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_LSB 19 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MSB 23 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 + + + + +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_LSB 24 +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MSB 25 +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MASK 0x03000000 + + + + +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_LSB 26 +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MSB 30 +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 + + + + +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 + + + + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + + + + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + + + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000 + + + + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_OFFSET 0x00000018 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MASK 0xffffffff + + + + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MSB 7 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MASK 0x000000ff + + + + +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_LSB 8 +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MSB 27 +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MASK 0x0fffff00 + + + + +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_LSB 28 +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif diff --git a/hw/qcn9224/wbm2sw_completion_ring_tx.h b/hw/qcn9224/wbm2sw_completion_ring_tx.h new file mode 100644 index 000000000000..fbabf66290c7 --- /dev/null +++ b/hw/qcn9224/wbm2sw_completion_ring_tx.h @@ -0,0 +1,376 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _WBM2SW_COMPLETION_RING_TX_H_ +#define _WBM2SW_COMPLETION_RING_TX_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "tx_rate_stats_info.h" +#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_TX 8 + + +struct wbm2sw_completion_ring_tx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t release_source_module : 3, + cache_id : 1, + reserved_2a : 2, + buffer_or_desc_type : 3, + return_buffer_manager : 4, + tqm_release_reason : 4, + rbm_override_valid : 1, + sw_buffer_cookie_11_0 : 12, + cookie_conversion_status : 1, + wbm_internal_error : 1; + uint32_t tqm_status_number : 24, + transmit_count : 7, + sw_release_details_valid : 1; + uint32_t ack_frame_rssi : 8, + first_msdu : 1, + last_msdu : 1, + fw_tx_notify_frame : 3, + buffer_timestamp : 19; + struct tx_rate_stats_info tx_rate_stats; + uint32_t sw_peer_id : 16, + tid : 4, + sw_buffer_cookie_19_12 : 8, + looping_count : 4; +#else + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t wbm_internal_error : 1, + cookie_conversion_status : 1, + sw_buffer_cookie_11_0 : 12, + rbm_override_valid : 1, + tqm_release_reason : 4, + return_buffer_manager : 4, + buffer_or_desc_type : 3, + reserved_2a : 2, + cache_id : 1, + release_source_module : 3; + uint32_t sw_release_details_valid : 1, + transmit_count : 7, + tqm_status_number : 24; + uint32_t buffer_timestamp : 19, + fw_tx_notify_frame : 3, + last_msdu : 1, + first_msdu : 1, + ack_frame_rssi : 8; + struct tx_rate_stats_info tx_rate_stats; + uint32_t looping_count : 4, + sw_buffer_cookie_19_12 : 8, + tid : 4, + sw_peer_id : 16; +#endif +}; + + + + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + + + + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + + + + +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + + + + +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_LSB 3 +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MSB 3 +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MASK 0x00000008 + + + + +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_LSB 4 +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MSB 5 +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MASK 0x00000030 + + + + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + + + + +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_LSB 9 +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MSB 12 +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 + + + + +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_LSB 13 +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MSB 16 +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MASK 0x0001e000 + + + + +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_LSB 17 +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MSB 17 +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MASK 0x00020000 + + + + +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_LSB 18 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MSB 29 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MASK 0x3ffc0000 + + + + +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_LSB 30 +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MSB 30 +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MASK 0x40000000 + + + + +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MASK 0x80000000 + + + + +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MSB 23 +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MASK 0x00ffffff + + + + +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_LSB 24 +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MSB 30 +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MASK 0x7f000000 + + + + +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_LSB 31 +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 + + + + +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MSB 7 +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MASK 0x000000ff + + + + +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_LSB 8 +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MSB 8 +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MASK 0x00000100 + + + + +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_LSB 9 +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MSB 9 +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MASK 0x00000200 + + + + +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_LSB 10 +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MSB 12 +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 + + + + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_LSB 13 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MASK 0xffffe000 + + + + + + + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + + + + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB 1 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB 3 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e + + + + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 + + + + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 + + + + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 + + + + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 + + + + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB 15 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0000f000 + + + + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 16 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 16 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00010000 + + + + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB 17 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB 28 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK 0x1ffe0000 + + + + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_RESERVED_0A_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_RESERVED_0A_LSB 29 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_RESERVED_0A_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_RESERVED_0A_MASK 0xe0000000 + + + + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + + + + +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MSB 15 +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MASK 0x0000ffff + + + + +#define WBM2SW_COMPLETION_RING_TX_TID_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_TID_LSB 16 +#define WBM2SW_COMPLETION_RING_TX_TID_MSB 19 +#define WBM2SW_COMPLETION_RING_TX_TID_MASK 0x000f0000 + + + + +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_LSB 20 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MSB 27 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MASK 0x0ff00000 + + + + +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_LSB 28 +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif diff --git a/hw/qcn9224/wbm_buffer_ring.h b/hw/qcn9224/wbm_buffer_ring.h new file mode 100644 index 000000000000..60b0f338dcef --- /dev/null +++ b/hw/qcn9224/wbm_buffer_ring.h @@ -0,0 +1,80 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _WBM_BUFFER_RING_H_ +#define _WBM_BUFFER_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_BUFFER_RING 2 + + +struct wbm_buffer_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buf_addr_info; +#else + struct buffer_addr_info buf_addr_info; +#endif +}; + + + + + + + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + +#endif diff --git a/hw/qcn9224/wbm_link_descriptor_ring.h b/hw/qcn9224/wbm_link_descriptor_ring.h new file mode 100644 index 000000000000..6426353d5218 --- /dev/null +++ b/hw/qcn9224/wbm_link_descriptor_ring.h @@ -0,0 +1,80 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _WBM_LINK_DESCRIPTOR_RING_H_ +#define _WBM_LINK_DESCRIPTOR_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2 + + +struct wbm_link_descriptor_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info desc_addr_info; +#else + struct buffer_addr_info desc_addr_info; +#endif +}; + + + + + + + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + +#endif diff --git a/hw/qcn9224/wbm_release_ring.h b/hw/qcn9224/wbm_release_ring.h new file mode 100644 index 000000000000..e34596274f1f --- /dev/null +++ b/hw/qcn9224/wbm_release_ring.h @@ -0,0 +1,190 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _WBM_RELEASE_RING_H_ +#define _WBM_RELEASE_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_RELEASE_RING 8 + + +struct wbm_release_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t release_source_module : 3, + reserved_2a : 3, + buffer_or_desc_type : 3, + reserved_2b : 22, + wbm_internal_error : 1; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 28, + looping_count : 4; +#else + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t wbm_internal_error : 1, + reserved_2b : 22, + buffer_or_desc_type : 3, + reserved_2a : 3, + release_source_module : 3; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t looping_count : 4, + reserved_7a : 28; +#endif +}; + + + + + + + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 + + + + +#define WBM_RELEASE_RING_RESERVED_2A_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RESERVED_2A_LSB 3 +#define WBM_RELEASE_RING_RESERVED_2A_MSB 5 +#define WBM_RELEASE_RING_RESERVED_2A_MASK 0x00000038 + + + + +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + + + + +#define WBM_RELEASE_RING_RESERVED_2B_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RESERVED_2B_LSB 9 +#define WBM_RELEASE_RING_RESERVED_2B_MSB 30 +#define WBM_RELEASE_RING_RESERVED_2B_MASK 0x7ffffe00 + + + + +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_LSB 31 +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MSB 31 +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MASK 0x80000000 + + + + +#define WBM_RELEASE_RING_RESERVED_3A_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RESERVED_3A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_3A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_3A_MASK 0xffffffff + + + + +#define WBM_RELEASE_RING_RESERVED_4A_OFFSET 0x00000010 +#define WBM_RELEASE_RING_RESERVED_4A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_4A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_4A_MASK 0xffffffff + + + + +#define WBM_RELEASE_RING_RESERVED_5A_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RESERVED_5A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_5A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_5A_MASK 0xffffffff + + + + +#define WBM_RELEASE_RING_RESERVED_6A_OFFSET 0x00000018 +#define WBM_RELEASE_RING_RESERVED_6A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_6A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_6A_MASK 0xffffffff + + + + +#define WBM_RELEASE_RING_RESERVED_7A_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RESERVED_7A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_7A_MSB 27 +#define WBM_RELEASE_RING_RESERVED_7A_MASK 0x0fffffff + + + + +#define WBM_RELEASE_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM_RELEASE_RING_LOOPING_COUNT_LSB 28 +#define WBM_RELEASE_RING_LOOPING_COUNT_MSB 31 +#define WBM_RELEASE_RING_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif diff --git a/hw/qcn9224/wbm_release_ring_rx.h b/hw/qcn9224/wbm_release_ring_rx.h new file mode 100644 index 000000000000..247323397a1a --- /dev/null +++ b/hw/qcn9224/wbm_release_ring_rx.h @@ -0,0 +1,484 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _WBM_RELEASE_RING_RX_H_ +#define _WBM_RELEASE_RING_RX_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_msdu_desc_info.h" +#include "rx_mpdu_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_RELEASE_RING_RX 8 + + +struct wbm_release_ring_rx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t release_source_module : 3, + bm_action : 3, + buffer_or_desc_type : 3, + first_msdu_index : 4, + reserved_2a : 2, + cache_id : 1, + cookie_conversion_status : 1, + rxdma_push_reason : 2, + rxdma_error_code : 5, + reo_push_reason : 2, + reo_error_code : 5, + wbm_internal_error : 1; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 20, + ring_id : 8, + looping_count : 4; +#else + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t wbm_internal_error : 1, + reo_error_code : 5, + reo_push_reason : 2, + rxdma_error_code : 5, + rxdma_push_reason : 2, + cookie_conversion_status : 1, + cache_id : 1, + reserved_2a : 2, + first_msdu_index : 4, + buffer_or_desc_type : 3, + bm_action : 3, + release_source_module : 3; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t reserved_6a : 32; + uint32_t looping_count : 4, + ring_id : 8, + reserved_7a : 20; +#endif +}; + + + + + + + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + + + + +#define WBM_RELEASE_RING_RX_BM_ACTION_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_BM_ACTION_LSB 3 +#define WBM_RELEASE_RING_RX_BM_ACTION_MSB 5 +#define WBM_RELEASE_RING_RX_BM_ACTION_MASK 0x00000038 + + + + +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + + + + +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_LSB 9 +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MSB 12 +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MASK 0x00001e00 + + + + +#define WBM_RELEASE_RING_RX_RESERVED_2A_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RESERVED_2A_LSB 13 +#define WBM_RELEASE_RING_RX_RESERVED_2A_MSB 14 +#define WBM_RELEASE_RING_RX_RESERVED_2A_MASK 0x00006000 + + + + +#define WBM_RELEASE_RING_RX_CACHE_ID_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_CACHE_ID_LSB 15 +#define WBM_RELEASE_RING_RX_CACHE_ID_MSB 15 +#define WBM_RELEASE_RING_RX_CACHE_ID_MASK 0x00008000 + + + + +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 + + + + +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_LSB 17 +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MSB 18 +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 + + + + +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_LSB 19 +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MSB 23 +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 + + + + +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_LSB 24 +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MSB 25 +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MASK 0x03000000 + + + + +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_LSB 26 +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MSB 30 +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 + + + + +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 + + + + + + + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + + + + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + + + + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + + + + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + + + + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + + + + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + + + + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + + + + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + + + + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + + + + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + + + + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + + + + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + + + + + + + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + + + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + + + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + + + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + + + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + + + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + + + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + + + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + + + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + + + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + + + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + + + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + + + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + + + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + + + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + + + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + + + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000 + + + + +#define WBM_RELEASE_RING_RX_RESERVED_6A_OFFSET 0x00000018 +#define WBM_RELEASE_RING_RX_RESERVED_6A_LSB 0 +#define WBM_RELEASE_RING_RX_RESERVED_6A_MSB 31 +#define WBM_RELEASE_RING_RX_RESERVED_6A_MASK 0xffffffff + + + + +#define WBM_RELEASE_RING_RX_RESERVED_7A_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RX_RESERVED_7A_LSB 0 +#define WBM_RELEASE_RING_RX_RESERVED_7A_MSB 19 +#define WBM_RELEASE_RING_RX_RESERVED_7A_MASK 0x000fffff + + + + +#define WBM_RELEASE_RING_RX_RING_ID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RX_RING_ID_LSB 20 +#define WBM_RELEASE_RING_RX_RING_ID_MSB 27 +#define WBM_RELEASE_RING_RX_RING_ID_MASK 0x0ff00000 + + + + +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_LSB 28 +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_MSB 31 +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif diff --git a/hw/qcn9224/wbm_release_ring_tx.h b/hw/qcn9224/wbm_release_ring_tx.h new file mode 100644 index 000000000000..51306643c8ab --- /dev/null +++ b/hw/qcn9224/wbm_release_ring_tx.h @@ -0,0 +1,404 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _WBM_RELEASE_RING_TX_H_ +#define _WBM_RELEASE_RING_TX_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "tx_rate_stats_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_RELEASE_RING_TX 8 + + +struct wbm_release_ring_tx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t release_source_module : 3, + bm_action : 3, + buffer_or_desc_type : 3, + first_msdu_index : 4, + tqm_release_reason : 4, + rbm_override_valid : 1, + rbm_override : 4, + reserved_2a : 7, + cache_id : 1, + cookie_conversion_status : 1, + wbm_internal_error : 1; + uint32_t tqm_status_number : 24, + transmit_count : 7, + sw_release_details_valid : 1; + uint32_t ack_frame_rssi : 8, + first_msdu : 1, + last_msdu : 1, + fw_tx_notify_frame : 3, + buffer_timestamp : 19; + struct tx_rate_stats_info tx_rate_stats; + uint32_t sw_peer_id : 16, + tid : 4, + tqm_status_number_31_24 : 8, + looping_count : 4; +#else + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t wbm_internal_error : 1, + cookie_conversion_status : 1, + cache_id : 1, + reserved_2a : 7, + rbm_override : 4, + rbm_override_valid : 1, + tqm_release_reason : 4, + first_msdu_index : 4, + buffer_or_desc_type : 3, + bm_action : 3, + release_source_module : 3; + uint32_t sw_release_details_valid : 1, + transmit_count : 7, + tqm_status_number : 24; + uint32_t buffer_timestamp : 19, + fw_tx_notify_frame : 3, + last_msdu : 1, + first_msdu : 1, + ack_frame_rssi : 8; + struct tx_rate_stats_info tx_rate_stats; + uint32_t looping_count : 4, + tqm_status_number_31_24 : 8, + tid : 4, + sw_peer_id : 16; +#endif +}; + + + + + + + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + + + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + + + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + + + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + + +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + + + + +#define WBM_RELEASE_RING_TX_BM_ACTION_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_BM_ACTION_LSB 3 +#define WBM_RELEASE_RING_TX_BM_ACTION_MSB 5 +#define WBM_RELEASE_RING_TX_BM_ACTION_MASK 0x00000038 + + + + +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + + + + +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_LSB 9 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MSB 12 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MASK 0x00001e00 + + + + +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_LSB 13 +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MSB 16 +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MASK 0x0001e000 + + + + +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_LSB 17 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MSB 17 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MASK 0x00020000 + + + + +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_LSB 18 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MSB 21 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MASK 0x003c0000 + + + + +#define WBM_RELEASE_RING_TX_RESERVED_2A_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RESERVED_2A_LSB 22 +#define WBM_RELEASE_RING_TX_RESERVED_2A_MSB 28 +#define WBM_RELEASE_RING_TX_RESERVED_2A_MASK 0x1fc00000 + + + + +#define WBM_RELEASE_RING_TX_CACHE_ID_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_CACHE_ID_LSB 29 +#define WBM_RELEASE_RING_TX_CACHE_ID_MSB 29 +#define WBM_RELEASE_RING_TX_CACHE_ID_MASK 0x20000000 + + + + +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_LSB 30 +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MSB 30 +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MASK 0x40000000 + + + + +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MASK 0x80000000 + + + + +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_LSB 0 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MSB 23 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MASK 0x00ffffff + + + + +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_OFFSET 0x0000000c +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_LSB 24 +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MSB 30 +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MASK 0x7f000000 + + + + +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_LSB 31 +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MSB 31 +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 + + + + +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_LSB 0 +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MSB 7 +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MASK 0x000000ff + + + + +#define WBM_RELEASE_RING_TX_FIRST_MSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_LSB 8 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_MSB 8 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_MASK 0x00000100 + + + + +#define WBM_RELEASE_RING_TX_LAST_MSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_LAST_MSDU_LSB 9 +#define WBM_RELEASE_RING_TX_LAST_MSDU_MSB 9 +#define WBM_RELEASE_RING_TX_LAST_MSDU_MASK 0x00000200 + + + + +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_LSB 10 +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MSB 12 +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 + + + + +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_LSB 13 +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MSB 31 +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MASK 0xffffe000 + + + + + + + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + + + + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB 1 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB 3 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e + + + + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 + + + + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 + + + + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 + + + + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 + + + + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB 15 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0000f000 + + + + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 16 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 16 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00010000 + + + + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB 17 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB 28 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK 0x1ffe0000 + + + + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_RESERVED_0A_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_RESERVED_0A_LSB 29 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_RESERVED_0A_MSB 31 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_RESERVED_0A_MASK 0xe0000000 + + + + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + + + + +#define WBM_RELEASE_RING_TX_SW_PEER_ID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_SW_PEER_ID_LSB 0 +#define WBM_RELEASE_RING_TX_SW_PEER_ID_MSB 15 +#define WBM_RELEASE_RING_TX_SW_PEER_ID_MASK 0x0000ffff + + + + +#define WBM_RELEASE_RING_TX_TID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_TID_LSB 16 +#define WBM_RELEASE_RING_TX_TID_MSB 19 +#define WBM_RELEASE_RING_TX_TID_MASK 0x000f0000 + + + + +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_LSB 20 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MSB 27 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MASK 0x0ff00000 + + + + +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_LSB 28 +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_MSB 31 +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif diff --git a/hw/qcn9224/wcss_seq_hwiobase.h b/hw/qcn9224/wcss_seq_hwiobase.h new file mode 100644 index 000000000000..a8409b012abe --- /dev/null +++ b/hw/qcn9224/wcss_seq_hwiobase.h @@ -0,0 +1,162 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef __WCSS_SEQ_HWIOBASE_H__ +#define __WCSS_SEQ_HWIOBASE_H__ + + + + + + +#define WCSS_CFGBUS_BASE 0x00008000 +#define WCSS_CFGBUS_BASE_SIZE 0x00008000 +#define WCSS_CFGBUS_BASE_PHYS 0x00008000 + + + +#define UMAC_NOC_BASE 0x00140000 +#define UMAC_NOC_BASE_SIZE 0x00004400 +#define UMAC_NOC_BASE_PHYS 0x00140000 + + + +#define PHYA0_BASE 0x00300000 +#define PHYA0_BASE_SIZE 0x00300000 +#define PHYA0_BASE_PHYS 0x00300000 + + + +#define PHYA1_BASE 0x00600000 +#define PHYA1_BASE_SIZE 0x00300000 +#define PHYA1_BASE_PHYS 0x00600000 + + + +#define DMAC_BASE 0x00900000 +#define DMAC_BASE_SIZE 0x00080000 +#define DMAC_BASE_PHYS 0x00900000 + + + +#define UMAC_BASE 0x00a00000 +#define UMAC_BASE_SIZE 0x0004d000 +#define UMAC_BASE_PHYS 0x00a00000 + + + +#define PMAC0_BASE 0x00a80000 +#define PMAC0_BASE_SIZE 0x00040000 +#define PMAC0_BASE_PHYS 0x00a80000 + + + +#define PMAC1_BASE 0x00ac0000 +#define PMAC1_BASE_SIZE 0x00040000 +#define PMAC1_BASE_PHYS 0x00ac0000 + + + +#define MAC_WSIB_BASE 0x00b3c000 +#define MAC_WSIB_BASE_SIZE 0x00004000 +#define MAC_WSIB_BASE_PHYS 0x00b3c000 + + + +#define CXC_BASE 0x00b40000 +#define CXC_BASE_SIZE 0x00010000 +#define CXC_BASE_PHYS 0x00b40000 + + + +#define WFSS_PMM_BASE 0x00b50000 +#define WFSS_PMM_BASE_SIZE 0x00002401 +#define WFSS_PMM_BASE_PHYS 0x00b50000 + + + +#define WFSS_CC_BASE 0x00b60000 +#define WFSS_CC_BASE_SIZE 0x00008000 +#define WFSS_CC_BASE_PHYS 0x00b60000 + + + +#define WCMN_CORE_BASE 0x00b68000 +#define WCMN_CORE_BASE_SIZE 0x000008a9 +#define WCMN_CORE_BASE_PHYS 0x00b68000 + + + +#define WIFI_CFGBUS_APB_TSLV_BASE 0x00b6b000 +#define WIFI_CFGBUS_APB_TSLV_BASE_SIZE 0x00001000 +#define WIFI_CFGBUS_APB_TSLV_BASE_PHYS 0x00b6b000 + + + +#define WFSS_CFGBUS_BASE 0x00b6c000 +#define WFSS_CFGBUS_BASE_SIZE 0x000000a0 +#define WFSS_CFGBUS_BASE_PHYS 0x00b6c000 + + + +#define WIFI_CFGBUS_AHB_TSLV_BASE 0x00b6d000 +#define WIFI_CFGBUS_AHB_TSLV_BASE_SIZE 0x00001000 +#define WIFI_CFGBUS_AHB_TSLV_BASE_PHYS 0x00b6d000 + + + +#define UMAC_ACMT_BASE 0x00b6e000 +#define UMAC_ACMT_BASE_SIZE 0x00001000 +#define UMAC_ACMT_BASE_PHYS 0x00b6e000 + + + +#define WCSS_CC_BASE 0x00b80000 +#define WCSS_CC_BASE_SIZE 0x00010000 +#define WCSS_CC_BASE_PHYS 0x00b80000 + + + +#define PMM_TOP_BASE 0x00b90000 +#define PMM_TOP_BASE_SIZE 0x00010000 +#define PMM_TOP_BASE_PHYS 0x00b90000 + + + +#define WCSS_TOP_CMN_BASE 0x00ba0000 +#define WCSS_TOP_CMN_BASE_SIZE 0x00004000 +#define WCSS_TOP_CMN_BASE_PHYS 0x00ba0000 + + + +#define MSIP_BASE 0x00bb0000 +#define MSIP_BASE_SIZE 0x00010000 +#define MSIP_BASE_PHYS 0x00bb0000 + + + +#define DBG_BASE 0x01000000 +#define DBG_BASE_SIZE 0x00100000 +#define DBG_BASE_PHYS 0x01000000 + + + +#define Q6SS_WLAN_BASE 0x01100000 +#define Q6SS_WLAN_BASE_SIZE 0x00100000 +#define Q6SS_WLAN_BASE_PHYS 0x01100000 + + +#endif diff --git a/hw/qcn9224/wcss_seq_hwioreg_umac.h b/hw/qcn9224/wcss_seq_hwioreg_umac.h new file mode 100644 index 000000000000..6441ff3cd16c --- /dev/null +++ b/hw/qcn9224/wcss_seq_hwioreg_umac.h @@ -0,0 +1,16031 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef __WCSS_SEQ_HWIOREG_UMAC_H__ +#define __WCSS_SEQ_HWIOREG_UMAC_H__ + + + + +#include "seq_hwio.h" +#include "wcss_seq_hwiobase.h" +#ifdef SCALE_INCLUDES +#include "HALhwio.h" +#else +#include "msmhwio.h" +#endif + +#define WBM_REG_REG_BASE (UMAC_BASE + 0x00034000) +#define WBM_REG_REG_BASE_SIZE 0x4000 +#define WBM_REG_REG_BASE_USED 0x3124 +#define WBM_REG_REG_BASE_PHYS (UMAC_BASE_PHYS + 0x00034000) +#define WBM_REG_REG_BASE_OFFS 0x00034000 + +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_ADDR(x) ((x) + 0x3c) +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_PHYS(x) ((x) + 0x3c) +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_OFFS (0x3c) +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_RMSK 0xfffff +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_POR 0x00000000 +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_ATTR 0x3 +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_IN(x) \ + in_dword(HWIO_WBM_R0_DUP_DET_START_COOKIE_ADDR(x)) +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_DUP_DET_START_COOKIE_ADDR(x), m) +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_OUT(x, v) \ + out_dword(HWIO_WBM_R0_DUP_DET_START_COOKIE_ADDR(x),v) +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_DUP_DET_START_COOKIE_ADDR(x),m,v,HWIO_WBM_R0_DUP_DET_START_COOKIE_IN(x)) +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_DUP_DET_START_COOKIE_BMSK 0xfffff +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_DUP_DET_START_COOKIE_SHFT 0 + +#define HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x40) +#define HWIO_WBM_R0_SW_COOKIE_CFG0_PHYS(x) ((x) + 0x40) +#define HWIO_WBM_R0_SW_COOKIE_CFG0_OFFS (0x40) +#define HWIO_WBM_R0_SW_COOKIE_CFG0_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_COOKIE_CFG0_POR 0x00000000 +#define HWIO_WBM_R0_SW_COOKIE_CFG0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_COOKIE_CFG0_ATTR 0x3 +#define HWIO_WBM_R0_SW_COOKIE_CFG0_IN(x) \ + in_dword(HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(x)) +#define HWIO_WBM_R0_SW_COOKIE_CFG0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(x), m) +#define HWIO_WBM_R0_SW_COOKIE_CFG0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(x),v) +#define HWIO_WBM_R0_SW_COOKIE_CFG0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(x),m,v,HWIO_WBM_R0_SW_COOKIE_CFG0_IN(x)) +#define HWIO_WBM_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_SHFT 0 + +#define HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x44) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_PHYS(x) ((x) + 0x44) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_OFFS (0x44) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_RMSK 0x7ffff +#define HWIO_WBM_R0_SW_COOKIE_CFG1_POR 0x00011700 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_COOKIE_CFG1_ATTR 0x3 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_IN(x) \ + in_dword(HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(x)) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(x), m) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(x),v) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(x),m,v,HWIO_WBM_R0_SW_COOKIE_CFG1_IN(x)) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff +#define HWIO_WBM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 + +#define HWIO_WBM_R0_WBM_CFG_2_ADDR(x) ((x) + 0x90) +#define HWIO_WBM_R0_WBM_CFG_2_PHYS(x) ((x) + 0x90) +#define HWIO_WBM_R0_WBM_CFG_2_OFFS (0x90) +#define HWIO_WBM_R0_WBM_CFG_2_RMSK 0x7f +#define HWIO_WBM_R0_WBM_CFG_2_POR 0x00000040 +#define HWIO_WBM_R0_WBM_CFG_2_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_CFG_2_ATTR 0x3 +#define HWIO_WBM_R0_WBM_CFG_2_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_CFG_2_ADDR(x)) +#define HWIO_WBM_R0_WBM_CFG_2_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_CFG_2_ADDR(x), m) +#define HWIO_WBM_R0_WBM_CFG_2_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_CFG_2_ADDR(x),v) +#define HWIO_WBM_R0_WBM_CFG_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_CFG_2_ADDR(x),m,v,HWIO_WBM_R0_WBM_CFG_2_IN(x)) +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_BMSK 0x40 +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_SHFT 6 +#define HWIO_WBM_R0_WBM_CFG_2_TRANS_BUNCHING_UPDATE_BMSK 0x20 +#define HWIO_WBM_R0_WBM_CFG_2_TRANS_BUNCHING_UPDATE_SHFT 5 +#define HWIO_WBM_R0_WBM_CFG_2_TRANS_BUNCHING_256B_EN_BMSK 0x10 +#define HWIO_WBM_R0_WBM_CFG_2_TRANS_BUNCHING_256B_EN_SHFT 4 +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_CONV_INDICATION_EN_BMSK 0x8 +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_CONV_INDICATION_EN_SHFT 3 +#define HWIO_WBM_R0_WBM_CFG_2_OUT_OF_ORDER_RELEASE_EN_BMSK 0x4 +#define HWIO_WBM_R0_WBM_CFG_2_OUT_OF_ORDER_RELEASE_EN_SHFT 2 +#define HWIO_WBM_R0_WBM_CFG_2_ERROR_PATH_COOKIE_CONV_EN_BMSK 0x2 +#define HWIO_WBM_R0_WBM_CFG_2_ERROR_PATH_COOKIE_CONV_EN_SHFT 1 +#define HWIO_WBM_R0_WBM_CFG_2_RELEASE_PATH_COOKIE_CONV_EN_BMSK 0x1 +#define HWIO_WBM_R0_WBM_CFG_2_RELEASE_PATH_COOKIE_CONV_EN_SHFT 0 + +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x) ((x) + 0x94) +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_PHYS(x) ((x) + 0x94) +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_OFFS (0x94) +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_RMSK 0x1ff +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_POR 0x000001fe +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ATTR 0x3 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_IN(x) \ + in_dword(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x)) +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x), m) +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x),v) +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x),m,v,HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_IN(x)) +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM_COOKIE_CONV_GLOBAL_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM_COOKIE_CONV_GLOBAL_ENABLE_SHFT 8 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW6_COOKIE_CONVERSION_EN_BMSK 0x80 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW6_COOKIE_CONVERSION_EN_SHFT 7 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW5_COOKIE_CONVERSION_EN_BMSK 0x40 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW5_COOKIE_CONVERSION_EN_SHFT 6 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW4_COOKIE_CONVERSION_EN_BMSK 0x20 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW4_COOKIE_CONVERSION_EN_SHFT 5 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW3_COOKIE_CONVERSION_EN_BMSK 0x10 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW3_COOKIE_CONVERSION_EN_SHFT 4 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW2_COOKIE_CONVERSION_EN_BMSK 0x8 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW2_COOKIE_CONVERSION_EN_SHFT 3 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW1_COOKIE_CONVERSION_EN_BMSK 0x4 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW1_COOKIE_CONVERSION_EN_SHFT 2 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW0_COOKIE_CONVERSION_EN_BMSK 0x2 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW0_COOKIE_CONVERSION_EN_SHFT 1 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2FW_COOKIE_CONVERSION_EN_BMSK 0x1 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2FW_COOKIE_CONVERSION_EN_SHFT 0 + +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_ADDR(x) ((x) + 0x98) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_PHYS(x) ((x) + 0x98) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_OFFS (0x98) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_POR 0x00000000 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_ATTR 0x3 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_IN(x) \ + in_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG0_ADDR(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_LINK_DESC_RING_CFG0_ADDR(x), m) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG0_ADDR(x),v) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_CFG0_ADDR(x),m,v,HWIO_WBM_R0_LINK_DESC_RING_CFG0_IN(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_WBM2REO_LINK_RING_WATERMARK_BMSK 0xffff0000 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_WBM2REO_LINK_RING_WATERMARK_SHFT 16 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_WBM2TQM_LINK_RING_WATERMARK_BMSK 0xffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_WBM2TQM_LINK_RING_WATERMARK_SHFT 0 + +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_ADDR(x) ((x) + 0x9c) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_PHYS(x) ((x) + 0x9c) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_OFFS (0x9c) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_POR 0x00000000 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_ATTR 0x3 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_IN(x) \ + in_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG1_ADDR(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_LINK_DESC_RING_CFG1_ADDR(x), m) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG1_ADDR(x),v) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_CFG1_ADDR(x),m,v,HWIO_WBM_R0_LINK_DESC_RING_CFG1_IN(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_WBM2FW_LINK_RING_WATERMARK_BMSK 0xffff0000 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_WBM2FW_LINK_RING_WATERMARK_SHFT 16 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_WBM2SW_LINK_RING_WATERMARK_BMSK 0xffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_WBM2SW_LINK_RING_WATERMARK_SHFT 0 + +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_ADDR(x) ((x) + 0xa0) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_PHYS(x) ((x) + 0xa0) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_OFFS (0xa0) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_RMSK 0xffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_POR 0x00000000 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_ATTR 0x3 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_IN(x) \ + in_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG2_ADDR(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_LINK_DESC_RING_CFG2_ADDR(x), m) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_OUT(x, v) \ + out_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG2_ADDR(x),v) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_CFG2_ADDR(x),m,v,HWIO_WBM_R0_LINK_DESC_RING_CFG2_IN(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_WBM2RXDMA0_LINK_RING_WATERMARK_BMSK 0xffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_WBM2RXDMA0_LINK_RING_WATERMARK_SHFT 0 + +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x) ((x) + 0x210) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_PHYS(x) ((x) + 0x210) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_OFFS (0x210) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_RMSK 0x7ff +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_POR 0x00000010 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_ATTR 0x3 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x)) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x),v) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x),m,v,HWIO_WBM_R0_IDLE_LIST_CONTROL_IN(x)) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_BMSK 0x7fc +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_SHFT 2 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_BMSK 0x2 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_SHFT 1 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_BUFFER_IDLE_LIST_MODE_BMSK 0x1 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_BUFFER_IDLE_LIST_MODE_SHFT 0 + +#define HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x) ((x) + 0x214) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_PHYS(x) ((x) + 0x214) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_OFFS (0x214) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_SIZE_POR 0x00020002 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_SIZE_ATTR 0x3 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x)) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_OUT(x, v) \ + out_dword(HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x),v) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x),m,v,HWIO_WBM_R0_IDLE_LIST_SIZE_IN(x)) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_BMSK 0xffff0000 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_SHFT 16 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_BMSK 0xffff +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x) ((x) + 0x220) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_PHYS(x) ((x) + 0x220) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_OFFS (0x220) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_BASE_ADDRESS_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_BASE_ADDRESS_31_0_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x) ((x) + 0x224) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_PHYS(x) ((x) + 0x224) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_OFFS (0x224) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK 0xffffff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT 8 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK 0xff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x) ((x) + 0x230) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_PHYS(x) ((x) + 0x230) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_OFFS (0x230) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_POR 0x00000000 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ATTR 0x3 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_IN(x) \ + in_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), m) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x),v) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x),m,v,HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_IN(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x) ((x) + 0x234) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_PHYS(x) ((x) + 0x234) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_OFFS (0x234) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_RMSK 0x1fffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_POR 0x00000000 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ATTR 0x3 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_IN(x) \ + in_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), m) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x),v) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x),m,v,HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_IN(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK 0x1fff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT 8 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x) ((x) + 0x240) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_PHYS(x) ((x) + 0x240) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_OFFS (0x240) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_POR 0x00000000 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ATTR 0x3 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_IN(x) \ + in_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), m) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x),v) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x),m,v,HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_IN(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x) ((x) + 0x244) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_PHYS(x) ((x) + 0x244) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_OFFS (0x244) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_RMSK 0x1fffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_POR 0x00000000 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ATTR 0x3 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_IN(x) \ + in_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), m) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x),v) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x),m,v,HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_IN(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK 0x1fff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT 8 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x) ((x) + 0x24c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_PHYS(x) ((x) + 0x24c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_OFFS (0x24c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_RMSK 0xfffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_POR 0x00000000 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ATTR 0x3 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_IN(x) \ + in_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), m) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x),v) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x),m,v,HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_IN(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_SCAT_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_SCAT_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x) ((x) + 0x254) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_PHYS(x) ((x) + 0x254) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_OFFS (0x254) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_RMSK 0xfffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_POR 0x00000000 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ATTR 0x3 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_IN(x) \ + in_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), m) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x),v) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x),m,v,HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_IN(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_SCAT_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_SCAT_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x34c) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x34c) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_OFFS (0x34c) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x350) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x350) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_OFFS (0x350) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x) ((x) + 0x354) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_PHYS(x) ((x) + 0x354) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_OFFS (0x354) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_RMSK 0xff +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x358) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x358) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_OFFS (0x358) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x) ((x) + 0x35c) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_PHYS(x) ((x) + 0x35c) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_OFFS (0x35c) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_RMSK 0x3fffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x368) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x368) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_OFFS (0x368) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x36c) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x36c) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_OFFS (0x36c) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x37c) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x37c) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x37c) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x380) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x380) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x380) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x384) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x384) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_OFFS (0x384) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x388) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x388) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x388) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x38c) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x38c) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x38c) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x390) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x390) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x390) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x394) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x394) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x394) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x398) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x398) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x398) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x39c) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x39c) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_OFFS (0x39c) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x3bc) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x3bc) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x3bc) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x3c0) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x3c0) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_OFFS (0x3c0) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x3c4) +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x3c4) +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_LSB_OFFS (0x3c4) +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_SW1_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW1_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW1_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW1_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_SW1_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x3c8) +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x3c8) +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_MSB_OFFS (0x3c8) +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_SW1_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW1_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW1_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW1_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_SW1_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_SW1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_SW1_RELEASE_RING_ID_ADDR(x) ((x) + 0x3cc) +#define HWIO_WBM_R0_SW1_RELEASE_RING_ID_PHYS(x) ((x) + 0x3cc) +#define HWIO_WBM_R0_SW1_RELEASE_RING_ID_OFFS (0x3cc) +#define HWIO_WBM_R0_SW1_RELEASE_RING_ID_RMSK 0xff +#define HWIO_WBM_R0_SW1_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_SW1_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_SW1_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_SW1_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW1_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_SW1_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW1_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_SW1_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW1_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_SW1_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_SW1_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_SW1_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x3d0) +#define HWIO_WBM_R0_SW1_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x3d0) +#define HWIO_WBM_R0_SW1_RELEASE_RING_STATUS_OFFS (0x3d0) +#define HWIO_WBM_R0_SW1_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_SW1_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_SW1_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_SW1_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW1_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_SW1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_SW1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_SW1_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_ADDR(x) ((x) + 0x3d4) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_PHYS(x) ((x) + 0x3d4) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_OFFS (0x3d4) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_RMSK 0x3fffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_SW1_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW1_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW1_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW1_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_SW1_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x3e0) +#define HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x3e0) +#define HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_LSB_OFFS (0x3e0) +#define HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x3e4) +#define HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x3e4) +#define HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_MSB_OFFS (0x3e4) +#define HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_SW1_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x3f4) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x3f4) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x3f4) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x3f8) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x3f8) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x3f8) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x3fc) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x3fc) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_STATUS_OFFS (0x3fc) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x400) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x400) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x400) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x404) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x404) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x404) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x408) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x408) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x408) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x40c) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x40c) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x40c) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x410) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x410) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x410) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x414) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x414) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_DATA_OFFS (0x414) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x434) +#define HWIO_WBM_R0_SW1_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x434) +#define HWIO_WBM_R0_SW1_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x434) +#define HWIO_WBM_R0_SW1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_SW1_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_SW1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_SW1_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_SW1_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_SW1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x438) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x438) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_1_OFFS (0x438) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_SW1_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW1_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW1_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW1_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_SW1_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_SW1_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x43c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x43c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_OFFS (0x43c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x440) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x440) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_OFFS (0x440) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x) ((x) + 0x444) +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_PHYS(x) ((x) + 0x444) +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_OFFS (0x444) +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_RMSK 0xff +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_PPE_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x448) +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x448) +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_OFFS (0x448) +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x) ((x) + 0x44c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_PHYS(x) ((x) + 0x44c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_OFFS (0x44c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_RMSK 0x3fffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_PPE_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x458) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x458) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_OFFS (0x458) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x45c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x45c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_OFFS (0x45c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x46c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x46c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x46c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x470) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x470) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x470) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x474) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x474) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_OFFS (0x474) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x478) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x478) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x478) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x47c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x47c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x47c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x480) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x480) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x480) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x484) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x484) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x484) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x488) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x488) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x488) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x48c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x48c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_OFFS (0x48c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x4ac) +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x4ac) +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x4ac) +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x4b0) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x4b0) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_1_OFFS (0x4b0) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_PPE_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_PPE_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_PPE_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_PPE_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0xa54) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_PHYS(x) ((x) + 0xa54) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_OFFS (0xa54) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x) ((x) + 0xa58) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_PHYS(x) ((x) + 0xa58) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_OFFS (0xa58) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x) ((x) + 0xa5c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_PHYS(x) ((x) + 0xa5c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_OFFS (0xa5c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x) ((x) + 0xa60) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_PHYS(x) ((x) + 0xa60) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_OFFS (0xa60) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x) ((x) + 0xa64) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_PHYS(x) ((x) + 0xa64) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_OFFS (0xa64) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xa68) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xa68) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_OFFS (0xa68) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xa6c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xa6c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_OFFS (0xa6c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xa78) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xa78) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_OFFS (0xa78) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xa7c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xa7c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_OFFS (0xa7c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xa80) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xa80) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_OFFS (0xa80) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa9c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa9c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_OFFS (0xa9c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xaa0) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xaa0) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_OFFS (0xaa0) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x) ((x) + 0xaa4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_PHYS(x) ((x) + 0xaa4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_OFFS (0xaa4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xaa8) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xaa8) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_OFFS (0xaa8) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xaac) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xaac) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_OFFS (0xaac) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xab0) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xab0) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_OFFS (0xab0) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_ADDR(x) ((x) + 0xab4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_PHYS(x) ((x) + 0xab4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_OFFS (0xab4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xac4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xac4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_OFFS (0xac4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_ADDR(x) ((x) + 0xac8) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_PHYS(x) ((x) + 0xac8) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_OFFS (0xac8) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0xd0c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_PHYS(x) ((x) + 0xd0c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_OFFS (0xd0c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x) ((x) + 0xd10) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_PHYS(x) ((x) + 0xd10) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_OFFS (0xd10) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x) ((x) + 0xd14) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_PHYS(x) ((x) + 0xd14) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_OFFS (0xd14) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x) ((x) + 0xd18) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_PHYS(x) ((x) + 0xd18) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_OFFS (0xd18) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x) ((x) + 0xd1c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_PHYS(x) ((x) + 0xd1c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_OFFS (0xd1c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xd20) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xd20) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_OFFS (0xd20) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xd24) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xd24) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_OFFS (0xd24) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xd28) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xd28) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_OFFS (0xd28) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xd2c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xd2c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_OFFS (0xd2c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xd30) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xd30) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_OFFS (0xd30) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xd34) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xd34) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_OFFS (0xd34) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xd38) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xd38) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_OFFS (0xd38) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xd3c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xd3c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xd3c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xd40) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xd40) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xd40) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xd44) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xd44) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_OFFS (0xd44) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xd48) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xd48) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xd48) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xd4c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xd4c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xd4c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xd50) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xd50) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xd50) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff00000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 20 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xd54) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xd54) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_OFFS (0xd54) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xd58) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xd58) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_OFFS (0xd58) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_ADDR(x) ((x) + 0xd5c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_PHYS(x) ((x) + 0xd5c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_OFFS (0xd5c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xdd8) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0xdd8) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_OFFS (0xdd8) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0xddc) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0xddc) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_OFFS (0xddc) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x) ((x) + 0xde0) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_PHYS(x) ((x) + 0xde0) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_OFFS (0xde0) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x) ((x) + 0xde4) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_PHYS(x) ((x) + 0xde4) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_OFFS (0xde4) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x) ((x) + 0xde8) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_PHYS(x) ((x) + 0xde8) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_OFFS (0xde8) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xdec) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xdec) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_OFFS (0xdec) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xdf0) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xdf0) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_OFFS (0xdf0) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xdfc) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xdfc) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0xdfc) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xe00) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xe00) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0xe00) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xe04) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xe04) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0xe04) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xe20) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xe20) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_OFFS (0xe20) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xe24) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xe24) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_OFFS (0xe24) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0xe28) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0xe28) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_OFFS (0xe28) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xe2c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xe2c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0xe2c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xe30) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xe30) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_OFFS (0xe30) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xe34) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xe34) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_OFFS (0xe34) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0xe38) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0xe38) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_OFFS (0xe38) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xe48) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xe48) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0xe48) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0xe4c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0xe4c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_OFFS (0xe4c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xe50) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0xe50) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_OFFS (0xe50) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0xe54) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0xe54) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_OFFS (0xe54) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x) ((x) + 0xe58) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_PHYS(x) ((x) + 0xe58) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_OFFS (0xe58) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x) ((x) + 0xe5c) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_PHYS(x) ((x) + 0xe5c) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_OFFS (0xe5c) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x) ((x) + 0xe60) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_PHYS(x) ((x) + 0xe60) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_OFFS (0xe60) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xe64) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xe64) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_OFFS (0xe64) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xe68) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xe68) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_OFFS (0xe68) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xe74) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xe74) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0xe74) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xe78) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xe78) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0xe78) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xe7c) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xe7c) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0xe7c) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xe98) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xe98) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_OFFS (0xe98) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xe9c) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xe9c) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_OFFS (0xe9c) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0xea0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0xea0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_OFFS (0xea0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xea4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xea4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0xea4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xea8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xea8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_OFFS (0xea8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xeac) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xeac) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_OFFS (0xeac) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0xeb0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0xeb0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_OFFS (0xeb0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xec0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xec0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0xec0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0xec4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0xec4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_OFFS (0xec4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xec8) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0xec8) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_OFFS (0xec8) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0xecc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0xecc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_OFFS (0xecc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x) ((x) + 0xed0) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_PHYS(x) ((x) + 0xed0) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_OFFS (0xed0) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x) ((x) + 0xed4) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_PHYS(x) ((x) + 0xed4) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_OFFS (0xed4) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x) ((x) + 0xed8) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_PHYS(x) ((x) + 0xed8) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_OFFS (0xed8) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xedc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xedc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_OFFS (0xedc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xee0) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xee0) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_OFFS (0xee0) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xeec) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xeec) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0xeec) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xef0) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xef0) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0xef0) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xef4) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xef4) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0xef4) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xf10) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xf10) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_OFFS (0xf10) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xf14) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xf14) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_OFFS (0xf14) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0xf18) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0xf18) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_OFFS (0xf18) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xf1c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xf1c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0xf1c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xf20) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xf20) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_OFFS (0xf20) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xf24) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xf24) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_OFFS (0xf24) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0xf28) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0xf28) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_OFFS (0xf28) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xf38) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xf38) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0xf38) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0xf3c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0xf3c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_OFFS (0xf3c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xf40) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0xf40) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_OFFS (0xf40) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0xf44) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0xf44) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_OFFS (0xf44) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x) ((x) + 0xf48) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_PHYS(x) ((x) + 0xf48) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_OFFS (0xf48) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x) ((x) + 0xf4c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_PHYS(x) ((x) + 0xf4c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_OFFS (0xf4c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x) ((x) + 0xf50) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_PHYS(x) ((x) + 0xf50) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_OFFS (0xf50) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xf54) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xf54) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_OFFS (0xf54) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xf58) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xf58) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_OFFS (0xf58) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xf64) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xf64) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0xf64) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xf68) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xf68) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0xf68) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xf6c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xf6c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0xf6c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xf88) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xf88) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_OFFS (0xf88) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xf8c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xf8c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_OFFS (0xf8c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0xf90) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0xf90) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_OFFS (0xf90) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xf94) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xf94) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0xf94) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xf98) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xf98) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_OFFS (0xf98) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xf9c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xf9c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_OFFS (0xf9c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0xfa0) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0xfa0) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_OFFS (0xfa0) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xfb0) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xfb0) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0xfb0) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0xfb4) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0xfb4) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_OFFS (0xfb4) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xfb8) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0xfb8) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_OFFS (0xfb8) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0xfbc) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0xfbc) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_OFFS (0xfbc) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ADDR(x) ((x) + 0xfc0) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_PHYS(x) ((x) + 0xfc0) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_OFFS (0xfc0) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_ADDR(x) ((x) + 0xfc4) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_PHYS(x) ((x) + 0xfc4) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_OFFS (0xfc4) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADDR(x) ((x) + 0xfc8) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_PHYS(x) ((x) + 0xfc8) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_OFFS (0xfc8) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xfcc) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xfcc) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_OFFS (0xfcc) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xfd0) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xfd0) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_OFFS (0xfd0) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xfdc) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xfdc) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0xfdc) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xfe0) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xfe0) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0xfe0) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xfe4) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xfe4) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0xfe4) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x1000) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x1000) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x1000) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x1004) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x1004) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x1004) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x1008) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x1008) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_OFFS (0x1008) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x100c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x100c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x100c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x1010) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x1010) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x1010) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x1014) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x1014) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x1014) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x1018) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x1018) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_OFFS (0x1018) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x1028) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x1028) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x1028) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x102c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x102c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_OFFS (0x102c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x1030) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x1030) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_OFFS (0x1030) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x1034) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x1034) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_OFFS (0x1034) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_ADDR(x) ((x) + 0x1038) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_PHYS(x) ((x) + 0x1038) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_OFFS (0x1038) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x103c) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x103c) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_OFFS (0x103c) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_ADDR(x) ((x) + 0x1040) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_PHYS(x) ((x) + 0x1040) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_OFFS (0x1040) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x1044) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x1044) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_OFFS (0x1044) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x1048) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x1048) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_OFFS (0x1048) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x1054) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x1054) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x1054) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x1058) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x1058) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x1058) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x105c) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x105c) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x105c) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x1078) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x1078) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x1078) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x107c) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x107c) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x107c) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x1080) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x1080) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_OFFS (0x1080) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x1084) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x1084) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x1084) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x1088) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x1088) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x1088) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x108c) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x108c) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x108c) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x1090) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x1090) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_OFFS (0x1090) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x10a0) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x10a0) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x10a0) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x10a4) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x10a4) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_OFFS (0x10a4) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x10a8) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x10a8) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_OFFS (0x10a8) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x10ac) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x10ac) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_OFFS (0x10ac) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_ADDR(x) ((x) + 0x10b0) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_PHYS(x) ((x) + 0x10b0) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_OFFS (0x10b0) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x10b4) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x10b4) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_OFFS (0x10b4) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_ADDR(x) ((x) + 0x10b8) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_PHYS(x) ((x) + 0x10b8) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_OFFS (0x10b8) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x10bc) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x10bc) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_OFFS (0x10bc) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x10c0) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x10c0) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_OFFS (0x10c0) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x10cc) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x10cc) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x10cc) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x10d0) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x10d0) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x10d0) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x10d4) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x10d4) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x10d4) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x10f0) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x10f0) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x10f0) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x10f4) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x10f4) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x10f4) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x10f8) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x10f8) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_OFFS (0x10f8) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x10fc) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x10fc) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x10fc) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x1100) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x1100) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x1100) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x1104) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x1104) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x1104) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x1108) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x1108) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_OFFS (0x1108) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x1118) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x1118) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x1118) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x111c) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x111c) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_OFFS (0x111c) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x) ((x) + 0x3010) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_PHYS(x) ((x) + 0x3010) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_OFFS (0x3010) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_SW_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x) ((x) + 0x3014) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_PHYS(x) ((x) + 0x3014) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_OFFS (0x3014) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_SW_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_SW1_RELEASE_RING_HP_ADDR(x) ((x) + 0x3018) +#define HWIO_WBM_R2_SW1_RELEASE_RING_HP_PHYS(x) ((x) + 0x3018) +#define HWIO_WBM_R2_SW1_RELEASE_RING_HP_OFFS (0x3018) +#define HWIO_WBM_R2_SW1_RELEASE_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_SW1_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_SW1_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_SW1_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_SW1_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_SW1_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_SW1_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_SW1_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_SW1_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_SW1_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_SW1_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_SW1_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_SW1_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_SW1_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_SW1_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_SW1_RELEASE_RING_TP_ADDR(x) ((x) + 0x301c) +#define HWIO_WBM_R2_SW1_RELEASE_RING_TP_PHYS(x) ((x) + 0x301c) +#define HWIO_WBM_R2_SW1_RELEASE_RING_TP_OFFS (0x301c) +#define HWIO_WBM_R2_SW1_RELEASE_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_SW1_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_SW1_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_SW1_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_SW1_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_SW1_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_SW1_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_SW1_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_SW1_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_SW1_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_SW1_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_SW1_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_SW1_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_SW1_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_SW1_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x) ((x) + 0x3020) +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_PHYS(x) ((x) + 0x3020) +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_OFFS (0x3020) +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_PPE_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x) ((x) + 0x3024) +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_PHYS(x) ((x) + 0x3024) +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_OFFS (0x3024) +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_PPE_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x) ((x) + 0x30b8) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_PHYS(x) ((x) + 0x30b8) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_OFFS (0x30b8) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x) ((x) + 0x30bc) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_PHYS(x) ((x) + 0x30bc) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_OFFS (0x30bc) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x) ((x) + 0x30c8) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_PHYS(x) ((x) + 0x30c8) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_OFFS (0x30c8) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x) ((x) + 0x30cc) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_PHYS(x) ((x) + 0x30cc) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_OFFS (0x30cc) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x) ((x) + 0x30d0) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_PHYS(x) ((x) + 0x30d0) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_OFFS (0x30d0) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x) ((x) + 0x30d4) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_PHYS(x) ((x) + 0x30d4) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_OFFS (0x30d4) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x) ((x) + 0x30d8) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_PHYS(x) ((x) + 0x30d8) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_OFFS (0x30d8) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x) ((x) + 0x30dc) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_PHYS(x) ((x) + 0x30dc) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_OFFS (0x30dc) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x) ((x) + 0x30e0) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_PHYS(x) ((x) + 0x30e0) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_OFFS (0x30e0) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x) ((x) + 0x30e4) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_PHYS(x) ((x) + 0x30e4) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_OFFS (0x30e4) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ADDR(x) ((x) + 0x30e8) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_PHYS(x) ((x) + 0x30e8) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_OFFS (0x30e8) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ADDR(x) ((x) + 0x30ec) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_PHYS(x) ((x) + 0x30ec) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_OFFS (0x30ec) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_ADDR(x) ((x) + 0x30f0) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_PHYS(x) ((x) + 0x30f0) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_OFFS (0x30f0) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_ADDR(x) ((x) + 0x30f4) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_PHYS(x) ((x) + 0x30f4) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_OFFS (0x30f4) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_ADDR(x) ((x) + 0x30f8) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_PHYS(x) ((x) + 0x30f8) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_OFFS (0x30f8) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_ADDR(x) ((x) + 0x30fc) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_PHYS(x) ((x) + 0x30fc) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_OFFS (0x30fc) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define REO_REG_REG_BASE (UMAC_BASE + 0x00038000) +#define REO_REG_REG_BASE_SIZE 0x4000 +#define REO_REG_REG_BASE_USED 0x30ac +#define REO_REG_REG_BASE_PHYS (UMAC_BASE_PHYS + 0x00038000) +#define REO_REG_REG_BASE_OFFS 0x00038000 + +#define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x) ((x) + 0x0) +#define HWIO_REO_R0_GENERAL_ENABLE_PHYS(x) ((x) + 0x0) +#define HWIO_REO_R0_GENERAL_ENABLE_OFFS (0x0) +#define HWIO_REO_R0_GENERAL_ENABLE_RMSK 0xffffffff +#define HWIO_REO_R0_GENERAL_ENABLE_POR 0x00000100 +#define HWIO_REO_R0_GENERAL_ENABLE_POR_RMSK 0xffffffff +#define HWIO_REO_R0_GENERAL_ENABLE_ATTR 0x3 +#define HWIO_REO_R0_GENERAL_ENABLE_IN(x) \ + in_dword(HWIO_REO_R0_GENERAL_ENABLE_ADDR(x)) +#define HWIO_REO_R0_GENERAL_ENABLE_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), m) +#define HWIO_REO_R0_GENERAL_ENABLE_OUT(x, v) \ + out_dword(HWIO_REO_R0_GENERAL_ENABLE_ADDR(x),v) +#define HWIO_REO_R0_GENERAL_ENABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_GENERAL_ENABLE_ADDR(x),m,v,HWIO_REO_R0_GENERAL_ENABLE_IN(x)) +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO1_RING_ENABLE_BMSK 0x80000000 +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO1_RING_ENABLE_SHFT 31 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW6_RING_ENABLE_BMSK 0x40000000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW6_RING_ENABLE_SHFT 30 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW5_RING_ENABLE_BMSK 0x20000000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW5_RING_ENABLE_SHFT 29 +#define HWIO_REO_R0_GENERAL_ENABLE_INVALIDATE_CACHE_FOR_ZERO_VLD_BMSK 0x10000000 +#define HWIO_REO_R0_GENERAL_ENABLE_INVALIDATE_CACHE_FOR_ZERO_VLD_SHFT 28 +#define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_BMSK 0x8000000 +#define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_SHFT 27 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW8_RING_ENABLE_BMSK 0x4000000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW8_RING_ENABLE_SHFT 26 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW7_RING_ENABLE_BMSK 0x2000000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW7_RING_ENABLE_SHFT 25 +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO3_RING_ENABLE_BMSK 0x1000000 +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO3_RING_ENABLE_SHFT 24 +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO2_RING_ENABLE_BMSK 0x800000 +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO2_RING_ENABLE_SHFT 23 +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_BMSK 0x400000 +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_SHFT 22 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_BMSK 0x200000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_SHFT 21 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_BMSK 0x100000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_SHFT 20 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_BMSK 0x80000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_SHFT 19 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW0_RING_ENABLE_BMSK 0x40000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW0_RING_ENABLE_SHFT 18 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_BMSK 0x20000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_SHFT 17 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_BMSK 0x10000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_SHFT 16 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_BMSK 0x8000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_SHFT 15 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_BMSK 0x4000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_SHFT 14 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_BMSK 0x2000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_SHFT 13 +#define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_BMSK 0x1000 +#define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_SHFT 12 +#define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_BMSK 0xe00 +#define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_SHFT 9 +#define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_BMSK 0x100 +#define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_SHFT 8 +#define HWIO_REO_R0_GENERAL_ENABLE_BACKUP_1_BMSK 0xe0 +#define HWIO_REO_R0_GENERAL_ENABLE_BACKUP_1_SHFT 5 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2PPE_RING_ENABLE_BMSK 0x10 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2PPE_RING_ENABLE_SHFT 4 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK 0x8 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_SHFT 3 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK 0x4 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_SHFT 2 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_SHFT 1 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_BMSK 0x1 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_SHFT 0 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x) ((x) + 0xd50) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_PHYS(x) ((x) + 0xd50) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_OFFS (0xd50) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK 0xffffffff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_POR 0x008609ff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_POR_RMSK 0xffffffff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_ATTR 0x3 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x) \ +in_dword(HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x)) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_INM(x, m) \ +in_dword_masked(HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), m) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_OUT(x, v) \ +out_dword(HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x),v) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_OUTM(x,m,v) \ +out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x),m,v,HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x)) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_DESC_TYPE_SWAP_BMSK 0xff000000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_DESC_TYPE_SWAP_SHFT 24 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_ENABLE_LEGACY_SWAP_BMSK 0x800000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_ENABLE_LEGACY_SWAP_SHFT 23 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_BMSK 0x400000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_SHFT 22 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_BMSK 0x200000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_SHFT 21 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_BMSK 0x100000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_SHFT 20 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_BMSK 0x80000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_SHFT 19 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_BMSK 0x40000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_SHFT 18 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_BMSK 0x20000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_SHFT 17 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_BMSK 0x1fe00 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_SHFT 9 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_BMSK 0x1ff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_SHFT 0 + +#define HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x) ((x) + 0xd54) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_PHYS(x) ((x) + 0xd54) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_OFFS (0xd54) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK 0x3 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_POR 0x00000000 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_POR_RMSK 0xffffffff +#define HWIO_REO_R0_CACHE_CTL_CONTROL_ATTR 0x3 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x) \ +in_dword(HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x)) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_INM(x, m) \ +in_dword_masked(HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), m) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_OUT(x, v) \ +out_dword(HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x),v) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_OUTM(x,m,v) \ +out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x),m,v,HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x)) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH_BMSK 0x2 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH_SHFT 1 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_BMSK 0x1 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_SHFT 0 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x) ((x) + 0xd58) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_PHYS(x) ((x) + 0xd58) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_OFFS (0xd58) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_RMSK 0x1ffffff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_POR 0x00000000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ATTR 0x3 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_IN(x) \ +in_dword(HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x)) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_INM(x, m) \ +in_dword_masked(HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), m) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_OUT(x, v) \ +out_dword(HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x),v) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_OUTM(x,m,v) \ +out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x),m,v,HWIO_REO_R0_CACHE_CTL_CONFIG_SET_IN(x)) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CONFIG_SET_BMSK 0x1ffffff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CONFIG_SET_SHFT 0 + +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x) ((x) + 0xd5c) +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_PHYS(x) ((x) + 0xd5c) +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_OFFS (0xd5c) +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_RMSK 0x3ff +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_POR 0x000000f0 +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_POR_RMSK 0xffffffff +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_ATTR 0x3 +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_IN(x) \ +in_dword(HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x)) +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_INM(x, m) \ +in_dword_masked(HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), m) +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_OUT(x, v) \ +out_dword(HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x),v) +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_OUTM(x,m,v) \ +out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x),m,v,HWIO_REO_R0_CACHE_CTL_SET_SIZE_IN(x)) +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SET1_SIZE_BMSK 0x3ff +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SET1_SIZE_SHFT 0 + +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x) ((x) + 0xd60) +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_PHYS(x) ((x) + 0xd60) +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_OFFS (0xd60) +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_RMSK 0x7 +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_POR 0x00000002 +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_POR_RMSK 0xffffffff +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_ATTR 0x3 +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_IN(x) \ +in_dword(HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x)) +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_INM(x, m) \ +in_dword_masked(HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x), m) +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_OUT(x, v) \ +out_dword(HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x),v) +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_OUTM(x,m,v) \ +out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x),m,v,HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_IN(x)) +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_VC_ID_BMSK 0x4 +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_VC_ID_SHFT 2 +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_GXI_PRIORITY_BMSK 0x3 +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_GXI_PRIORITY_SHFT 0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x) ((x) + 0x4) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_PHYS(x) ((x) + 0x4) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OFFS (0x4) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_POR 0x76543210 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x) ((x) + 0x8) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_PHYS(x) ((x) + 0x8) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OFFS (0x8) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_POR 0x6666ba98 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x) ((x) + 0xc) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_PHYS(x) ((x) + 0xc) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OFFS (0xc) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_POR 0x66666666 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x) ((x) + 0x10) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_PHYS(x) ((x) + 0x10) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OFFS (0x10) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_POR 0x66666666 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT 0 + +#define HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x50) +#define HWIO_REO_R0_SW_COOKIE_CFG0_PHYS(x) ((x) + 0x50) +#define HWIO_REO_R0_SW_COOKIE_CFG0_OFFS (0x50) +#define HWIO_REO_R0_SW_COOKIE_CFG0_RMSK 0xffffffff +#define HWIO_REO_R0_SW_COOKIE_CFG0_POR 0x00000000 +#define HWIO_REO_R0_SW_COOKIE_CFG0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW_COOKIE_CFG0_ATTR 0x3 +#define HWIO_REO_R0_SW_COOKIE_CFG0_IN(x) \ + in_dword(HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x)) +#define HWIO_REO_R0_SW_COOKIE_CFG0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x), m) +#define HWIO_REO_R0_SW_COOKIE_CFG0_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x),v) +#define HWIO_REO_R0_SW_COOKIE_CFG0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x),m,v,HWIO_REO_R0_SW_COOKIE_CFG0_IN(x)) +#define HWIO_REO_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_BMSK 0xffffffff +#define HWIO_REO_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_SHFT 0 + +#define HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x54) +#define HWIO_REO_R0_SW_COOKIE_CFG1_PHYS(x) ((x) + 0x54) +#define HWIO_REO_R0_SW_COOKIE_CFG1_OFFS (0x54) +#define HWIO_REO_R0_SW_COOKIE_CFG1_RMSK 0x1fffff +#define HWIO_REO_R0_SW_COOKIE_CFG1_POR 0x00111700 +#define HWIO_REO_R0_SW_COOKIE_CFG1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW_COOKIE_CFG1_ATTR 0x3 +#define HWIO_REO_R0_SW_COOKIE_CFG1_IN(x) \ + in_dword(HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x)) +#define HWIO_REO_R0_SW_COOKIE_CFG1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x), m) +#define HWIO_REO_R0_SW_COOKIE_CFG1_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x),v) +#define HWIO_REO_R0_SW_COOKIE_CFG1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x),m,v,HWIO_REO_R0_SW_COOKIE_CFG1_IN(x)) +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_BMSK 0x100000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_SHFT 20 +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_BMSK 0x80000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_SHFT 19 +#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 +#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff +#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 + +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(x) ((x) + 0x58) +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_PHYS(x) ((x) + 0x58) +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_OFFS (0x58) +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_RMSK 0xffffffff +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_POR 0x00000000 +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ATTR 0x3 +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_IN(x) \ + in_dword(HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(x)) +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(x), m) +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_OUT(x, v) \ + out_dword(HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(x),v) +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(x),m,v,HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_IN(x)) +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_VALUE_SHFT 0 + +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(x) ((x) + 0x5c) +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_PHYS(x) ((x) + 0x5c) +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_OFFS (0x5c) +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_RMSK 0xffffffff +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_POR 0x00000000 +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ATTR 0x3 +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_IN(x) \ + in_dword(HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(x)) +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(x), m) +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_OUT(x, v) \ + out_dword(HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(x),v) +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(x),m,v,HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_IN(x)) +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_VALUE_SHFT 0 + +#define HWIO_REO_R0_QDESC_ADDR_READ_ADDR(x) ((x) + 0x60) +#define HWIO_REO_R0_QDESC_ADDR_READ_PHYS(x) ((x) + 0x60) +#define HWIO_REO_R0_QDESC_ADDR_READ_OFFS (0x60) +#define HWIO_REO_R0_QDESC_ADDR_READ_RMSK 0x1ff +#define HWIO_REO_R0_QDESC_ADDR_READ_POR 0x00000000 +#define HWIO_REO_R0_QDESC_ADDR_READ_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QDESC_ADDR_READ_ATTR 0x3 +#define HWIO_REO_R0_QDESC_ADDR_READ_IN(x) \ + in_dword(HWIO_REO_R0_QDESC_ADDR_READ_ADDR(x)) +#define HWIO_REO_R0_QDESC_ADDR_READ_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QDESC_ADDR_READ_ADDR(x), m) +#define HWIO_REO_R0_QDESC_ADDR_READ_OUT(x, v) \ + out_dword(HWIO_REO_R0_QDESC_ADDR_READ_ADDR(x),v) +#define HWIO_REO_R0_QDESC_ADDR_READ_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_QDESC_ADDR_READ_ADDR(x),m,v,HWIO_REO_R0_QDESC_ADDR_READ_IN(x)) +#define HWIO_REO_R0_QDESC_ADDR_READ_GXI_SWAP_BMSK 0x100 +#define HWIO_REO_R0_QDESC_ADDR_READ_GXI_SWAP_SHFT 8 +#define HWIO_REO_R0_QDESC_ADDR_READ_LUT_FEATURE_ENABLE_BMSK 0x80 +#define HWIO_REO_R0_QDESC_ADDR_READ_LUT_FEATURE_ENABLE_SHFT 7 +#define HWIO_REO_R0_QDESC_ADDR_READ_CLEAR_QDESC_ARRAY_BMSK 0x40 +#define HWIO_REO_R0_QDESC_ADDR_READ_CLEAR_QDESC_ARRAY_SHFT 6 +#define HWIO_REO_R0_QDESC_ADDR_READ_INDEX_BMSK 0x3f +#define HWIO_REO_R0_QDESC_ADDR_READ_INDEX_SHFT 0 + +#define HWIO_REO_R0_QDESC_ADDR_LOWER_ADDR(x) ((x) + 0x64) +#define HWIO_REO_R0_QDESC_ADDR_LOWER_PHYS(x) ((x) + 0x64) +#define HWIO_REO_R0_QDESC_ADDR_LOWER_OFFS (0x64) +#define HWIO_REO_R0_QDESC_ADDR_LOWER_RMSK 0xffffffff +#define HWIO_REO_R0_QDESC_ADDR_LOWER_POR 0x00000000 +#define HWIO_REO_R0_QDESC_ADDR_LOWER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QDESC_ADDR_LOWER_ATTR 0x1 +#define HWIO_REO_R0_QDESC_ADDR_LOWER_IN(x) \ + in_dword(HWIO_REO_R0_QDESC_ADDR_LOWER_ADDR(x)) +#define HWIO_REO_R0_QDESC_ADDR_LOWER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QDESC_ADDR_LOWER_ADDR(x), m) +#define HWIO_REO_R0_QDESC_ADDR_LOWER_QDESC_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_QDESC_ADDR_LOWER_QDESC_ADDR_SHFT 0 + +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_ADDR(x) ((x) + 0x68) +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_PHYS(x) ((x) + 0x68) +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_OFFS (0x68) +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_RMSK 0x3ffffff +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_POR 0x00000000 +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_ATTR 0x1 +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_IN(x) \ + in_dword(HWIO_REO_R0_QDESC_ADDR_HIGHER_ADDR(x)) +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QDESC_ADDR_HIGHER_ADDR(x), m) +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_Q_INDEX_BMSK 0x3ffff00 +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_Q_INDEX_SHFT 8 +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_QDESC_ADDR_BMSK 0xff +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_QDESC_ADDR_SHFT 0 + +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ADDR(x) ((x) + 0x6c) +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_PHYS(x) ((x) + 0x6c) +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_OFFS (0x6c) +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_RMSK 0x1fff +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_POR 0x00000000 +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ATTR 0x3 +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_IN(x) \ + in_dword(HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ADDR(x)) +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ADDR(x), m) +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ADDR(x),v) +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ADDR(x),m,v,HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_IN(x)) +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_MAX_SUPPORTED_BMSK 0x1fff +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_MAX_SUPPORTED_SHFT 0 + +#define HWIO_REO_R0_RX_STATS_CMD_ADDR(x) ((x) + 0x70) +#define HWIO_REO_R0_RX_STATS_CMD_PHYS(x) ((x) + 0x70) +#define HWIO_REO_R0_RX_STATS_CMD_OFFS (0x70) +#define HWIO_REO_R0_RX_STATS_CMD_RMSK 0xff +#define HWIO_REO_R0_RX_STATS_CMD_POR 0x00000000 +#define HWIO_REO_R0_RX_STATS_CMD_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RX_STATS_CMD_ATTR 0x3 +#define HWIO_REO_R0_RX_STATS_CMD_IN(x) \ + in_dword(HWIO_REO_R0_RX_STATS_CMD_ADDR(x)) +#define HWIO_REO_R0_RX_STATS_CMD_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RX_STATS_CMD_ADDR(x), m) +#define HWIO_REO_R0_RX_STATS_CMD_OUT(x, v) \ + out_dword(HWIO_REO_R0_RX_STATS_CMD_ADDR(x),v) +#define HWIO_REO_R0_RX_STATS_CMD_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RX_STATS_CMD_ADDR(x),m,v,HWIO_REO_R0_RX_STATS_CMD_IN(x)) +#define HWIO_REO_R0_RX_STATS_CMD_CLEAR_ALL_VDEV_ID_RX_STATS_BMSK 0x80 +#define HWIO_REO_R0_RX_STATS_CMD_CLEAR_ALL_VDEV_ID_RX_STATS_SHFT 7 +#define HWIO_REO_R0_RX_STATS_CMD_CLEAR_SINGLE_VDEV_RX_STATS_BMSK 0x40 +#define HWIO_REO_R0_RX_STATS_CMD_CLEAR_SINGLE_VDEV_RX_STATS_SHFT 6 +#define HWIO_REO_R0_RX_STATS_CMD_VDEV_ID_BMSK 0x3f +#define HWIO_REO_R0_RX_STATS_CMD_VDEV_ID_SHFT 0 + +#define HWIO_REO_R0_RX_STATS_LOWER_ADDR(x) ((x) + 0x74) +#define HWIO_REO_R0_RX_STATS_LOWER_PHYS(x) ((x) + 0x74) +#define HWIO_REO_R0_RX_STATS_LOWER_OFFS (0x74) +#define HWIO_REO_R0_RX_STATS_LOWER_RMSK 0xffffffff +#define HWIO_REO_R0_RX_STATS_LOWER_POR 0x00000000 +#define HWIO_REO_R0_RX_STATS_LOWER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RX_STATS_LOWER_ATTR 0x1 +#define HWIO_REO_R0_RX_STATS_LOWER_IN(x) \ + in_dword(HWIO_REO_R0_RX_STATS_LOWER_ADDR(x)) +#define HWIO_REO_R0_RX_STATS_LOWER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RX_STATS_LOWER_ADDR(x), m) +#define HWIO_REO_R0_RX_STATS_LOWER_MSDU_BYTE_COUNT_BMSK 0xffffffff +#define HWIO_REO_R0_RX_STATS_LOWER_MSDU_BYTE_COUNT_SHFT 0 + +#define HWIO_REO_R0_RX_STATS_HIGHER_ADDR(x) ((x) + 0x78) +#define HWIO_REO_R0_RX_STATS_HIGHER_PHYS(x) ((x) + 0x78) +#define HWIO_REO_R0_RX_STATS_HIGHER_OFFS (0x78) +#define HWIO_REO_R0_RX_STATS_HIGHER_RMSK 0xffffffff +#define HWIO_REO_R0_RX_STATS_HIGHER_POR 0x00000000 +#define HWIO_REO_R0_RX_STATS_HIGHER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RX_STATS_HIGHER_ATTR 0x1 +#define HWIO_REO_R0_RX_STATS_HIGHER_IN(x) \ + in_dword(HWIO_REO_R0_RX_STATS_HIGHER_ADDR(x)) +#define HWIO_REO_R0_RX_STATS_HIGHER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RX_STATS_HIGHER_ADDR(x), m) +#define HWIO_REO_R0_RX_STATS_HIGHER_MSDU_COUNT_BMSK 0xfffffff0 +#define HWIO_REO_R0_RX_STATS_HIGHER_MSDU_COUNT_SHFT 4 +#define HWIO_REO_R0_RX_STATS_HIGHER_MSDU_BYTE_COUNT_BMSK 0xf +#define HWIO_REO_R0_RX_STATS_HIGHER_MSDU_BYTE_COUNT_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x) ((x) + 0x28c) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_PHYS(x) ((x) + 0x28c) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OFFS (0x28c) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x) ((x) + 0x290) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_PHYS(x) ((x) + 0x290) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OFFS (0x290) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x) ((x) + 0x294) +#define HWIO_REO_R0_REO_CMD_RING_ID_PHYS(x) ((x) + 0x294) +#define HWIO_REO_R0_REO_CMD_RING_ID_OFFS (0x294) +#define HWIO_REO_R0_REO_CMD_RING_ID_RMSK 0xff +#define HWIO_REO_R0_REO_CMD_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_ID_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x) ((x) + 0x298) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_PHYS(x) ((x) + 0x298) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_OFFS (0x298) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x) ((x) + 0x29c) +#define HWIO_REO_R0_REO_CMD_RING_MISC_PHYS(x) ((x) + 0x29c) +#define HWIO_REO_R0_REO_CMD_RING_MISC_OFFS (0x29c) +#define HWIO_REO_R0_REO_CMD_RING_MISC_RMSK 0x3fffff +#define HWIO_REO_R0_REO_CMD_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO_CMD_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x2a8) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x2a8) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OFFS (0x2a8) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x2ac) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x2ac) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OFFS (0x2ac) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x2bc) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x2bc) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x2bc) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x2c0) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x2c0) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x2c0) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x2c4) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x2c4) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OFFS (0x2c4) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x2c8) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x2c8) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x2c8) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x2cc) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x2cc) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x2cc) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x2d0) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x2d0) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x2d0) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x2d4) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x2d4) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OFFS (0x2d4) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x2d8) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x2d8) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OFFS (0x2d8) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x) ((x) + 0x2dc) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_PHYS(x) ((x) + 0x2dc) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OFFS (0x2dc) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x2fc) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x2fc) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OFFS (0x2fc) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_ADDR(x) ((x) + 0x300) +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_PHYS(x) ((x) + 0x300) +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_OFFS (0x300) +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x) ((x) + 0x304) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_PHYS(x) ((x) + 0x304) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OFFS (0x304) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x) ((x) + 0x308) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_PHYS(x) ((x) + 0x308) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OFFS (0x308) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_ID_ADDR(x) ((x) + 0x30c) +#define HWIO_REO_R0_SW2REO_RING_ID_PHYS(x) ((x) + 0x30c) +#define HWIO_REO_R0_SW2REO_RING_ID_OFFS (0x30c) +#define HWIO_REO_R0_SW2REO_RING_ID_RMSK 0xff +#define HWIO_REO_R0_SW2REO_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_ID_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_ID_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_ID_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x) ((x) + 0x310) +#define HWIO_REO_R0_SW2REO_RING_STATUS_PHYS(x) ((x) + 0x310) +#define HWIO_REO_R0_SW2REO_RING_STATUS_OFFS (0x310) +#define HWIO_REO_R0_SW2REO_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_SW2REO_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x) ((x) + 0x314) +#define HWIO_REO_R0_SW2REO_RING_MISC_PHYS(x) ((x) + 0x314) +#define HWIO_REO_R0_SW2REO_RING_MISC_OFFS (0x314) +#define HWIO_REO_R0_SW2REO_RING_MISC_RMSK 0x3fffff +#define HWIO_REO_R0_SW2REO_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_SW2REO_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_MISC_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_SW2REO_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x320) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x320) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OFFS (0x320) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x324) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x324) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OFFS (0x324) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x334) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x334) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x334) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x338) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x338) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x338) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x33c) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x33c) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OFFS (0x33c) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x340) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x340) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x340) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x344) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x344) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x344) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x348) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x348) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x348) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x34c) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x34c) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OFFS (0x34c) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x350) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x350) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OFFS (0x350) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x) ((x) + 0x354) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_PHYS(x) ((x) + 0x354) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OFFS (0x354) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x374) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x374) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OFFS (0x374) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_MISC_1_ADDR(x) ((x) + 0x378) +#define HWIO_REO_R0_SW2REO_RING_MISC_1_PHYS(x) ((x) + 0x378) +#define HWIO_REO_R0_SW2REO_RING_MISC_1_OFFS (0x378) +#define HWIO_REO_R0_SW2REO_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_SW2REO_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_SW2REO_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_SW2REO_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x) ((x) + 0x37c) +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_PHYS(x) ((x) + 0x37c) +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_OFFS (0x37c) +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x) ((x) + 0x380) +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_PHYS(x) ((x) + 0x380) +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_OFFS (0x380) +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x) ((x) + 0x384) +#define HWIO_REO_R0_SW2REO1_RING_ID_PHYS(x) ((x) + 0x384) +#define HWIO_REO_R0_SW2REO1_RING_ID_OFFS (0x384) +#define HWIO_REO_R0_SW2REO1_RING_ID_RMSK 0xff +#define HWIO_REO_R0_SW2REO1_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_ID_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_SW2REO1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x) ((x) + 0x388) +#define HWIO_REO_R0_SW2REO1_RING_STATUS_PHYS(x) ((x) + 0x388) +#define HWIO_REO_R0_SW2REO1_RING_STATUS_OFFS (0x388) +#define HWIO_REO_R0_SW2REO1_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_SW2REO1_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x) ((x) + 0x38c) +#define HWIO_REO_R0_SW2REO1_RING_MISC_PHYS(x) ((x) + 0x38c) +#define HWIO_REO_R0_SW2REO1_RING_MISC_OFFS (0x38c) +#define HWIO_REO_R0_SW2REO1_RING_MISC_RMSK 0x3fffff +#define HWIO_REO_R0_SW2REO1_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_SW2REO1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_MISC_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_SW2REO1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_SW2REO1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_SW2REO1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_SW2REO1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_SW2REO1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_SW2REO1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_SW2REO1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_SW2REO1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_SW2REO1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_SW2REO1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x398) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x398) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_OFFS (0x398) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x39c) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x39c) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_OFFS (0x39c) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x3ac) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x3ac) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x3ac) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x3b0) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x3b0) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x3b0) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x3b4) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x3b4) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_OFFS (0x3b4) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3b8) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3b8) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3b8) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x3bc) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x3bc) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x3bc) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x3c0) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x3c0) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x3c0) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x3c4) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x3c4) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_OFFS (0x3c4) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x3c8) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x3c8) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_OFFS (0x3c8) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x) ((x) + 0x3cc) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_PHYS(x) ((x) + 0x3cc) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_OFFS (0x3cc) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x3ec) +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x3ec) +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_OFFS (0x3ec) +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_ADDR(x) ((x) + 0x3f0) +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_PHYS(x) ((x) + 0x3f0) +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_OFFS (0x3f0) +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_SW2REO2_RING_BASE_LSB_ADDR(x) ((x) + 0x3f4) +#define HWIO_REO_R0_SW2REO2_RING_BASE_LSB_PHYS(x) ((x) + 0x3f4) +#define HWIO_REO_R0_SW2REO2_RING_BASE_LSB_OFFS (0x3f4) +#define HWIO_REO_R0_SW2REO2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO2_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO2_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO2_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO2_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO2_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO2_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO2_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO2_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO2_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO2_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_SW2REO2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO2_RING_BASE_MSB_ADDR(x) ((x) + 0x3f8) +#define HWIO_REO_R0_SW2REO2_RING_BASE_MSB_PHYS(x) ((x) + 0x3f8) +#define HWIO_REO_R0_SW2REO2_RING_BASE_MSB_OFFS (0x3f8) +#define HWIO_REO_R0_SW2REO2_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_REO_R0_SW2REO2_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO2_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO2_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO2_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO2_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO2_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO2_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO2_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO2_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO2_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO2_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_SW2REO2_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_SW2REO2_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_SW2REO2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_SW2REO2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO2_RING_ID_ADDR(x) ((x) + 0x3fc) +#define HWIO_REO_R0_SW2REO2_RING_ID_PHYS(x) ((x) + 0x3fc) +#define HWIO_REO_R0_SW2REO2_RING_ID_OFFS (0x3fc) +#define HWIO_REO_R0_SW2REO2_RING_ID_RMSK 0xff +#define HWIO_REO_R0_SW2REO2_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_SW2REO2_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_SW2REO2_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO2_RING_ID_ADDR(x)) +#define HWIO_REO_R0_SW2REO2_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO2_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_SW2REO2_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO2_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_SW2REO2_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO2_RING_ID_ADDR(x),m,v,HWIO_REO_R0_SW2REO2_RING_ID_IN(x)) +#define HWIO_REO_R0_SW2REO2_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_SW2REO2_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_SW2REO2_RING_STATUS_ADDR(x) ((x) + 0x400) +#define HWIO_REO_R0_SW2REO2_RING_STATUS_PHYS(x) ((x) + 0x400) +#define HWIO_REO_R0_SW2REO2_RING_STATUS_OFFS (0x400) +#define HWIO_REO_R0_SW2REO2_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_SW2REO2_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_SW2REO2_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO2_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_SW2REO2_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO2_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_SW2REO2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_SW2REO2_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_SW2REO2_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_SW2REO2_RING_MISC_ADDR(x) ((x) + 0x404) +#define HWIO_REO_R0_SW2REO2_RING_MISC_PHYS(x) ((x) + 0x404) +#define HWIO_REO_R0_SW2REO2_RING_MISC_OFFS (0x404) +#define HWIO_REO_R0_SW2REO2_RING_MISC_RMSK 0x3fffff +#define HWIO_REO_R0_SW2REO2_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_SW2REO2_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_SW2REO2_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO2_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_SW2REO2_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO2_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_SW2REO2_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO2_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_SW2REO2_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO2_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_SW2REO2_RING_MISC_IN(x)) +#define HWIO_REO_R0_SW2REO2_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_SW2REO2_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_SW2REO2_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_SW2REO2_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_SW2REO2_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_SW2REO2_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_SW2REO2_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_SW2REO2_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_SW2REO2_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_SW2REO2_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_SW2REO2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_SW2REO2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_SW2REO2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_SW2REO2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_SW2REO2_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_SW2REO2_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_SW2REO2_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_SW2REO2_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_SW2REO2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_SW2REO2_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_SW2REO2_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_SW2REO2_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_SW2REO2_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x410) +#define HWIO_REO_R0_SW2REO2_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x410) +#define HWIO_REO_R0_SW2REO2_RING_TP_ADDR_LSB_OFFS (0x410) +#define HWIO_REO_R0_SW2REO2_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO2_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO2_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO2_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO2_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO2_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO2_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO2_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO2_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO2_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO2_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_SW2REO2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO2_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x414) +#define HWIO_REO_R0_SW2REO2_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x414) +#define HWIO_REO_R0_SW2REO2_RING_TP_ADDR_MSB_OFFS (0x414) +#define HWIO_REO_R0_SW2REO2_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_SW2REO2_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO2_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO2_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO2_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO2_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO2_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO2_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO2_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO2_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO2_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO2_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_SW2REO2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_SW2REO2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x424) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x424) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x424) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x428) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x428) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x428) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x42c) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x42c) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_STATUS_OFFS (0x42c) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x430) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x430) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x430) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_SW2REO2_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x434) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x434) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x434) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x438) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x438) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x438) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R0_SW2REO2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x43c) +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x43c) +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_LSB_OFFS (0x43c) +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x440) +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x440) +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_MSB_OFFS (0x440) +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_SW2REO2_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_SW2REO2_RING_MSI1_DATA_ADDR(x) ((x) + 0x444) +#define HWIO_REO_R0_SW2REO2_RING_MSI1_DATA_PHYS(x) ((x) + 0x444) +#define HWIO_REO_R0_SW2REO2_RING_MSI1_DATA_OFFS (0x444) +#define HWIO_REO_R0_SW2REO2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_SW2REO2_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_SW2REO2_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO2_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_SW2REO2_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO2_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_SW2REO2_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO2_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_SW2REO2_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO2_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_SW2REO2_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_SW2REO2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_SW2REO2_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x464) +#define HWIO_REO_R0_SW2REO2_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x464) +#define HWIO_REO_R0_SW2REO2_RING_HP_TP_SW_OFFSET_OFFS (0x464) +#define HWIO_REO_R0_SW2REO2_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_SW2REO2_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_SW2REO2_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_SW2REO2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO2_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_SW2REO2_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_SW2REO2_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO2_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_SW2REO2_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO2_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_SW2REO2_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_SW2REO2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_SW2REO2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_SW2REO2_RING_MISC_1_ADDR(x) ((x) + 0x468) +#define HWIO_REO_R0_SW2REO2_RING_MISC_1_PHYS(x) ((x) + 0x468) +#define HWIO_REO_R0_SW2REO2_RING_MISC_1_OFFS (0x468) +#define HWIO_REO_R0_SW2REO2_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_SW2REO2_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_SW2REO2_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO2_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_SW2REO2_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO2_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_SW2REO2_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO2_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_SW2REO2_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO2_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_SW2REO2_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO2_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_SW2REO2_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_SW2REO2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_SW2REO2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_SW2REO2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_SW2REO3_RING_BASE_LSB_ADDR(x) ((x) + 0x46c) +#define HWIO_REO_R0_SW2REO3_RING_BASE_LSB_PHYS(x) ((x) + 0x46c) +#define HWIO_REO_R0_SW2REO3_RING_BASE_LSB_OFFS (0x46c) +#define HWIO_REO_R0_SW2REO3_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO3_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO3_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO3_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO3_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO3_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO3_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO3_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO3_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO3_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO3_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_SW2REO3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO3_RING_BASE_MSB_ADDR(x) ((x) + 0x470) +#define HWIO_REO_R0_SW2REO3_RING_BASE_MSB_PHYS(x) ((x) + 0x470) +#define HWIO_REO_R0_SW2REO3_RING_BASE_MSB_OFFS (0x470) +#define HWIO_REO_R0_SW2REO3_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_REO_R0_SW2REO3_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO3_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO3_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO3_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO3_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO3_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO3_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO3_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO3_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO3_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO3_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_SW2REO3_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_SW2REO3_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_SW2REO3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_SW2REO3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO3_RING_ID_ADDR(x) ((x) + 0x474) +#define HWIO_REO_R0_SW2REO3_RING_ID_PHYS(x) ((x) + 0x474) +#define HWIO_REO_R0_SW2REO3_RING_ID_OFFS (0x474) +#define HWIO_REO_R0_SW2REO3_RING_ID_RMSK 0xff +#define HWIO_REO_R0_SW2REO3_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_SW2REO3_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_SW2REO3_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO3_RING_ID_ADDR(x)) +#define HWIO_REO_R0_SW2REO3_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO3_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_SW2REO3_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO3_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_SW2REO3_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO3_RING_ID_ADDR(x),m,v,HWIO_REO_R0_SW2REO3_RING_ID_IN(x)) +#define HWIO_REO_R0_SW2REO3_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_SW2REO3_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_SW2REO3_RING_STATUS_ADDR(x) ((x) + 0x478) +#define HWIO_REO_R0_SW2REO3_RING_STATUS_PHYS(x) ((x) + 0x478) +#define HWIO_REO_R0_SW2REO3_RING_STATUS_OFFS (0x478) +#define HWIO_REO_R0_SW2REO3_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_SW2REO3_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_SW2REO3_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO3_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_SW2REO3_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO3_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_SW2REO3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_SW2REO3_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_SW2REO3_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_SW2REO3_RING_MISC_ADDR(x) ((x) + 0x47c) +#define HWIO_REO_R0_SW2REO3_RING_MISC_PHYS(x) ((x) + 0x47c) +#define HWIO_REO_R0_SW2REO3_RING_MISC_OFFS (0x47c) +#define HWIO_REO_R0_SW2REO3_RING_MISC_RMSK 0x3fffff +#define HWIO_REO_R0_SW2REO3_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_SW2REO3_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_SW2REO3_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO3_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_SW2REO3_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO3_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_SW2REO3_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO3_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_SW2REO3_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO3_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_SW2REO3_RING_MISC_IN(x)) +#define HWIO_REO_R0_SW2REO3_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_SW2REO3_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_SW2REO3_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_SW2REO3_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_SW2REO3_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_SW2REO3_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_SW2REO3_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_SW2REO3_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_SW2REO3_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_SW2REO3_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_SW2REO3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_SW2REO3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_SW2REO3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_SW2REO3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_SW2REO3_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_SW2REO3_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_SW2REO3_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_SW2REO3_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_SW2REO3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_SW2REO3_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_SW2REO3_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_SW2REO3_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_SW2REO3_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x488) +#define HWIO_REO_R0_SW2REO3_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x488) +#define HWIO_REO_R0_SW2REO3_RING_TP_ADDR_LSB_OFFS (0x488) +#define HWIO_REO_R0_SW2REO3_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO3_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO3_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO3_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO3_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO3_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO3_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO3_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO3_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO3_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO3_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_SW2REO3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO3_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x48c) +#define HWIO_REO_R0_SW2REO3_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x48c) +#define HWIO_REO_R0_SW2REO3_RING_TP_ADDR_MSB_OFFS (0x48c) +#define HWIO_REO_R0_SW2REO3_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_SW2REO3_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO3_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO3_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO3_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO3_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO3_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO3_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO3_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO3_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO3_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO3_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_SW2REO3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_SW2REO3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x49c) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x49c) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x49c) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x4a0) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x4a0) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x4a0) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x4a4) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x4a4) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_STATUS_OFFS (0x4a4) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x4a8) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x4a8) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x4a8) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_SW2REO3_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x4ac) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x4ac) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x4ac) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x4b0) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x4b0) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x4b0) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R0_SW2REO3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x4b4) +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x4b4) +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_LSB_OFFS (0x4b4) +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4b8) +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4b8) +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_MSB_OFFS (0x4b8) +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_SW2REO3_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_SW2REO3_RING_MSI1_DATA_ADDR(x) ((x) + 0x4bc) +#define HWIO_REO_R0_SW2REO3_RING_MSI1_DATA_PHYS(x) ((x) + 0x4bc) +#define HWIO_REO_R0_SW2REO3_RING_MSI1_DATA_OFFS (0x4bc) +#define HWIO_REO_R0_SW2REO3_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_SW2REO3_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_SW2REO3_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO3_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_SW2REO3_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO3_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_SW2REO3_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO3_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_SW2REO3_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO3_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_SW2REO3_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_SW2REO3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_SW2REO3_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x4dc) +#define HWIO_REO_R0_SW2REO3_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x4dc) +#define HWIO_REO_R0_SW2REO3_RING_HP_TP_SW_OFFSET_OFFS (0x4dc) +#define HWIO_REO_R0_SW2REO3_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_SW2REO3_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_SW2REO3_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_SW2REO3_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO3_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_SW2REO3_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO3_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_SW2REO3_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO3_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_SW2REO3_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO3_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_SW2REO3_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_SW2REO3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_SW2REO3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_SW2REO3_RING_MISC_1_ADDR(x) ((x) + 0x4e0) +#define HWIO_REO_R0_SW2REO3_RING_MISC_1_PHYS(x) ((x) + 0x4e0) +#define HWIO_REO_R0_SW2REO3_RING_MISC_1_OFFS (0x4e0) +#define HWIO_REO_R0_SW2REO3_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_SW2REO3_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_SW2REO3_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO3_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_SW2REO3_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO3_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_SW2REO3_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO3_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_SW2REO3_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO3_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_SW2REO3_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO3_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_SW2REO3_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_SW2REO3_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO3_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_SW2REO3_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_SW2REO3_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x) ((x) + 0x4e4) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_PHYS(x) ((x) + 0x4e4) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OFFS (0x4e4) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x) ((x) + 0x4e8) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_PHYS(x) ((x) + 0x4e8) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OFFS (0x4e8) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x) ((x) + 0x4ec) +#define HWIO_REO_R0_REO2SW1_RING_ID_PHYS(x) ((x) + 0x4ec) +#define HWIO_REO_R0_REO2SW1_RING_ID_OFFS (0x4ec) +#define HWIO_REO_R0_REO2SW1_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2SW1_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x) ((x) + 0x4f0) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_PHYS(x) ((x) + 0x4f0) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_OFFS (0x4f0) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) ((x) + 0x4f4) +#define HWIO_REO_R0_REO2SW1_RING_MISC_PHYS(x) ((x) + 0x4f4) +#define HWIO_REO_R0_REO2SW1_RING_MISC_OFFS (0x4f4) +#define HWIO_REO_R0_REO2SW1_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2SW1_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2SW1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x4f8) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x4f8) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OFFS (0x4f8) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x4fc) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x4fc) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OFFS (0x4fc) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x508) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x508) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OFFS (0x508) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x50c) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x50c) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OFFS (0x50c) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x510) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x510) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OFFS (0x510) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x52c) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x52c) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OFFS (0x52c) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x530) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x530) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OFFS (0x530) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) ((x) + 0x534) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_PHYS(x) ((x) + 0x534) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OFFS (0x534) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x538) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x538) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_OFFS (0x538) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x53c) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x53c) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_OFFS (0x53c) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x540) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x540) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_OFFS (0x540) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x) ((x) + 0x544) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_PHYS(x) ((x) + 0x544) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_OFFS (0x544) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x554) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x554) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OFFS (0x554) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x) ((x) + 0x558) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_PHYS(x) ((x) + 0x558) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_OFFS (0x558) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) ((x) + 0x55c) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_PHYS(x) ((x) + 0x55c) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OFFS (0x55c) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x) ((x) + 0x560) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_PHYS(x) ((x) + 0x560) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OFFS (0x560) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x) ((x) + 0x564) +#define HWIO_REO_R0_REO2SW2_RING_ID_PHYS(x) ((x) + 0x564) +#define HWIO_REO_R0_REO2SW2_RING_ID_OFFS (0x564) +#define HWIO_REO_R0_REO2SW2_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2SW2_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x) ((x) + 0x568) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_PHYS(x) ((x) + 0x568) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_OFFS (0x568) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x) ((x) + 0x56c) +#define HWIO_REO_R0_REO2SW2_RING_MISC_PHYS(x) ((x) + 0x56c) +#define HWIO_REO_R0_REO2SW2_RING_MISC_OFFS (0x56c) +#define HWIO_REO_R0_REO2SW2_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2SW2_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2SW2_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2SW2_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x570) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x570) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OFFS (0x570) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x574) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x574) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OFFS (0x574) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x580) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x580) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OFFS (0x580) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x584) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x584) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OFFS (0x584) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x588) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x588) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OFFS (0x588) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x5a4) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x5a4) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OFFS (0x5a4) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x5a8) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x5a8) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OFFS (0x5a8) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x) ((x) + 0x5ac) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_PHYS(x) ((x) + 0x5ac) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OFFS (0x5ac) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x5b0) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x5b0) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_OFFS (0x5b0) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x5b4) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x5b4) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_OFFS (0x5b4) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x5b8) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x5b8) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_OFFS (0x5b8) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_ADDR(x) ((x) + 0x5bc) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_PHYS(x) ((x) + 0x5bc) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_OFFS (0x5bc) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x5cc) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x5cc) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OFFS (0x5cc) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_ADDR(x) ((x) + 0x5d0) +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_PHYS(x) ((x) + 0x5d0) +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_OFFS (0x5d0) +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x) ((x) + 0x5d4) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_PHYS(x) ((x) + 0x5d4) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OFFS (0x5d4) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x) ((x) + 0x5d8) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_PHYS(x) ((x) + 0x5d8) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OFFS (0x5d8) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x) ((x) + 0x5dc) +#define HWIO_REO_R0_REO2SW3_RING_ID_PHYS(x) ((x) + 0x5dc) +#define HWIO_REO_R0_REO2SW3_RING_ID_OFFS (0x5dc) +#define HWIO_REO_R0_REO2SW3_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2SW3_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x) ((x) + 0x5e0) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_PHYS(x) ((x) + 0x5e0) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_OFFS (0x5e0) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x) ((x) + 0x5e4) +#define HWIO_REO_R0_REO2SW3_RING_MISC_PHYS(x) ((x) + 0x5e4) +#define HWIO_REO_R0_REO2SW3_RING_MISC_OFFS (0x5e4) +#define HWIO_REO_R0_REO2SW3_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2SW3_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2SW3_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2SW3_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x5e8) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x5e8) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OFFS (0x5e8) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x5ec) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x5ec) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OFFS (0x5ec) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x5f8) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x5f8) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OFFS (0x5f8) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x5fc) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x5fc) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OFFS (0x5fc) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x600) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x600) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OFFS (0x600) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x61c) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x61c) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OFFS (0x61c) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x620) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x620) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OFFS (0x620) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x) ((x) + 0x624) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_PHYS(x) ((x) + 0x624) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OFFS (0x624) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x628) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x628) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_OFFS (0x628) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x62c) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x62c) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_OFFS (0x62c) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x630) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x630) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_OFFS (0x630) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_ADDR(x) ((x) + 0x634) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_PHYS(x) ((x) + 0x634) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_OFFS (0x634) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x644) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x644) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OFFS (0x644) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_ADDR(x) ((x) + 0x648) +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_PHYS(x) ((x) + 0x648) +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_OFFS (0x648) +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x) ((x) + 0x64c) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_PHYS(x) ((x) + 0x64c) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OFFS (0x64c) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x) ((x) + 0x650) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_PHYS(x) ((x) + 0x650) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OFFS (0x650) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x) ((x) + 0x654) +#define HWIO_REO_R0_REO2SW4_RING_ID_PHYS(x) ((x) + 0x654) +#define HWIO_REO_R0_REO2SW4_RING_ID_OFFS (0x654) +#define HWIO_REO_R0_REO2SW4_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2SW4_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x) ((x) + 0x658) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_PHYS(x) ((x) + 0x658) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_OFFS (0x658) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x) ((x) + 0x65c) +#define HWIO_REO_R0_REO2SW4_RING_MISC_PHYS(x) ((x) + 0x65c) +#define HWIO_REO_R0_REO2SW4_RING_MISC_OFFS (0x65c) +#define HWIO_REO_R0_REO2SW4_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2SW4_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2SW4_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2SW4_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x660) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x660) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OFFS (0x660) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x664) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x664) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OFFS (0x664) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x670) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x670) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OFFS (0x670) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x674) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x674) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OFFS (0x674) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x678) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x678) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OFFS (0x678) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x694) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x694) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OFFS (0x694) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x698) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x698) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OFFS (0x698) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x) ((x) + 0x69c) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_PHYS(x) ((x) + 0x69c) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OFFS (0x69c) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x6a0) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x6a0) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_OFFS (0x6a0) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x6a4) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x6a4) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_OFFS (0x6a4) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x6a8) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x6a8) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_OFFS (0x6a8) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_ADDR(x) ((x) + 0x6ac) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_PHYS(x) ((x) + 0x6ac) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_OFFS (0x6ac) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x6bc) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x6bc) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OFFS (0x6bc) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_ADDR(x) ((x) + 0x6c0) +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_PHYS(x) ((x) + 0x6c0) +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_OFFS (0x6c0) +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ADDR(x) ((x) + 0x6c4) +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_PHYS(x) ((x) + 0x6c4) +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_OFFS (0x6c4) +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ADDR(x) ((x) + 0x6c8) +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_PHYS(x) ((x) + 0x6c8) +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_OFFS (0x6c8) +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_ID_ADDR(x) ((x) + 0x6cc) +#define HWIO_REO_R0_REO2SW5_RING_ID_PHYS(x) ((x) + 0x6cc) +#define HWIO_REO_R0_REO2SW5_RING_ID_OFFS (0x6cc) +#define HWIO_REO_R0_REO2SW5_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2SW5_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2SW5_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2SW5_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2SW5_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_STATUS_ADDR(x) ((x) + 0x6d0) +#define HWIO_REO_R0_REO2SW5_RING_STATUS_PHYS(x) ((x) + 0x6d0) +#define HWIO_REO_R0_REO2SW5_RING_STATUS_OFFS (0x6d0) +#define HWIO_REO_R0_REO2SW5_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW5_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW5_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2SW5_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2SW5_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_MISC_ADDR(x) ((x) + 0x6d4) +#define HWIO_REO_R0_REO2SW5_RING_MISC_PHYS(x) ((x) + 0x6d4) +#define HWIO_REO_R0_REO2SW5_RING_MISC_OFFS (0x6d4) +#define HWIO_REO_R0_REO2SW5_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2SW5_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2SW5_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2SW5_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2SW5_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2SW5_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2SW5_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2SW5_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2SW5_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2SW5_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2SW5_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2SW5_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2SW5_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2SW5_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2SW5_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2SW5_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6d8) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6d8) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_OFFS (0x6d8) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x6dc) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x6dc) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_OFFS (0x6dc) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x6e8) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x6e8) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_OFFS (0x6e8) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x6ec) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x6ec) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_OFFS (0x6ec) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x6f0) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x6f0) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_OFFS (0x6f0) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x70c) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x70c) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_OFFS (0x70c) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x710) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x710) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_OFFS (0x710) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ADDR(x) ((x) + 0x714) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_PHYS(x) ((x) + 0x714) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_OFFS (0x714) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x718) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x718) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_OFFS (0x718) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x71c) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x71c) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_OFFS (0x71c) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x720) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x720) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_OFFS (0x720) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_ADDR(x) ((x) + 0x724) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_PHYS(x) ((x) + 0x724) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_OFFS (0x724) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x734) +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x734) +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_OFFS (0x734) +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_ADDR(x) ((x) + 0x738) +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_PHYS(x) ((x) + 0x738) +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_OFFS (0x738) +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ADDR(x) ((x) + 0x73c) +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_PHYS(x) ((x) + 0x73c) +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_OFFS (0x73c) +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ADDR(x) ((x) + 0x740) +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_PHYS(x) ((x) + 0x740) +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_OFFS (0x740) +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_ID_ADDR(x) ((x) + 0x744) +#define HWIO_REO_R0_REO2SW6_RING_ID_PHYS(x) ((x) + 0x744) +#define HWIO_REO_R0_REO2SW6_RING_ID_OFFS (0x744) +#define HWIO_REO_R0_REO2SW6_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2SW6_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2SW6_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2SW6_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2SW6_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_STATUS_ADDR(x) ((x) + 0x748) +#define HWIO_REO_R0_REO2SW6_RING_STATUS_PHYS(x) ((x) + 0x748) +#define HWIO_REO_R0_REO2SW6_RING_STATUS_OFFS (0x748) +#define HWIO_REO_R0_REO2SW6_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW6_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW6_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2SW6_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2SW6_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_MISC_ADDR(x) ((x) + 0x74c) +#define HWIO_REO_R0_REO2SW6_RING_MISC_PHYS(x) ((x) + 0x74c) +#define HWIO_REO_R0_REO2SW6_RING_MISC_OFFS (0x74c) +#define HWIO_REO_R0_REO2SW6_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2SW6_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2SW6_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2SW6_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2SW6_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2SW6_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2SW6_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2SW6_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2SW6_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2SW6_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2SW6_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2SW6_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2SW6_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2SW6_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2SW6_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2SW6_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x750) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x750) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_OFFS (0x750) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x754) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x754) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_OFFS (0x754) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x760) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x760) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_OFFS (0x760) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x764) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x764) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_OFFS (0x764) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x768) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x768) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_OFFS (0x768) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x784) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x784) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_OFFS (0x784) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x788) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x788) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_OFFS (0x788) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ADDR(x) ((x) + 0x78c) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_PHYS(x) ((x) + 0x78c) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_OFFS (0x78c) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x790) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x790) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_OFFS (0x790) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x794) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x794) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_OFFS (0x794) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x798) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x798) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_OFFS (0x798) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_ADDR(x) ((x) + 0x79c) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_PHYS(x) ((x) + 0x79c) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_OFFS (0x79c) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x7ac) +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x7ac) +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_OFFS (0x7ac) +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_ADDR(x) ((x) + 0x7b0) +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_PHYS(x) ((x) + 0x7b0) +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_OFFS (0x7b0) +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2SW7_RING_BASE_LSB_ADDR(x) ((x) + 0x7b4) +#define HWIO_REO_R0_REO2SW7_RING_BASE_LSB_PHYS(x) ((x) + 0x7b4) +#define HWIO_REO_R0_REO2SW7_RING_BASE_LSB_OFFS (0x7b4) +#define HWIO_REO_R0_REO2SW7_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW7_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW7_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW7_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW7_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW7_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW7_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW7_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW7_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW7_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW7_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW7_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW7_RING_BASE_MSB_ADDR(x) ((x) + 0x7b8) +#define HWIO_REO_R0_REO2SW7_RING_BASE_MSB_PHYS(x) ((x) + 0x7b8) +#define HWIO_REO_R0_REO2SW7_RING_BASE_MSB_OFFS (0x7b8) +#define HWIO_REO_R0_REO2SW7_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2SW7_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW7_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW7_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW7_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW7_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW7_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW7_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW7_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW7_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW7_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW7_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW7_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW7_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW7_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW7_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW7_RING_ID_ADDR(x) ((x) + 0x7bc) +#define HWIO_REO_R0_REO2SW7_RING_ID_PHYS(x) ((x) + 0x7bc) +#define HWIO_REO_R0_REO2SW7_RING_ID_OFFS (0x7bc) +#define HWIO_REO_R0_REO2SW7_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2SW7_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2SW7_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2SW7_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW7_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2SW7_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW7_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2SW7_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW7_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2SW7_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW7_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2SW7_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2SW7_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2SW7_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2SW7_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2SW7_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2SW7_RING_STATUS_ADDR(x) ((x) + 0x7c0) +#define HWIO_REO_R0_REO2SW7_RING_STATUS_PHYS(x) ((x) + 0x7c0) +#define HWIO_REO_R0_REO2SW7_RING_STATUS_OFFS (0x7c0) +#define HWIO_REO_R0_REO2SW7_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW7_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW7_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW7_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW7_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW7_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW7_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW7_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2SW7_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2SW7_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2SW7_RING_MISC_ADDR(x) ((x) + 0x7c4) +#define HWIO_REO_R0_REO2SW7_RING_MISC_PHYS(x) ((x) + 0x7c4) +#define HWIO_REO_R0_REO2SW7_RING_MISC_OFFS (0x7c4) +#define HWIO_REO_R0_REO2SW7_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2SW7_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2SW7_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2SW7_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW7_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2SW7_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW7_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2SW7_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW7_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2SW7_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW7_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2SW7_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2SW7_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2SW7_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2SW7_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2SW7_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2SW7_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2SW7_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2SW7_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2SW7_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2SW7_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2SW7_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2SW7_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2SW7_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2SW7_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2SW7_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2SW7_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2SW7_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2SW7_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2SW7_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2SW7_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2SW7_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2SW7_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2SW7_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2SW7_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2SW7_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2SW7_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2SW7_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2SW7_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x7c8) +#define HWIO_REO_R0_REO2SW7_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x7c8) +#define HWIO_REO_R0_REO2SW7_RING_HP_ADDR_LSB_OFFS (0x7c8) +#define HWIO_REO_R0_REO2SW7_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW7_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW7_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW7_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW7_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW7_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW7_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW7_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW7_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW7_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW7_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW7_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW7_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x7cc) +#define HWIO_REO_R0_REO2SW7_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x7cc) +#define HWIO_REO_R0_REO2SW7_RING_HP_ADDR_MSB_OFFS (0x7cc) +#define HWIO_REO_R0_REO2SW7_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2SW7_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW7_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW7_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW7_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW7_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW7_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW7_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW7_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW7_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW7_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW7_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW7_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW7_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7d8) +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7d8) +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_SETUP_OFFS (0x7d8) +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x7dc) +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x7dc) +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_STATUS_OFFS (0x7dc) +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x7e0) +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x7e0) +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_FULL_COUNTER_OFFS (0x7e0) +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW7_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW7_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW7_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW7_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2SW7_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x7fc) +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x7fc) +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_LSB_OFFS (0x7fc) +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x800) +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x800) +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_MSB_OFFS (0x800) +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW7_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW7_RING_MSI1_DATA_ADDR(x) ((x) + 0x804) +#define HWIO_REO_R0_REO2SW7_RING_MSI1_DATA_PHYS(x) ((x) + 0x804) +#define HWIO_REO_R0_REO2SW7_RING_MSI1_DATA_OFFS (0x804) +#define HWIO_REO_R0_REO2SW7_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW7_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW7_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW7_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW7_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW7_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW7_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW7_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW7_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW7_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW7_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW7_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x808) +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x808) +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT2_SETUP_OFFS (0x808) +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2SW7_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x80c) +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x80c) +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_LSB_OFFS (0x80c) +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x810) +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x810) +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_MSB_OFFS (0x810) +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW7_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW7_RING_MSI2_DATA_ADDR(x) ((x) + 0x814) +#define HWIO_REO_R0_REO2SW7_RING_MSI2_DATA_PHYS(x) ((x) + 0x814) +#define HWIO_REO_R0_REO2SW7_RING_MSI2_DATA_OFFS (0x814) +#define HWIO_REO_R0_REO2SW7_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW7_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW7_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW7_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW7_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW7_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW7_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW7_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW7_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW7_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW7_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW7_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW7_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x824) +#define HWIO_REO_R0_REO2SW7_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x824) +#define HWIO_REO_R0_REO2SW7_RING_HP_TP_SW_OFFSET_OFFS (0x824) +#define HWIO_REO_R0_REO2SW7_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2SW7_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2SW7_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2SW7_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW7_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2SW7_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW7_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2SW7_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW7_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2SW7_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW7_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2SW7_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2SW7_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2SW7_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW7_RING_MISC_1_ADDR(x) ((x) + 0x828) +#define HWIO_REO_R0_REO2SW7_RING_MISC_1_PHYS(x) ((x) + 0x828) +#define HWIO_REO_R0_REO2SW7_RING_MISC_1_OFFS (0x828) +#define HWIO_REO_R0_REO2SW7_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2SW7_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2SW7_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW7_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2SW7_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW7_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2SW7_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW7_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2SW7_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW7_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2SW7_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW7_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2SW7_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2SW7_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW7_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW7_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW7_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2SW8_RING_BASE_LSB_ADDR(x) ((x) + 0x82c) +#define HWIO_REO_R0_REO2SW8_RING_BASE_LSB_PHYS(x) ((x) + 0x82c) +#define HWIO_REO_R0_REO2SW8_RING_BASE_LSB_OFFS (0x82c) +#define HWIO_REO_R0_REO2SW8_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW8_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW8_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW8_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW8_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW8_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW8_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW8_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW8_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW8_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW8_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW8_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW8_RING_BASE_MSB_ADDR(x) ((x) + 0x830) +#define HWIO_REO_R0_REO2SW8_RING_BASE_MSB_PHYS(x) ((x) + 0x830) +#define HWIO_REO_R0_REO2SW8_RING_BASE_MSB_OFFS (0x830) +#define HWIO_REO_R0_REO2SW8_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2SW8_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW8_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW8_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW8_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW8_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW8_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW8_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW8_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW8_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW8_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW8_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW8_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW8_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW8_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW8_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW8_RING_ID_ADDR(x) ((x) + 0x834) +#define HWIO_REO_R0_REO2SW8_RING_ID_PHYS(x) ((x) + 0x834) +#define HWIO_REO_R0_REO2SW8_RING_ID_OFFS (0x834) +#define HWIO_REO_R0_REO2SW8_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2SW8_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2SW8_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2SW8_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW8_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2SW8_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW8_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2SW8_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW8_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2SW8_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW8_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2SW8_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2SW8_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2SW8_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2SW8_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2SW8_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2SW8_RING_STATUS_ADDR(x) ((x) + 0x838) +#define HWIO_REO_R0_REO2SW8_RING_STATUS_PHYS(x) ((x) + 0x838) +#define HWIO_REO_R0_REO2SW8_RING_STATUS_OFFS (0x838) +#define HWIO_REO_R0_REO2SW8_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW8_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW8_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW8_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW8_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW8_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW8_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW8_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2SW8_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2SW8_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2SW8_RING_MISC_ADDR(x) ((x) + 0x83c) +#define HWIO_REO_R0_REO2SW8_RING_MISC_PHYS(x) ((x) + 0x83c) +#define HWIO_REO_R0_REO2SW8_RING_MISC_OFFS (0x83c) +#define HWIO_REO_R0_REO2SW8_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2SW8_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2SW8_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2SW8_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW8_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2SW8_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW8_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2SW8_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW8_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2SW8_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW8_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2SW8_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2SW8_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2SW8_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2SW8_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2SW8_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2SW8_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2SW8_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2SW8_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2SW8_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2SW8_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2SW8_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2SW8_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2SW8_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2SW8_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2SW8_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2SW8_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2SW8_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2SW8_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2SW8_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2SW8_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2SW8_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2SW8_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2SW8_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2SW8_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2SW8_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2SW8_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2SW8_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2SW8_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x840) +#define HWIO_REO_R0_REO2SW8_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x840) +#define HWIO_REO_R0_REO2SW8_RING_HP_ADDR_LSB_OFFS (0x840) +#define HWIO_REO_R0_REO2SW8_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW8_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW8_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW8_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW8_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW8_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW8_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW8_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW8_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW8_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW8_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW8_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW8_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x844) +#define HWIO_REO_R0_REO2SW8_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x844) +#define HWIO_REO_R0_REO2SW8_RING_HP_ADDR_MSB_OFFS (0x844) +#define HWIO_REO_R0_REO2SW8_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2SW8_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW8_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW8_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW8_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW8_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW8_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW8_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW8_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW8_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW8_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW8_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW8_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW8_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x850) +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x850) +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_SETUP_OFFS (0x850) +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x854) +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x854) +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_STATUS_OFFS (0x854) +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x858) +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x858) +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_FULL_COUNTER_OFFS (0x858) +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW8_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW8_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW8_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW8_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2SW8_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x874) +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x874) +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_LSB_OFFS (0x874) +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x878) +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x878) +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_MSB_OFFS (0x878) +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW8_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW8_RING_MSI1_DATA_ADDR(x) ((x) + 0x87c) +#define HWIO_REO_R0_REO2SW8_RING_MSI1_DATA_PHYS(x) ((x) + 0x87c) +#define HWIO_REO_R0_REO2SW8_RING_MSI1_DATA_OFFS (0x87c) +#define HWIO_REO_R0_REO2SW8_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW8_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW8_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW8_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW8_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW8_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW8_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW8_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW8_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW8_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW8_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW8_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x880) +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x880) +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT2_SETUP_OFFS (0x880) +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2SW8_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x884) +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x884) +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_LSB_OFFS (0x884) +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x888) +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x888) +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_MSB_OFFS (0x888) +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW8_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW8_RING_MSI2_DATA_ADDR(x) ((x) + 0x88c) +#define HWIO_REO_R0_REO2SW8_RING_MSI2_DATA_PHYS(x) ((x) + 0x88c) +#define HWIO_REO_R0_REO2SW8_RING_MSI2_DATA_OFFS (0x88c) +#define HWIO_REO_R0_REO2SW8_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW8_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW8_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW8_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW8_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW8_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW8_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW8_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW8_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW8_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW8_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW8_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW8_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x89c) +#define HWIO_REO_R0_REO2SW8_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x89c) +#define HWIO_REO_R0_REO2SW8_RING_HP_TP_SW_OFFSET_OFFS (0x89c) +#define HWIO_REO_R0_REO2SW8_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2SW8_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2SW8_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2SW8_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW8_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2SW8_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW8_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2SW8_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW8_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2SW8_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW8_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2SW8_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2SW8_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2SW8_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW8_RING_MISC_1_ADDR(x) ((x) + 0x8a0) +#define HWIO_REO_R0_REO2SW8_RING_MISC_1_PHYS(x) ((x) + 0x8a0) +#define HWIO_REO_R0_REO2SW8_RING_MISC_1_OFFS (0x8a0) +#define HWIO_REO_R0_REO2SW8_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2SW8_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2SW8_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW8_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2SW8_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW8_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2SW8_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW8_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2SW8_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW8_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2SW8_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW8_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2SW8_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2SW8_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW8_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW8_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW8_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x) ((x) + 0x8a4) +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_PHYS(x) ((x) + 0x8a4) +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_OFFS (0x8a4) +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_ADDR(x) ((x) + 0x8a8) +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_PHYS(x) ((x) + 0x8a8) +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_OFFS (0x8a8) +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_ID_ADDR(x) ((x) + 0x8ac) +#define HWIO_REO_R0_REO2SW0_RING_ID_PHYS(x) ((x) + 0x8ac) +#define HWIO_REO_R0_REO2SW0_RING_ID_OFFS (0x8ac) +#define HWIO_REO_R0_REO2SW0_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2SW0_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2SW0_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2SW0_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2SW0_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_STATUS_ADDR(x) ((x) + 0x8b0) +#define HWIO_REO_R0_REO2SW0_RING_STATUS_PHYS(x) ((x) + 0x8b0) +#define HWIO_REO_R0_REO2SW0_RING_STATUS_OFFS (0x8b0) +#define HWIO_REO_R0_REO2SW0_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW0_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW0_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2SW0_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2SW0_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_MISC_ADDR(x) ((x) + 0x8b4) +#define HWIO_REO_R0_REO2SW0_RING_MISC_PHYS(x) ((x) + 0x8b4) +#define HWIO_REO_R0_REO2SW0_RING_MISC_OFFS (0x8b4) +#define HWIO_REO_R0_REO2SW0_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2SW0_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2SW0_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2SW0_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2SW0_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2SW0_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2SW0_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2SW0_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2SW0_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2SW0_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2SW0_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2SW0_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2SW0_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2SW0_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2SW0_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2SW0_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x8b8) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x8b8) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_OFFS (0x8b8) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x8bc) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x8bc) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_OFFS (0x8bc) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x8c8) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x8c8) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_OFFS (0x8c8) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x8cc) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x8cc) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_OFFS (0x8cc) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x8d0) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x8d0) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_OFFS (0x8d0) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x8ec) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x8ec) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_OFFS (0x8ec) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x8f0) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x8f0) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_OFFS (0x8f0) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_ADDR(x) ((x) + 0x8f4) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_PHYS(x) ((x) + 0x8f4) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_OFFS (0x8f4) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x8f8) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x8f8) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_OFFS (0x8f8) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x8fc) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x8fc) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_OFFS (0x8fc) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x900) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x900) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_OFFS (0x900) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_ADDR(x) ((x) + 0x904) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_PHYS(x) ((x) + 0x904) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_OFFS (0x904) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x914) +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x914) +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_OFFS (0x914) +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_ADDR(x) ((x) + 0x918) +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_PHYS(x) ((x) + 0x918) +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_OFFS (0x918) +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ADDR(x) ((x) + 0x91c) +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_PHYS(x) ((x) + 0x91c) +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_OFFS (0x91c) +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_ADDR(x) ((x) + 0x920) +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_PHYS(x) ((x) + 0x920) +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_OFFS (0x920) +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_ID_ADDR(x) ((x) + 0x924) +#define HWIO_REO_R0_REO2PPE_RING_ID_PHYS(x) ((x) + 0x924) +#define HWIO_REO_R0_REO2PPE_RING_ID_OFFS (0x924) +#define HWIO_REO_R0_REO2PPE_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2PPE_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2PPE_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2PPE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2PPE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_STATUS_ADDR(x) ((x) + 0x928) +#define HWIO_REO_R0_REO2PPE_RING_STATUS_PHYS(x) ((x) + 0x928) +#define HWIO_REO_R0_REO2PPE_RING_STATUS_OFFS (0x928) +#define HWIO_REO_R0_REO2PPE_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2PPE_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2PPE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2PPE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2PPE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_MISC_ADDR(x) ((x) + 0x92c) +#define HWIO_REO_R0_REO2PPE_RING_MISC_PHYS(x) ((x) + 0x92c) +#define HWIO_REO_R0_REO2PPE_RING_MISC_OFFS (0x92c) +#define HWIO_REO_R0_REO2PPE_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2PPE_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2PPE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2PPE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2PPE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2PPE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2PPE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2PPE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2PPE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2PPE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2PPE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2PPE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2PPE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2PPE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2PPE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2PPE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x930) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x930) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_OFFS (0x930) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x934) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x934) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_OFFS (0x934) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x940) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x940) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_OFFS (0x940) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x944) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x944) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_OFFS (0x944) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x948) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x948) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_OFFS (0x948) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x964) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x964) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_OFFS (0x964) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x968) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x968) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_OFFS (0x968) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_ADDR(x) ((x) + 0x96c) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_PHYS(x) ((x) + 0x96c) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_OFFS (0x96c) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x970) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x970) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_OFFS (0x970) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x974) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x974) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_OFFS (0x974) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x978) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x978) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_OFFS (0x978) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_ADDR(x) ((x) + 0x97c) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_PHYS(x) ((x) + 0x97c) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_OFFS (0x97c) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x98c) +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x98c) +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_OFFS (0x98c) +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_ADDR(x) ((x) + 0x990) +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_PHYS(x) ((x) + 0x990) +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_OFFS (0x990) +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0xa84) + +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0xa84) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OFFS (0xa84) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0xa88) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0xa88) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OFFS (0xa88) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x) ((x) + 0xa8c) +#define HWIO_REO_R0_REO_STATUS_RING_ID_PHYS(x) ((x) + 0xa8c) +#define HWIO_REO_R0_REO_STATUS_RING_ID_OFFS (0xa8c) +#define HWIO_REO_R0_REO_STATUS_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO_STATUS_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_ID_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x) ((x) + 0xa90) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_PHYS(x) ((x) + 0xa90) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_OFFS (0xa90) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x) ((x) + 0xa94) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_PHYS(x) ((x) + 0xa94) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_OFFS (0xa94) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO_STATUS_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xa98) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xa98) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OFFS (0xa98) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xa9c) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xa9c) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OFFS (0xa9c) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xaa8) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xaa8) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0xaa8) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xaac) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xaac) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0xaac) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xab0) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xab0) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0xab0) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xacc) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xacc) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OFFS (0xacc) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xad0) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xad0) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OFFS (0xad0) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xad4) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xad4) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OFFS (0xad4) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xad8) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xad8) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_OFFS (0xad8) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xadc) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xadc) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_OFFS (0xadc) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xae0) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xae0) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_OFFS (0xae0) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_ADDR(x) ((x) + 0xae4) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_PHYS(x) ((x) + 0xae4) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_OFFS (0xae4) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xaf4) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xaf4) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xaf4) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_ADDR(x) ((x) + 0xaf8) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_PHYS(x) ((x) + 0xaf8) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_OFFS (0xaf8) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x) ((x) + 0xb08) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_PHYS(x) ((x) + 0xb08) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OFFS (0xb08) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_POR 0x000186a0 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ATTR 0x3 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x)) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), m) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUT(x, v) \ + out_dword(HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x),v) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x),m,v,HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x)) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_SHFT 0 + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x) ((x) + 0xb0c) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_PHYS(x) ((x) + 0xb0c) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OFFS (0xb0c) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_POR 0x000186a0 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ATTR 0x3 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x)) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), m) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x),v) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x),m,v,HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x)) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_SHFT 0 + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x) ((x) + 0xb10) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_PHYS(x) ((x) + 0xb10) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OFFS (0xb10) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_POR 0x00009c40 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ATTR 0x3 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x)) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), m) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUT(x, v) \ + out_dword(HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x),v) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x),m,v,HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x)) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_SHFT 0 + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x) ((x) + 0xb14) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_PHYS(x) ((x) + 0xb14) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OFFS (0xb14) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_POR 0x00009c40 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ATTR 0x3 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x)) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), m) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUT(x, v) \ + out_dword(HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x),v) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x),m,v,HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x)) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_SHFT 0 + +#define HWIO_REO_R0_MISC_CTL_ADDR(x) ((x) + 0xb7c) +#define HWIO_REO_R0_MISC_CTL_PHYS(x) ((x) + 0xb7c) +#define HWIO_REO_R0_MISC_CTL_OFFS (0xb7c) +#define HWIO_REO_R0_MISC_CTL_RMSK 0x3fffffff +#define HWIO_REO_R0_MISC_CTL_POR 0x0cac0008 +#define HWIO_REO_R0_MISC_CTL_POR_RMSK 0xffffffff +#define HWIO_REO_R0_MISC_CTL_ATTR 0x3 +#define HWIO_REO_R0_MISC_CTL_IN(x) \ + in_dword(HWIO_REO_R0_MISC_CTL_ADDR(x)) +#define HWIO_REO_R0_MISC_CTL_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_MISC_CTL_ADDR(x), m) +#define HWIO_REO_R0_MISC_CTL_OUT(x, v) \ + out_dword(HWIO_REO_R0_MISC_CTL_ADDR(x),v) +#define HWIO_REO_R0_MISC_CTL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_MISC_CTL_ADDR(x),m,v,HWIO_REO_R0_MISC_CTL_IN(x)) +#define HWIO_REO_R0_MISC_CTL_WCSS_INDICATION_BMSK 0x20000000 +#define HWIO_REO_R0_MISC_CTL_WCSS_INDICATION_SHFT 29 +#define HWIO_REO_R0_MISC_CTL_SOFT_REORDER_DEST_RING_BMSK 0x1e000000 +#define HWIO_REO_R0_MISC_CTL_SOFT_REORDER_DEST_RING_SHFT 25 +#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_BMSK 0x1e00000 +#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_SHFT 21 +#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK 0x1e0000 +#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_SHFT 17 +#define HWIO_REO_R0_MISC_CTL_CACHE_FLUSH_Q_DESC_ONLY_BMSK 0x10000 +#define HWIO_REO_R0_MISC_CTL_CACHE_FLUSH_Q_DESC_ONLY_SHFT 16 +#define HWIO_REO_R0_MISC_CTL_MSI_ENABLE_CHK_BIT_BMSK 0x8000 +#define HWIO_REO_R0_MISC_CTL_MSI_ENABLE_CHK_BIT_SHFT 15 +#define HWIO_REO_R0_MISC_CTL_SPARE_CONTROL_BMSK 0x7fff +#define HWIO_REO_R0_MISC_CTL_SPARE_CONTROL_SHFT 0 + +#define HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x) ((x) + 0x3020) +#define HWIO_REO_R2_REO_CMD_RING_HP_PHYS(x) ((x) + 0x3020) +#define HWIO_REO_R2_REO_CMD_RING_HP_OFFS (0x3020) +#define HWIO_REO_R2_REO_CMD_RING_HP_RMSK 0xffff +#define HWIO_REO_R2_REO_CMD_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO_CMD_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO_CMD_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO_CMD_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO_CMD_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO_CMD_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO_CMD_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO_CMD_RING_HP_IN(x)) +#define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x) ((x) + 0x3024) +#define HWIO_REO_R2_REO_CMD_RING_TP_PHYS(x) ((x) + 0x3024) +#define HWIO_REO_R2_REO_CMD_RING_TP_OFFS (0x3024) +#define HWIO_REO_R2_REO_CMD_RING_TP_RMSK 0xffff +#define HWIO_REO_R2_REO_CMD_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO_CMD_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO_CMD_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO_CMD_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO_CMD_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO_CMD_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO_CMD_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO_CMD_RING_TP_IN(x)) +#define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x) ((x) + 0x3028) +#define HWIO_REO_R2_SW2REO_RING_HP_PHYS(x) ((x) + 0x3028) +#define HWIO_REO_R2_SW2REO_RING_HP_OFFS (0x3028) +#define HWIO_REO_R2_SW2REO_RING_HP_RMSK 0xffff +#define HWIO_REO_R2_SW2REO_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_SW2REO_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_SW2REO_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_SW2REO_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_SW2REO_RING_HP_ADDR(x)) +#define HWIO_REO_R2_SW2REO_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_SW2REO_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_SW2REO_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_SW2REO_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_HP_ADDR(x),m,v,HWIO_REO_R2_SW2REO_RING_HP_IN(x)) +#define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_SW2REO_RING_TP_ADDR(x) ((x) + 0x302c) +#define HWIO_REO_R2_SW2REO_RING_TP_PHYS(x) ((x) + 0x302c) +#define HWIO_REO_R2_SW2REO_RING_TP_OFFS (0x302c) +#define HWIO_REO_R2_SW2REO_RING_TP_RMSK 0xffff +#define HWIO_REO_R2_SW2REO_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_SW2REO_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_SW2REO_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_SW2REO_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_SW2REO_RING_TP_ADDR(x)) +#define HWIO_REO_R2_SW2REO_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_SW2REO_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_SW2REO_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_SW2REO_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_TP_ADDR(x),m,v,HWIO_REO_R2_SW2REO_RING_TP_IN(x)) +#define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x) ((x) + 0x3030) +#define HWIO_REO_R2_SW2REO1_RING_HP_PHYS(x) ((x) + 0x3030) +#define HWIO_REO_R2_SW2REO1_RING_HP_OFFS (0x3030) +#define HWIO_REO_R2_SW2REO1_RING_HP_RMSK 0xffff +#define HWIO_REO_R2_SW2REO1_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_SW2REO1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_SW2REO1_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_SW2REO1_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x)) +#define HWIO_REO_R2_SW2REO1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_SW2REO1_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_SW2REO1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x),m,v,HWIO_REO_R2_SW2REO1_RING_HP_IN(x)) +#define HWIO_REO_R2_SW2REO1_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_REO_R2_SW2REO1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x) ((x) + 0x3034) +#define HWIO_REO_R2_SW2REO1_RING_TP_PHYS(x) ((x) + 0x3034) +#define HWIO_REO_R2_SW2REO1_RING_TP_OFFS (0x3034) +#define HWIO_REO_R2_SW2REO1_RING_TP_RMSK 0xffff +#define HWIO_REO_R2_SW2REO1_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_SW2REO1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_SW2REO1_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_SW2REO1_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x)) +#define HWIO_REO_R2_SW2REO1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_SW2REO1_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_SW2REO1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x),m,v,HWIO_REO_R2_SW2REO1_RING_TP_IN(x)) +#define HWIO_REO_R2_SW2REO1_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R2_SW2REO1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_SW2REO2_RING_HP_ADDR(x) ((x) + 0x3038) +#define HWIO_REO_R2_SW2REO2_RING_HP_PHYS(x) ((x) + 0x3038) +#define HWIO_REO_R2_SW2REO2_RING_HP_OFFS (0x3038) +#define HWIO_REO_R2_SW2REO2_RING_HP_RMSK 0xffff +#define HWIO_REO_R2_SW2REO2_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_SW2REO2_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_SW2REO2_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_SW2REO2_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_SW2REO2_RING_HP_ADDR(x)) +#define HWIO_REO_R2_SW2REO2_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_SW2REO2_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_SW2REO2_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_SW2REO2_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_SW2REO2_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_SW2REO2_RING_HP_ADDR(x),m,v,HWIO_REO_R2_SW2REO2_RING_HP_IN(x)) +#define HWIO_REO_R2_SW2REO2_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_REO_R2_SW2REO2_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_SW2REO2_RING_TP_ADDR(x) ((x) + 0x303c) +#define HWIO_REO_R2_SW2REO2_RING_TP_PHYS(x) ((x) + 0x303c) +#define HWIO_REO_R2_SW2REO2_RING_TP_OFFS (0x303c) +#define HWIO_REO_R2_SW2REO2_RING_TP_RMSK 0xffff +#define HWIO_REO_R2_SW2REO2_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_SW2REO2_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_SW2REO2_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_SW2REO2_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_SW2REO2_RING_TP_ADDR(x)) +#define HWIO_REO_R2_SW2REO2_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_SW2REO2_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_SW2REO2_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_SW2REO2_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_SW2REO2_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_SW2REO2_RING_TP_ADDR(x),m,v,HWIO_REO_R2_SW2REO2_RING_TP_IN(x)) +#define HWIO_REO_R2_SW2REO2_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R2_SW2REO2_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_SW2REO3_RING_HP_ADDR(x) ((x) + 0x3040) +#define HWIO_REO_R2_SW2REO3_RING_HP_PHYS(x) ((x) + 0x3040) +#define HWIO_REO_R2_SW2REO3_RING_HP_OFFS (0x3040) +#define HWIO_REO_R2_SW2REO3_RING_HP_RMSK 0xffff +#define HWIO_REO_R2_SW2REO3_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_SW2REO3_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_SW2REO3_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_SW2REO3_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_SW2REO3_RING_HP_ADDR(x)) +#define HWIO_REO_R2_SW2REO3_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_SW2REO3_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_SW2REO3_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_SW2REO3_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_SW2REO3_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_SW2REO3_RING_HP_ADDR(x),m,v,HWIO_REO_R2_SW2REO3_RING_HP_IN(x)) +#define HWIO_REO_R2_SW2REO3_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_REO_R2_SW2REO3_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_SW2REO3_RING_TP_ADDR(x) ((x) + 0x3044) +#define HWIO_REO_R2_SW2REO3_RING_TP_PHYS(x) ((x) + 0x3044) +#define HWIO_REO_R2_SW2REO3_RING_TP_OFFS (0x3044) +#define HWIO_REO_R2_SW2REO3_RING_TP_RMSK 0xffff +#define HWIO_REO_R2_SW2REO3_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_SW2REO3_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_SW2REO3_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_SW2REO3_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_SW2REO3_RING_TP_ADDR(x)) +#define HWIO_REO_R2_SW2REO3_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_SW2REO3_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_SW2REO3_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_SW2REO3_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_SW2REO3_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_SW2REO3_RING_TP_ADDR(x),m,v,HWIO_REO_R2_SW2REO3_RING_TP_IN(x)) +#define HWIO_REO_R2_SW2REO3_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R2_SW2REO3_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x) ((x) + 0x3048) +#define HWIO_REO_R2_REO2SW1_RING_HP_PHYS(x) ((x) + 0x3048) +#define HWIO_REO_R2_REO2SW1_RING_HP_OFFS (0x3048) +#define HWIO_REO_R2_REO2SW1_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW1_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW1_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW1_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2SW1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW1_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2SW1_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x) ((x) + 0x304c) +#define HWIO_REO_R2_REO2SW1_RING_TP_PHYS(x) ((x) + 0x304c) +#define HWIO_REO_R2_REO2SW1_RING_TP_OFFS (0x304c) +#define HWIO_REO_R2_REO2SW1_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW1_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW1_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW1_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2SW1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW1_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2SW1_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x) ((x) + 0x3050) +#define HWIO_REO_R2_REO2SW2_RING_HP_PHYS(x) ((x) + 0x3050) +#define HWIO_REO_R2_REO2SW2_RING_HP_OFFS (0x3050) +#define HWIO_REO_R2_REO2SW2_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW2_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW2_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW2_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW2_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2SW2_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW2_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW2_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2SW2_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x) ((x) + 0x3054) +#define HWIO_REO_R2_REO2SW2_RING_TP_PHYS(x) ((x) + 0x3054) +#define HWIO_REO_R2_REO2SW2_RING_TP_OFFS (0x3054) +#define HWIO_REO_R2_REO2SW2_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW2_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW2_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW2_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW2_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2SW2_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW2_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW2_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2SW2_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x) ((x) + 0x3058) +#define HWIO_REO_R2_REO2SW3_RING_HP_PHYS(x) ((x) + 0x3058) +#define HWIO_REO_R2_REO2SW3_RING_HP_OFFS (0x3058) +#define HWIO_REO_R2_REO2SW3_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW3_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW3_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW3_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW3_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2SW3_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW3_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW3_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2SW3_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x) ((x) + 0x305c) +#define HWIO_REO_R2_REO2SW3_RING_TP_PHYS(x) ((x) + 0x305c) +#define HWIO_REO_R2_REO2SW3_RING_TP_OFFS (0x305c) +#define HWIO_REO_R2_REO2SW3_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW3_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW3_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW3_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW3_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2SW3_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW3_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW3_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2SW3_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x) ((x) + 0x3060) +#define HWIO_REO_R2_REO2SW4_RING_HP_PHYS(x) ((x) + 0x3060) +#define HWIO_REO_R2_REO2SW4_RING_HP_OFFS (0x3060) +#define HWIO_REO_R2_REO2SW4_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW4_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW4_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW4_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW4_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2SW4_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW4_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW4_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2SW4_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x) ((x) + 0x3064) +#define HWIO_REO_R2_REO2SW4_RING_TP_PHYS(x) ((x) + 0x3064) +#define HWIO_REO_R2_REO2SW4_RING_TP_OFFS (0x3064) +#define HWIO_REO_R2_REO2SW4_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW4_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW4_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW4_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW4_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2SW4_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW4_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW4_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2SW4_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW5_RING_HP_ADDR(x) ((x) + 0x3068) +#define HWIO_REO_R2_REO2SW5_RING_HP_PHYS(x) ((x) + 0x3068) +#define HWIO_REO_R2_REO2SW5_RING_HP_OFFS (0x3068) +#define HWIO_REO_R2_REO2SW5_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW5_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW5_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW5_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW5_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW5_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2SW5_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW5_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW5_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW5_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW5_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW5_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2SW5_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2SW5_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW5_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW5_RING_TP_ADDR(x) ((x) + 0x306c) +#define HWIO_REO_R2_REO2SW5_RING_TP_PHYS(x) ((x) + 0x306c) +#define HWIO_REO_R2_REO2SW5_RING_TP_OFFS (0x306c) +#define HWIO_REO_R2_REO2SW5_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW5_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW5_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW5_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW5_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW5_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2SW5_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW5_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW5_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW5_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW5_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW5_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2SW5_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2SW5_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW5_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW6_RING_HP_ADDR(x) ((x) + 0x3070) +#define HWIO_REO_R2_REO2SW6_RING_HP_PHYS(x) ((x) + 0x3070) +#define HWIO_REO_R2_REO2SW6_RING_HP_OFFS (0x3070) +#define HWIO_REO_R2_REO2SW6_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW6_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW6_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW6_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW6_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW6_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2SW6_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW6_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW6_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW6_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW6_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW6_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2SW6_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2SW6_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW6_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW6_RING_TP_ADDR(x) ((x) + 0x3074) +#define HWIO_REO_R2_REO2SW6_RING_TP_PHYS(x) ((x) + 0x3074) +#define HWIO_REO_R2_REO2SW6_RING_TP_OFFS (0x3074) +#define HWIO_REO_R2_REO2SW6_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW6_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW6_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW6_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW6_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW6_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2SW6_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW6_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW6_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW6_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW6_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW6_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2SW6_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2SW6_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW6_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW7_RING_HP_ADDR(x) ((x) + 0x3078) +#define HWIO_REO_R2_REO2SW7_RING_HP_PHYS(x) ((x) + 0x3078) +#define HWIO_REO_R2_REO2SW7_RING_HP_OFFS (0x3078) +#define HWIO_REO_R2_REO2SW7_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW7_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW7_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW7_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW7_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW7_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2SW7_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW7_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW7_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW7_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW7_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW7_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2SW7_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2SW7_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW7_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW7_RING_TP_ADDR(x) ((x) + 0x307c) +#define HWIO_REO_R2_REO2SW7_RING_TP_PHYS(x) ((x) + 0x307c) +#define HWIO_REO_R2_REO2SW7_RING_TP_OFFS (0x307c) +#define HWIO_REO_R2_REO2SW7_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW7_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW7_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW7_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW7_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW7_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2SW7_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW7_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW7_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW7_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW7_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW7_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2SW7_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2SW7_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW7_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW8_RING_HP_ADDR(x) ((x) + 0x3080) +#define HWIO_REO_R2_REO2SW8_RING_HP_PHYS(x) ((x) + 0x3080) +#define HWIO_REO_R2_REO2SW8_RING_HP_OFFS (0x3080) +#define HWIO_REO_R2_REO2SW8_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW8_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW8_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW8_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW8_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW8_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2SW8_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW8_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW8_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW8_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW8_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW8_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2SW8_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2SW8_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW8_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW8_RING_TP_ADDR(x) ((x) + 0x3084) +#define HWIO_REO_R2_REO2SW8_RING_TP_PHYS(x) ((x) + 0x3084) +#define HWIO_REO_R2_REO2SW8_RING_TP_OFFS (0x3084) +#define HWIO_REO_R2_REO2SW8_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW8_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW8_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW8_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW8_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW8_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2SW8_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW8_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW8_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW8_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW8_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW8_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2SW8_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2SW8_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW8_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x) ((x) + 0x3088) +#define HWIO_REO_R2_REO2SW0_RING_HP_PHYS(x) ((x) + 0x3088) +#define HWIO_REO_R2_REO2SW0_RING_HP_OFFS (0x3088) +#define HWIO_REO_R2_REO2SW0_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW0_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW0_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW0_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW0_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2SW0_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW0_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW0_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2SW0_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2SW0_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW0_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW0_RING_TP_ADDR(x) ((x) + 0x308c) +#define HWIO_REO_R2_REO2SW0_RING_TP_PHYS(x) ((x) + 0x308c) +#define HWIO_REO_R2_REO2SW0_RING_TP_OFFS (0x308c) +#define HWIO_REO_R2_REO2SW0_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW0_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW0_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW0_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW0_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW0_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2SW0_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW0_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW0_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW0_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW0_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW0_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2SW0_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2SW0_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW0_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2PPE_RING_HP_ADDR(x) ((x) + 0x3090) +#define HWIO_REO_R2_REO2PPE_RING_HP_PHYS(x) ((x) + 0x3090) +#define HWIO_REO_R2_REO2PPE_RING_HP_OFFS (0x3090) +#define HWIO_REO_R2_REO2PPE_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2PPE_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2PPE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2PPE_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2PPE_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2PPE_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2PPE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2PPE_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2PPE_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2PPE_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2PPE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2PPE_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2PPE_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2PPE_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2PPE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2PPE_RING_TP_ADDR(x) ((x) + 0x3094) +#define HWIO_REO_R2_REO2PPE_RING_TP_PHYS(x) ((x) + 0x3094) +#define HWIO_REO_R2_REO2PPE_RING_TP_OFFS (0x3094) +#define HWIO_REO_R2_REO2PPE_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2PPE_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2PPE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2PPE_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2PPE_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2PPE_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2PPE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2PPE_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2PPE_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2PPE_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2PPE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2PPE_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2PPE_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2PPE_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2PPE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2FW_RING_HP_ADDR(x) ((x) + 0x3098) +#define HWIO_REO_R2_REO2FW_RING_HP_PHYS(x) ((x) + 0x3098) +#define HWIO_REO_R2_REO2FW_RING_HP_OFFS (0x3098) +#define HWIO_REO_R2_REO2FW_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2FW_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2FW_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2FW_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2FW_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2FW_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2FW_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2FW_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2FW_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2FW_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2FW_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2FW_RING_TP_ADDR(x) ((x) + 0x309c) +#define HWIO_REO_R2_REO2FW_RING_TP_PHYS(x) ((x) + 0x309c) +#define HWIO_REO_R2_REO2FW_RING_TP_OFFS (0x309c) +#define HWIO_REO_R2_REO2FW_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2FW_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2FW_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2FW_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2FW_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2FW_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2FW_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2FW_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2FW_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2FW_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2FW_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x) ((x) + 0x30a8) +#define HWIO_REO_R2_REO_STATUS_RING_HP_PHYS(x) ((x) + 0x30a8) +#define HWIO_REO_R2_REO_STATUS_RING_HP_OFFS (0x30a8) +#define HWIO_REO_R2_REO_STATUS_RING_HP_RMSK 0xffff +#define HWIO_REO_R2_REO_STATUS_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO_STATUS_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO_STATUS_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO_STATUS_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO_STATUS_RING_HP_IN(x)) +#define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x) ((x) + 0x30ac) +#define HWIO_REO_R2_REO_STATUS_RING_TP_PHYS(x) ((x) + 0x30ac) +#define HWIO_REO_R2_REO_STATUS_RING_TP_OFFS (0x30ac) +#define HWIO_REO_R2_REO_STATUS_RING_TP_RMSK 0xffff +#define HWIO_REO_R2_REO_STATUS_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO_STATUS_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO_STATUS_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO_STATUS_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO_STATUS_RING_TP_IN(x)) +#define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_SHFT 0 + + +#define MAC_TCL_REG_REG_BASE (UMAC_BASE + 0x00044000) +#define MAC_TCL_REG_REG_BASE_SIZE 0x3000 +#define MAC_TCL_REG_REG_BASE_USED 0x205c +#define MAC_TCL_REG_REG_BASE_PHYS (UMAC_BASE_PHYS + 0x00044000) +#define MAC_TCL_REG_REG_BASE_OFFS 0x00044000 + +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x) ((x) + 0x0) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_PHYS(x) ((x) + 0x0) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OFFS (0x0) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK 0x3ffe0 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x3ffc0 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 6 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_SHFT 5 + +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x) ((x) + 0x4) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_PHYS(x) ((x) + 0x4) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OFFS (0x4) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK 0x3ffe0 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_BMSK 0x3ffc0 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_SHFT 6 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_SHFT 5 + +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x) ((x) + 0x8) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_PHYS(x) ((x) + 0x8) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OFFS (0x8) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK 0x3ffe0 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_BMSK 0x3ffc0 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_SHFT 6 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_SHFT 5 + +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_ADDR(x) ((x) + 0xc) +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_PHYS(x) ((x) + 0xc) +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_OFFS (0xc) +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_RMSK 0x3ffe0 +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_CTRL_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_CTRL_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_TIMEOUT_VAL_BMSK 0x3ffc0 +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_TIMEOUT_VAL_SHFT 6 +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_RNG_PRTY_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_RNG_PRTY_SHFT 5 + +#define HWIO_TCL_R0_SW2TCL5_RING_CTRL_ADDR(x) ((x) + 0x10) +#define HWIO_TCL_R0_SW2TCL5_RING_CTRL_PHYS(x) ((x) + 0x10) +#define HWIO_TCL_R0_SW2TCL5_RING_CTRL_OFFS (0x10) +#define HWIO_TCL_R0_SW2TCL5_RING_CTRL_RMSK 0x3ffe0 +#define HWIO_TCL_R0_SW2TCL5_RING_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL5_RING_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL5_RING_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL5_RING_CTRL_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL5_RING_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL5_RING_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL5_RING_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL5_RING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL5_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL5_RING_CTRL_IN(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_CTRL_TIMEOUT_VAL_BMSK 0x3ffc0 +#define HWIO_TCL_R0_SW2TCL5_RING_CTRL_TIMEOUT_VAL_SHFT 6 +#define HWIO_TCL_R0_SW2TCL5_RING_CTRL_RNG_PRTY_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL5_RING_CTRL_RNG_PRTY_SHFT 5 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x) ((x) + 0x18) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_PHYS(x) ((x) + 0x18) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_OFFS (0x18) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_RMSK 0x3ffe0 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_TIMEOUT_VAL_BMSK 0x3ffc0 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_TIMEOUT_VAL_SHFT 6 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_RNG_PRTY_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_RNG_PRTY_SHFT 5 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) ((x) + 0x20) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PHYS(x) ((x) + 0x20) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OFFS (0x20) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK 0xfffffff +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_POR 0x0b700000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ATTR 0x3 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x) \ + in_dword(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x)) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), m) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUT(x, v) \ + out_dword(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x),v) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x),m,v,HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x)) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE_RING_EN_BMSK 0x8000000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE_RING_EN_SHFT 27 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_VLAN_LLC_SEL_BMSK 0x4000000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_VLAN_LLC_SEL_SHFT 26 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INSERT_VLAN_EN_BMSK 0x2000000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INSERT_VLAN_EN_SHFT 25 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_STOP_META_RD_AT_8B_BDRY_BMSK 0x1000000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_STOP_META_RD_AT_8B_BDRY_SHFT 24 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK 0x800000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT 23 + +#define HWIO_TCL_R0_RBM_MAPPING0_ADDR(x) ((x) + 0x88) +#define HWIO_TCL_R0_RBM_MAPPING0_PHYS(x) ((x) + 0x88) +#define HWIO_TCL_R0_RBM_MAPPING0_OFFS (0x88) + +#define HWIO_TCL_R0_RBM_MAPPING0_RMSK 0xffffffff +#define HWIO_TCL_R0_RBM_MAPPING0_POR 0x00000000 +#define HWIO_TCL_R0_RBM_MAPPING0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_RBM_MAPPING0_ATTR 0x3 +#define HWIO_TCL_R0_RBM_MAPPING0_IN(x) \ + in_dword(HWIO_TCL_R0_RBM_MAPPING0_ADDR(x)) +#define HWIO_TCL_R0_RBM_MAPPING0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_RBM_MAPPING0_ADDR(x), m) +#define HWIO_TCL_R0_RBM_MAPPING0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_RBM_MAPPING0_ADDR(x),v) +#define HWIO_TCL_R0_RBM_MAPPING0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_RBM_MAPPING0_ADDR(x),m,v,HWIO_TCL_R0_RBM_MAPPING0_IN(x)) +#define HWIO_TCL_R0_RBM_MAPPING0_PPE2TCL1_RING_BMSK 0xf0000000 +#define HWIO_TCL_R0_RBM_MAPPING0_PPE2TCL1_RING_SHFT 28 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL_CREDIT_RING_BMSK 0xf000000 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL_CREDIT_RING_SHFT 24 +#define HWIO_TCL_R0_RBM_MAPPING0_FW2TCL_RING_BMSK 0xf00000 +#define HWIO_TCL_R0_RBM_MAPPING0_FW2TCL_RING_SHFT 20 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL5_RING_BMSK 0xf0000 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL5_RING_SHFT 16 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL4_RING_BMSK 0xf000 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL4_RING_SHFT 12 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL3_RING_BMSK 0xf00 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL3_RING_SHFT 8 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL2_RING_BMSK 0xf0 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL2_RING_SHFT 4 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL1_RING_BMSK 0xf +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL1_RING_SHFT 0 + +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n) ((base) + 0X8C + (0x4*(n))) +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_PHYS(base,n) ((base) + 0X8C + (0x4*(n))) +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_OFFS(n) (0X8C + (0x4*(n))) +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_RMSK 0x7fffff +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_MAXn 47 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_POR 0x00000038 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ATTR 0x3 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n), HWIO_TCL_R0_SW_CONFIG_BANK_n_RMSK) +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n), mask) +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_OUTI(base,n,val) \ + out_dword(HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n),val) +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n),mask,val,HWIO_TCL_R0_SW_CONFIG_BANK_n_INI(base,n)) +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_BMSK 0x7e0000 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT 17 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_BMSK 0x18000 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT 15 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_BMSK 0x4000 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT 14 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_BMSK 0x3000 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT 12 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_BMSK 0x800 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT 11 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_BMSK 0x400 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT 10 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_BMSK 0x200 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT 9 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_BMSK 0x100 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT 8 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_BMSK 0x80 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT 7 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_BMSK 0x78 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT 3 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_BMSK 0x6 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT 1 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_BMSK 0x1 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT 0 +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(base,n) ((base) + 0X14C + (0x4*(n))) +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_PHYS(base,n) ((base) + 0X14C + (0x4*(n))) +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_OFFS(n) (0X14C + (0x4*(n))) +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_RMSK 0xffffffff +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_MAXn 15 +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_POR 0x00000000 +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ATTR 0x3 +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(base,n), HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_RMSK) +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(base,n), mask) +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_OUTI(base,n,val) \ + out_dword(HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(base,n),val) +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(base,n),mask,val,HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_INI(base,n)) +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_VAL_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n) ((base) + 0X240 + (0x4*(n))) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_PHYS(base,n) ((base) + 0X240 + (0x4*(n))) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_OFFS(n) (0X240 + (0x4*(n))) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK 0xffffffff +#define HWIO_TCL_R0_DSCP_TID_MAP_n_MAXn 287 +#define HWIO_TCL_R0_DSCP_TID_MAP_n_POR 0x00000000 +#define HWIO_TCL_R0_DSCP_TID_MAP_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_DSCP_TID_MAP_n_ATTR 0x3 +#define HWIO_TCL_R0_DSCP_TID_MAP_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n), HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n), mask) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_OUTI(base,n,val) \ + out_dword(HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n),val) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n),mask,val,HWIO_TCL_R0_DSCP_TID_MAP_n_INI(base,n)) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_DSCP_TID_MAP_n_VAL_SHFT 0 + +#define HWIO_TCL_R0_PCP_TID_MAP_ADDR(x) ((x) + 0x6c0) +#define HWIO_TCL_R0_PCP_TID_MAP_PHYS(x) ((x) + 0x6c0) +#define HWIO_TCL_R0_PCP_TID_MAP_OFFS (0x6c0) +#define HWIO_TCL_R0_PCP_TID_MAP_RMSK 0xffffff +#define HWIO_TCL_R0_PCP_TID_MAP_POR 0x00000000 +#define HWIO_TCL_R0_PCP_TID_MAP_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PCP_TID_MAP_ATTR 0x3 +#define HWIO_TCL_R0_PCP_TID_MAP_IN(x) \ + in_dword(HWIO_TCL_R0_PCP_TID_MAP_ADDR(x)) +#define HWIO_TCL_R0_PCP_TID_MAP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), m) +#define HWIO_TCL_R0_PCP_TID_MAP_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PCP_TID_MAP_ADDR(x),v) +#define HWIO_TCL_R0_PCP_TID_MAP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PCP_TID_MAP_ADDR(x),m,v,HWIO_TCL_R0_PCP_TID_MAP_IN(x)) +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_BMSK 0xe00000 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT 21 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_BMSK 0x1c0000 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT 18 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_BMSK 0x38000 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT 15 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_BMSK 0x7000 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT 12 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_BMSK 0xe00 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT 9 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_BMSK 0x1c0 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT 6 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_BMSK 0x38 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT 3 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_BMSK 0x7 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_SHFT 0 + +#define HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x) ((x) + 0x6e8) +#define HWIO_TCL_R0_TID_MAP_PRTY_PHYS(x) ((x) + 0x6e8) +#define HWIO_TCL_R0_TID_MAP_PRTY_OFFS (0x6e8) +#define HWIO_TCL_R0_TID_MAP_PRTY_RMSK 0xef +#define HWIO_TCL_R0_TID_MAP_PRTY_POR 0x00000000 +#define HWIO_TCL_R0_TID_MAP_PRTY_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TID_MAP_PRTY_ATTR 0x3 +#define HWIO_TCL_R0_TID_MAP_PRTY_IN(x) \ + in_dword(HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x)) +#define HWIO_TCL_R0_TID_MAP_PRTY_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), m) +#define HWIO_TCL_R0_TID_MAP_PRTY_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x),v) +#define HWIO_TCL_R0_TID_MAP_PRTY_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x),m,v,HWIO_TCL_R0_TID_MAP_PRTY_IN(x)) +#define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_BMSK 0xe0 +#define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_SHFT 5 +#define HWIO_TCL_R0_TID_MAP_PRTY_VAL_BMSK 0xf +#define HWIO_TCL_R0_TID_MAP_PRTY_VAL_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) ((x) + 0x900) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_PHYS(x) ((x) + 0x900) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OFFS (0x900) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) ((x) + 0x904) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_PHYS(x) ((x) + 0x904) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OFFS (0x904) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) ((x) + 0x908) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_PHYS(x) ((x) + 0x908) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_OFFS (0x908) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x) ((x) + 0x90c) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_PHYS(x) ((x) + 0x90c) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OFFS (0x90c) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) ((x) + 0x910) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_PHYS(x) ((x) + 0x910) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_OFFS (0x910) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK 0x3fffff +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x91c) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x91c) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OFFS (0x91c) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x920) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x920) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OFFS (0x920) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x930) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x930) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x930) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x934) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x934) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x934) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x938) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x938) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OFFS (0x938) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x93c) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x93c) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x93c) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x940) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x940) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x940) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x944) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x944) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x944) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff00000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 20 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x948) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x948) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OFFS (0x948) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x94c) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x94c) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OFFS (0x94c) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) ((x) + 0x950) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_PHYS(x) ((x) + 0x950) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OFFS (0x950) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x970) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x970) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OFFS (0x970) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_ADDR(x) ((x) + 0x974) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_PHYS(x) ((x) + 0x974) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_OFFS (0x974) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) ((x) + 0x978) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_PHYS(x) ((x) + 0x978) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OFFS (0x978) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x) ((x) + 0x97c) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_PHYS(x) ((x) + 0x97c) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OFFS (0x97c) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x) ((x) + 0x980) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_PHYS(x) ((x) + 0x980) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_OFFS (0x980) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL2_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x) ((x) + 0x984) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_PHYS(x) ((x) + 0x984) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OFFS (0x984) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x) ((x) + 0x988) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_PHYS(x) ((x) + 0x988) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_OFFS (0x988) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK 0x3fffff +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x994) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x994) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OFFS (0x994) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x998) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x998) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OFFS (0x998) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x9a8) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x9a8) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x9a8) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x9ac) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x9ac) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x9ac) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x9b0) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x9b0) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OFFS (0x9b0) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x9b4) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x9b4) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x9b4) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x9b8) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x9b8) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x9b8) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x9bc) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x9bc) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x9bc) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff00000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 20 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x9c0) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x9c0) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OFFS (0x9c0) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x9c4) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x9c4) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OFFS (0x9c4) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x) ((x) + 0x9c8) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_PHYS(x) ((x) + 0x9c8) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OFFS (0x9c8) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x9e8) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x9e8) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OFFS (0x9e8) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_ADDR(x) ((x) + 0x9ec) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_PHYS(x) ((x) + 0x9ec) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_OFFS (0x9ec) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x) ((x) + 0x9f0) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_PHYS(x) ((x) + 0x9f0) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OFFS (0x9f0) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x) ((x) + 0x9f4) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_PHYS(x) ((x) + 0x9f4) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OFFS (0x9f4) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x) ((x) + 0x9f8) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_PHYS(x) ((x) + 0x9f8) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_OFFS (0x9f8) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL3_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x) ((x) + 0x9fc) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_PHYS(x) ((x) + 0x9fc) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OFFS (0x9fc) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x) ((x) + 0xa00) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_PHYS(x) ((x) + 0xa00) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_OFFS (0xa00) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK 0x3fffff +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xa0c) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xa0c) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OFFS (0xa0c) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xa10) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xa10) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OFFS (0xa10) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xa20) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xa20) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xa20) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xa24) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xa24) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xa24) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xa28) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xa28) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OFFS (0xa28) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xa2c) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xa2c) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xa2c) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xa30) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xa30) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xa30) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xa34) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xa34) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xa34) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff00000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 20 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa38) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa38) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OFFS (0xa38) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa3c) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa3c) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OFFS (0xa3c) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x) ((x) + 0xa40) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_PHYS(x) ((x) + 0xa40) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OFFS (0xa40) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xa60) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xa60) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OFFS (0xa60) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_ADDR(x) ((x) + 0xa64) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_PHYS(x) ((x) + 0xa64) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_OFFS (0xa64) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_ADDR(x) ((x) + 0xa68) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_PHYS(x) ((x) + 0xa68) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_OFFS (0xa68) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_ADDR(x) ((x) + 0xa6c) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_PHYS(x) ((x) + 0xa6c) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_OFFS (0xa6c) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_ID_ADDR(x) ((x) + 0xa70) +#define HWIO_TCL_R0_SW2TCL4_RING_ID_PHYS(x) ((x) + 0xa70) +#define HWIO_TCL_R0_SW2TCL4_RING_ID_OFFS (0xa70) +#define HWIO_TCL_R0_SW2TCL4_RING_ID_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL4_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_ID_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL4_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_ADDR(x) ((x) + 0xa74) +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_PHYS(x) ((x) + 0xa74) +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_OFFS (0xa74) +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_ADDR(x) ((x) + 0xa78) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_PHYS(x) ((x) + 0xa78) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_OFFS (0xa78) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_RMSK 0x3fffff +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_MISC_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xa84) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xa84) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_OFFS (0xa84) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xa88) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xa88) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_OFFS (0xa88) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xa98) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xa98) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xa98) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xa9c) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xa9c) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xa9c) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xaa0) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xaa0) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_OFFS (0xaa0) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xaa4) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xaa4) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xaa4) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xaa8) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xaa8) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xaa8) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xaac) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xaac) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xaac) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff00000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 20 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xab0) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xab0) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_OFFS (0xab0) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xab4) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xab4) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_OFFS (0xab4) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_ADDR(x) ((x) + 0xab8) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_PHYS(x) ((x) + 0xab8) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_OFFS (0xab8) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xad8) +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xad8) +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_OFFS (0xad8) +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_ADDR(x) ((x) + 0xadc) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_PHYS(x) ((x) + 0xadc) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_OFFS (0xadc) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_LSB_ADDR(x) ((x) + 0xae0) +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_LSB_PHYS(x) ((x) + 0xae0) +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_LSB_OFFS (0xae0) +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL5_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL5_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL5_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL5_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL5_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_MSB_ADDR(x) ((x) + 0xae4) +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_MSB_PHYS(x) ((x) + 0xae4) +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_MSB_OFFS (0xae4) +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL5_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL5_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL5_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL5_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL5_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL5_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL5_RING_ID_ADDR(x) ((x) + 0xae8) +#define HWIO_TCL_R0_SW2TCL5_RING_ID_PHYS(x) ((x) + 0xae8) +#define HWIO_TCL_R0_SW2TCL5_RING_ID_OFFS (0xae8) +#define HWIO_TCL_R0_SW2TCL5_RING_ID_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL5_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL5_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL5_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL5_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL5_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL5_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL5_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL5_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL5_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL5_RING_ID_IN(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL5_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL5_RING_STATUS_ADDR(x) ((x) + 0xaec) +#define HWIO_TCL_R0_SW2TCL5_RING_STATUS_PHYS(x) ((x) + 0xaec) +#define HWIO_TCL_R0_SW2TCL5_RING_STATUS_OFFS (0xaec) +#define HWIO_TCL_R0_SW2TCL5_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL5_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL5_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL5_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL5_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL5_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL5_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_SW2TCL5_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL5_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_ADDR(x) ((x) + 0xaf0) +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_PHYS(x) ((x) + 0xaf0) +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_OFFS (0xaf0) +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_RMSK 0x3fffff +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL5_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL5_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL5_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL5_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL5_RING_MISC_IN(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xafc) +#define HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xafc) +#define HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_LSB_OFFS (0xafc) +#define HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xb00) +#define HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xb00) +#define HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_MSB_OFFS (0xb00) +#define HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL5_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xb10) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xb10) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xb10) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xb14) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xb14) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xb14) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xb18) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xb18) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_STATUS_OFFS (0xb18) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xb1c) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xb1c) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xb1c) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xb20) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xb20) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xb20) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xb24) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xb24) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xb24) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff00000 +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 20 +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R0_SW2TCL5_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xb28) +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xb28) +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_LSB_OFFS (0xb28) +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xb2c) +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xb2c) +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_MSB_OFFS (0xb2c) +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_DATA_ADDR(x) ((x) + 0xb30) +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_DATA_PHYS(x) ((x) + 0xb30) +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_DATA_OFFS (0xb30) +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL5_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL5_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL5_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL5_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL5_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL5_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xb50) +#define HWIO_TCL_R0_SW2TCL5_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xb50) +#define HWIO_TCL_R0_SW2TCL5_RING_HP_TP_SW_OFFSET_OFFS (0xb50) +#define HWIO_TCL_R0_SW2TCL5_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL5_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL5_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL5_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL5_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL5_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL5_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL5_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL5_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL5_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL5_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL5_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_1_ADDR(x) ((x) + 0xb54) +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_1_PHYS(x) ((x) + 0xb54) +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_1_OFFS (0xb54) +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL5_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL5_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL5_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL5_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL5_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x) ((x) + 0xb58) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_PHYS(x) ((x) + 0xb58) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_OFFS (0xb58) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x) ((x) + 0xb5c) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_PHYS(x) ((x) + 0xb5c) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_OFFS (0xb5c) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x) ((x) + 0xb60) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_PHYS(x) ((x) + 0xb60) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_OFFS (0xb60) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x) ((x) + 0xb64) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_PHYS(x) ((x) + 0xb64) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_OFFS (0xb64) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x) ((x) + 0xb68) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_PHYS(x) ((x) + 0xb68) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_OFFS (0xb68) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_RMSK 0x3fffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xb74) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xb74) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_OFFS (0xb74) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xb78) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xb78) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_OFFS (0xb78) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xb88) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xb88) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xb88) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xb8c) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xb8c) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xb8c) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xb90) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xb90) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_OFFS (0xb90) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xb94) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xb94) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xb94) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xb98) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xb98) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xb98) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xb9c) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xb9c) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xb9c) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff00000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 20 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xba0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xba0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_OFFS (0xba0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xba4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xba4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_OFFS (0xba4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x) ((x) + 0xba8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_PHYS(x) ((x) + 0xba8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_OFFS (0xba8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xbc8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xbc8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_OFFS (0xbc8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_ADDR(x) ((x) + 0xbcc) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_PHYS(x) ((x) + 0xbcc) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_OFFS (0xbcc) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ADDR(x) ((x) + 0xc48) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_PHYS(x) ((x) + 0xc48) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_OFFS (0xc48) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_ADDR(x) ((x) + 0xc4c) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_PHYS(x) ((x) + 0xc4c) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_OFFS (0xc4c) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_ADDR(x) ((x) + 0xc50) +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_PHYS(x) ((x) + 0xc50) +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_OFFS (0xc50) +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_RMSK 0xff +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_ID_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_ADDR(x) ((x) + 0xc54) +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_PHYS(x) ((x) + 0xc54) +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_OFFS (0xc54) +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_ADDR(x) ((x) + 0xc58) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_PHYS(x) ((x) + 0xc58) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_OFFS (0xc58) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_RMSK 0x3fffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_MISC_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xc64) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xc64) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_OFFS (0xc64) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xc68) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xc68) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_OFFS (0xc68) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xc78) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xc78) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xc78) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xc7c) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xc7c) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xc7c) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xc80) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xc80) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_OFFS (0xc80) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xc84) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xc84) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xc84) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xc88) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xc88) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xc88) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xc8c) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xc8c) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xc8c) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff00000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 20 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xc90) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xc90) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_OFFS (0xc90) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xc94) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xc94) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_OFFS (0xc94) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_ADDR(x) ((x) + 0xc98) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_PHYS(x) ((x) + 0xc98) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_OFFS (0xc98) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xcb8) +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xcb8) +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_OFFS (0xcb8) +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_ADDR(x) ((x) + 0xcbc) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_PHYS(x) ((x) + 0xcbc) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_OFFS (0xcbc) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x) ((x) + 0xd38) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_PHYS(x) ((x) + 0xd38) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OFFS (0xd38) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x) ((x) + 0xd3c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_PHYS(x) ((x) + 0xd3c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OFFS (0xd3c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x) ((x) + 0xd40) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_PHYS(x) ((x) + 0xd40) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OFFS (0xd40) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK 0xffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_SHFT 8 +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x) ((x) + 0xd44) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_PHYS(x) ((x) + 0xd44) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OFFS (0xd44) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x) ((x) + 0xd48) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_PHYS(x) ((x) + 0xd48) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OFFS (0xd48) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK 0x7ffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xd4c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xd4c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OFFS (0xd4c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xd50) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xd50) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OFFS (0xd50) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xd5c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xd5c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OFFS (0xd5c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xd60) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xd60) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OFFS (0xd60) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xd64) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xd64) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OFFS (0xd64) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xd80) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xd80) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OFFS (0xd80) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xd84) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xd84) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OFFS (0xd84) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x) ((x) + 0xd88) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_PHYS(x) ((x) + 0xd88) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OFFS (0xd88) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xd8c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xd8c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_OFFS (0xd8c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xd90) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xd90) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_OFFS (0xd90) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xd94) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xd94) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_OFFS (0xd94) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_ADDR(x) ((x) + 0xd98) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_PHYS(x) ((x) + 0xd98) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_OFFS (0xd98) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xda8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xda8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OFFS (0xda8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_ADDR(x) ((x) + 0xdac) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_PHYS(x) ((x) + 0xdac) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_OFFS (0xdac) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x) ((x) + 0x2000) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_PHYS(x) ((x) + 0x2000) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_OFFS (0x2000) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL1_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL1_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x)) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x) ((x) + 0x2004) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_PHYS(x) ((x) + 0x2004) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_OFFS (0x2004) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL1_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL1_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x)) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x) ((x) + 0x2008) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_PHYS(x) ((x) + 0x2008) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_OFFS (0x2008) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL2_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL2_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL2_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x)) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x) ((x) + 0x200c) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_PHYS(x) ((x) + 0x200c) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_OFFS (0x200c) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL2_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL2_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL2_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x)) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x) ((x) + 0x2010) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_PHYS(x) ((x) + 0x2010) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_OFFS (0x2010) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL3_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL3_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL3_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x)) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x) ((x) + 0x2014) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_PHYS(x) ((x) + 0x2014) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_OFFS (0x2014) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL3_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL3_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL3_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x)) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL4_RING_HP_ADDR(x) ((x) + 0x2018) +#define HWIO_TCL_R2_SW2TCL4_RING_HP_PHYS(x) ((x) + 0x2018) +#define HWIO_TCL_R2_SW2TCL4_RING_HP_OFFS (0x2018) +#define HWIO_TCL_R2_SW2TCL4_RING_HP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL4_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL4_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL4_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL4_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL4_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL4_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL4_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL4_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL4_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL4_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL4_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL4_RING_HP_IN(x)) +#define HWIO_TCL_R2_SW2TCL4_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL4_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL4_RING_TP_ADDR(x) ((x) + 0x201c) +#define HWIO_TCL_R2_SW2TCL4_RING_TP_PHYS(x) ((x) + 0x201c) +#define HWIO_TCL_R2_SW2TCL4_RING_TP_OFFS (0x201c) +#define HWIO_TCL_R2_SW2TCL4_RING_TP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL4_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL4_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL4_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL4_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL4_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL4_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL4_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL4_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL4_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL4_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL4_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL4_RING_TP_IN(x)) +#define HWIO_TCL_R2_SW2TCL4_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL4_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL5_RING_HP_ADDR(x) ((x) + 0x2020) +#define HWIO_TCL_R2_SW2TCL5_RING_HP_PHYS(x) ((x) + 0x2020) +#define HWIO_TCL_R2_SW2TCL5_RING_HP_OFFS (0x2020) +#define HWIO_TCL_R2_SW2TCL5_RING_HP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL5_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL5_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL5_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL5_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL5_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL5_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL5_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL5_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL5_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL5_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL5_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL5_RING_HP_IN(x)) +#define HWIO_TCL_R2_SW2TCL5_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL5_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL5_RING_TP_ADDR(x) ((x) + 0x2024) +#define HWIO_TCL_R2_SW2TCL5_RING_TP_PHYS(x) ((x) + 0x2024) +#define HWIO_TCL_R2_SW2TCL5_RING_TP_OFFS (0x2024) +#define HWIO_TCL_R2_SW2TCL5_RING_TP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL5_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL5_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL5_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL5_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL5_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL5_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL5_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL5_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL5_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL5_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL5_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL5_RING_TP_IN(x)) +#define HWIO_TCL_R2_SW2TCL5_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL5_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x) ((x) + 0x2028) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_PHYS(x) ((x) + 0x2028) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_OFFS (0x2028) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_IN(x)) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x) ((x) + 0x202c) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_PHYS(x) ((x) + 0x202c) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_OFFS (0x202c) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_IN(x)) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x) ((x) + 0x2030) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_PHYS(x) ((x) + 0x2030) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_OFFS (0x2030) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK 0xffff +#define HWIO_TCL_R2_FW2TCL1_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_FW2TCL1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_FW2TCL1_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x)) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x) ((x) + 0x2034) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_PHYS(x) ((x) + 0x2034) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_OFFS (0x2034) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK 0xffff +#define HWIO_TCL_R2_FW2TCL1_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_FW2TCL1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_FW2TCL1_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x)) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_ADDR(x) ((x) + 0x2038) +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_PHYS(x) ((x) + 0x2038) +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_OFFS (0x2038) +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_RMSK 0xfffff +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_PPE2TCL1_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_PPE2TCL1_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_PPE2TCL1_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_PPE2TCL1_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_PPE2TCL1_RING_HP_IN(x)) +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_ADDR(x) ((x) + 0x203c) +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_PHYS(x) ((x) + 0x203c) +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_OFFS (0x203c) +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_RMSK 0xfffff +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_PPE2TCL1_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_PPE2TCL1_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_PPE2TCL1_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_PPE2TCL1_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_PPE2TCL1_RING_TP_IN(x)) +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x) ((x) + 0x2048) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_PHYS(x) ((x) + 0x2048) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OFFS (0x2048) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK 0xffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x)) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x) ((x) + 0x204c) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_PHYS(x) ((x) + 0x204c) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OFFS (0x204c) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK 0xffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x)) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_SHFT 0 + +#endif diff --git a/hw/qcn9224/wcss_version.h b/hw/qcn9224/wcss_version.h new file mode 100644 index 000000000000..31e653989ea8 --- /dev/null +++ b/hw/qcn9224/wcss_version.h @@ -0,0 +1,17 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#define WCSS_VERSION 2176 diff --git a/hw/qcn9224/wfss_ce_reg_seq_hwioreg.h b/hw/qcn9224/wfss_ce_reg_seq_hwioreg.h new file mode 100755 index 000000000000..a8315cd57f91 --- /dev/null +++ b/hw/qcn9224/wfss_ce_reg_seq_hwioreg.h @@ -0,0 +1,20509 @@ + +/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef __WFSS_CE_REG_SEQ_HWIOREG_H__ +#define __WFSS_CE_REG_SEQ_HWIOREG_H__ + + + + + +#define CE_WFSS_CE_REG_BASE 0x1B80000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x1B80000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x1B81000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x1B82000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x1B83000 + + + +#define WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x00000000) +#define WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_USED 0x404 +#define WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x00000000) +#define WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00000000 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_0_CHANNEL_DST_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x00001000) +#define WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_USED 0x40c +#define WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x00001000) +#define WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS 0x00001000 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x00002000) +#define WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_USED 0x404 +#define WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x00002000) +#define WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00002000 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_1_CHANNEL_DST_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x00003000) +#define WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_USED 0x40c +#define WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x00003000) +#define WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS 0x00003000 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x00004000) +#define WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_USED 0x404 +#define WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x00004000) +#define WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00004000 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_2_CHANNEL_DST_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x00005000) +#define WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_USED 0x40c +#define WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x00005000) +#define WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS 0x00005000 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x00006000) +#define WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_USED 0x404 +#define WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x00006000) +#define WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00006000 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_3_CHANNEL_DST_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x00007000) +#define WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_USED 0x40c +#define WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x00007000) +#define WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS 0x00007000 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x00008000) +#define WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_USED 0x404 +#define WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x00008000) +#define WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00008000 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_4_CHANNEL_DST_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x00009000) +#define WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_USED 0x40c +#define WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x00009000) +#define WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS 0x00009000 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x0000a000) +#define WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_USED 0x404 +#define WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x0000a000) +#define WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS 0x0000a000 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_5_CHANNEL_DST_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x0000b000) +#define WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_USED 0x40c +#define WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x0000b000) +#define WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS 0x0000b000 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x0000c000) +#define WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_USED 0x404 +#define WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x0000c000) +#define WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS 0x0000c000 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_6_CHANNEL_DST_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x0000d000) +#define WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_USED 0x40c +#define WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x0000d000) +#define WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS 0x0000d000 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x0000e000) +#define WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_USED 0x404 +#define WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x0000e000) +#define WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS 0x0000e000 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_7_CHANNEL_DST_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x0000f000) +#define WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_USED 0x40c +#define WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x0000f000) +#define WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS 0x0000f000 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x00010000) +#define WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_USED 0x404 +#define WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x00010000) +#define WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00010000 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_8_CHANNEL_DST_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x00011000) +#define WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_USED 0x40c +#define WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x00011000) +#define WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS 0x00011000 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x00012000) +#define WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_USED 0x404 +#define WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x00012000) +#define WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00012000 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_9_CHANNEL_DST_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x00013000) +#define WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_USED 0x40c +#define WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x00013000) +#define WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS 0x00013000 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x00014000) +#define WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_USED 0x404 +#define WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x00014000) +#define WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00014000 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_10_CHANNEL_DST_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x00015000) +#define WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_USED 0x40c +#define WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x00015000) +#define WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS 0x00015000 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x00016000) +#define WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_USED 0x404 +#define WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x00016000) +#define WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00016000 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_11_CHANNEL_DST_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x00017000) +#define WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_USED 0x40c +#define WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x00017000) +#define WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS 0x00017000 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_12_CHANNEL_SRC_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x00018000) +#define WFSS_CE_12_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_12_CHANNEL_SRC_REG_REG_BASE_USED 0x404 +#define WFSS_CE_12_CHANNEL_SRC_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x00018000) +#define WFSS_CE_12_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00018000 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_12_CHANNEL_DST_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x00019000) +#define WFSS_CE_12_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_12_CHANNEL_DST_REG_REG_BASE_USED 0x40c +#define WFSS_CE_12_CHANNEL_DST_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x00019000) +#define WFSS_CE_12_CHANNEL_DST_REG_REG_BASE_OFFS 0x00019000 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_13_CHANNEL_SRC_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x0001a000) +#define WFSS_CE_13_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_13_CHANNEL_SRC_REG_REG_BASE_USED 0x404 +#define WFSS_CE_13_CHANNEL_SRC_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x0001a000) +#define WFSS_CE_13_CHANNEL_SRC_REG_REG_BASE_OFFS 0x0001a000 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_13_CHANNEL_DST_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x0001b000) +#define WFSS_CE_13_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_13_CHANNEL_DST_REG_REG_BASE_USED 0x40c +#define WFSS_CE_13_CHANNEL_DST_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x0001b000) +#define WFSS_CE_13_CHANNEL_DST_REG_REG_BASE_OFFS 0x0001b000 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_14_CHANNEL_SRC_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x0001c000) +#define WFSS_CE_14_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_14_CHANNEL_SRC_REG_REG_BASE_USED 0x404 +#define WFSS_CE_14_CHANNEL_SRC_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x0001c000) +#define WFSS_CE_14_CHANNEL_SRC_REG_REG_BASE_OFFS 0x0001c000 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_14_CHANNEL_DST_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x0001d000) +#define WFSS_CE_14_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_14_CHANNEL_DST_REG_REG_BASE_USED 0x40c +#define WFSS_CE_14_CHANNEL_DST_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x0001d000) +#define WFSS_CE_14_CHANNEL_DST_REG_REG_BASE_OFFS 0x0001d000 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_15_CHANNEL_SRC_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x0001e000) +#define WFSS_CE_15_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_15_CHANNEL_SRC_REG_REG_BASE_USED 0x404 +#define WFSS_CE_15_CHANNEL_SRC_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x0001e000) +#define WFSS_CE_15_CHANNEL_SRC_REG_REG_BASE_OFFS 0x0001e000 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_15_CHANNEL_DST_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x0001f000) +#define WFSS_CE_15_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_15_CHANNEL_DST_REG_REG_BASE_USED 0x40c +#define WFSS_CE_15_CHANNEL_DST_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x0001f000) +#define WFSS_CE_15_CHANNEL_DST_REG_REG_BASE_OFFS 0x0001f000 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xc) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0 + + + +#define WFSS_CE_COMMON_REG_REG_BASE (CE_WFSS_CE_REG_BASE + 0x00020000) +#define WFSS_CE_COMMON_REG_REG_BASE_SIZE 0x1000 +#define WFSS_CE_COMMON_REG_REG_BASE_USED 0x41c +#define WFSS_CE_COMMON_REG_REG_BASE_PHYS (CE_WFSS_CE_REG_BASE_PHYS + 0x00020000) +#define WFSS_CE_COMMON_REG_REG_BASE_OFFS 0x00020000 + +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x) ((x) + 0x0) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_PHYS(x) ((x) + 0x0) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_OFFS (0x0) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x) ((x) + 0x4) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_PHYS(x) ((x) + 0x4) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_OFFS (0x4) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK 0xff +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_BMSK 0xff +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x) ((x) + 0x8) +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_PHYS(x) ((x) + 0x8) +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_OFFS (0x8) +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK 0xfff +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_POR 0x00000211 +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0xe00 +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 9 +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x1f0 +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 4 +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0xf +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x) ((x) + 0xc) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_PHYS(x) ((x) + 0xc) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OFFS (0xc) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x) ((x) + 0x10) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_PHYS(x) ((x) + 0x10) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OFFS (0x10) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK 0x80000fff +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 31 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SPARE_BMSK 0x800 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SPARE_SHFT 11 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK 0x400 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT 10 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_FIFO_BMSK 0x200 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_FIFO_SHFT 9 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x100 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT 8 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x80 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT 7 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x40 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT 6 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x20 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT 5 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x10 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT 4 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x8 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT 3 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x4 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT 2 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_CMD_BMSK 0x2 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_CMD_SHFT 1 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CORE_BMSK 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CORE_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x) ((x) + 0x14) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_PHYS(x) ((x) + 0x14) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_OFFS (0x14) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK 0x1010101 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x1000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 24 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x10000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 16 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x100 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 8 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x) ((x) + 0x18) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_PHYS(x) ((x) + 0x18) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_OFFS (0x18) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK 0x3f3f3f +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x3f0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 16 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x3f00 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 8 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x3f +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_PHYS(x) ((x) + 0x1c) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OFFS (0x1c) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 24 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0xff0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 16 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x3f00 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 8 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x3f +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x) ((x) + 0x20) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_PHYS(x) ((x) + 0x20) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OFFS (0x20) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 24 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0xff0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 16 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x3f00 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 8 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x3f +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x) ((x) + 0x24) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_PHYS(x) ((x) + 0x24) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OFFS (0x24) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK 0xfffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_POR 0x00360000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_BMSK 0x8000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_SHFT 27 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_BMSK 0x4000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_SHFT 26 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_BMSK 0x2000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_SHFT 25 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK 0x1000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT 24 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK 0x800000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT 23 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x700000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 20 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0xe0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 17 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x1fe00 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 9 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x1fe +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x) ((x) + 0x28) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_PHYS(x) ((x) + 0x28) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OFFS (0x28) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK 0xffff0001 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_POR 0x00ff0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 16 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x) ((x) + 0x2c) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_PHYS(x) ((x) + 0x2c) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_OFFS (0x2c) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK 0xffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0xffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x) ((x) + 0x30) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_PHYS(x) ((x) + 0x30) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_OFFS (0x30) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 16 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0xffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR(x) ((x) + 0x34) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_PHYS(x) ((x) + 0x34) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_OFFS (0x34) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_RMSK 0xfffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0xe0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 17 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x10000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 16 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0xffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR(x) ((x) + 0x38) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_PHYS(x) ((x) + 0x38) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_OFFS (0x38) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_RMSK 0xfffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0xe0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 17 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x10000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 16 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0xffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS(x) ((x) + 0x3c) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_OFFS (0x3c) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x) ((x) + 0x40) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS(x) ((x) + 0x40) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_OFFS (0x40) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x) ((x) + 0x44) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS(x) ((x) + 0x44) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_OFFS (0x44) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x) ((x) + 0x48) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS(x) ((x) + 0x48) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_OFFS (0x48) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_PHYS(x) ((x) + 0x4c) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OFFS (0x4c) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_SHFT 16 +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_BMSK 0xffff +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x) ((x) + 0x50) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_PHYS(x) ((x) + 0x50) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OFFS (0x50) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK 0x1ffff +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_MISC_IE_BMSK 0x10000 +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_MISC_IE_SHFT 16 +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_BMSK 0xffff +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x) ((x) + 0x54) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_PHYS(x) ((x) + 0x54) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OFFS (0x54) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_BMSK 0xffff0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_SHFT 16 +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_BMSK 0xffff +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x) ((x) + 0x58) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_PHYS(x) ((x) + 0x58) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OFFS (0x58) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_SHFT 16 +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_BMSK 0xffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_PHYS(x) ((x) + 0x5c) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OFFS (0x5c) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK 0x1ffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_MISC_IE_BMSK 0x10000 +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_MISC_IE_SHFT 16 +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_BMSK 0xffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x) ((x) + 0x60) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_PHYS(x) ((x) + 0x60) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OFFS (0x60) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x) ((x) + 0x64) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_PHYS(x) ((x) + 0x64) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OFFS (0x64) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR(x) ((x) + 0x68) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_PHYS(x) ((x) + 0x68) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_OFFS (0x68) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_RMSK 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_SEED_2_BMSK 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_SEED_2_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_PHYS(x) ((x) + 0x6c) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OFFS (0x6c) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POLY_0_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POLY_0_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x) ((x) + 0x70) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_PHYS(x) ((x) + 0x70) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OFFS (0x70) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POLY_1_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POLY_1_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR(x) ((x) + 0x74) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_PHYS(x) ((x) + 0x74) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_OFFS (0x74) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_RMSK 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POLY_2_BMSK 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POLY_2_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x) ((x) + 0x78) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_PHYS(x) ((x) + 0x78) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_OFFS (0x78) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_POR 0x00000201 +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_PHYS(x) ((x) + 0x7c) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_OFFS (0x7c) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_POR 0x00000201 +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x) ((x) + 0x80) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_PHYS(x) ((x) + 0x80) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_OFFS (0x80) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_POR 0x00000201 +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x) ((x) + 0x84) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_PHYS(x) ((x) + 0x84) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_OFFS (0x84) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_POR 0x00000201 +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR(x) ((x) + 0x88) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_PHYS(x) ((x) + 0x88) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_OFFS (0x88) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_RMSK 0x1fffff +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IC_CLK_BMSK 0x100000 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IC_CLK_SHFT 20 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_DMA_CLK_BMSK 0xf0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_DMA_CLK_SHFT 16 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_CORE_CLK_BMSK 0xffff +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_CORE_CLK_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR(x) ((x) + 0x8c) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_PHYS(x) ((x) + 0x8c) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_OFFS (0x8c) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_RMSK 0x3ffff +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_CLK_EXTEND_BMSK 0x20000 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_CLK_EXTEND_SHFT 17 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_WRAPPER_REG_CLK_BMSK 0x10000 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_WRAPPER_REG_CLK_SHFT 16 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_CSM_REG_CLK_BMSK 0xffff +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_CSM_REG_CLK_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR(x) ((x) + 0x90) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_PHYS(x) ((x) + 0x90) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_OFFS (0x90) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_DST_SRNG_CLK_BMSK 0xffff0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_DST_SRNG_CLK_SHFT 16 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_SRC_SRNG_CLK_BMSK 0xffff +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_SRC_SRNG_CLK_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_3_ADDR(x) ((x) + 0x94) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_3_PHYS(x) ((x) + 0x94) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_3_OFFS (0x94) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_3_RMSK 0x1ffff +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_3_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_3_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_3_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_3_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_3_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_3_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_3_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_3_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_3_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_3_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_3_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_3_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_3_TZ_CLK_BMSK 0x10000 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_3_TZ_CLK_SHFT 16 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_3_STS_SRNG_CLK_BMSK 0xffff +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_3_STS_SRNG_CLK_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x) ((x) + 0x98) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_PHYS(x) ((x) + 0x98) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OFFS (0x98) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_RMSK 0xffff +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IDLE_CFG_BMSK 0xffff +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IDLE_CFG_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR(x) ((x) + 0x9c) +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_PHYS(x) ((x) + 0x9c) +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_OFFS (0x9c) +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_VALUE_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_PHYS(x) ((x) + 0xa0) +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OFFS (0xa0) +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_VAL_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_VAL_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_PHYS(x) ((x) + 0xa4) +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_OFFS (0xa4) +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_RMSK 0xf00ff +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_POR 0x0003000a +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA_PRIORITY_BMSK 0xf0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA_PRIORITY_SHFT 16 +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA3_READ_AXI_MAX_LENGTH_CFG_BMSK 0xc0 +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA3_READ_AXI_MAX_LENGTH_CFG_SHFT 6 +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA2_READ_AXI_MAX_LENGTH_CFG_BMSK 0x30 +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA2_READ_AXI_MAX_LENGTH_CFG_SHFT 4 +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA1_READ_AXI_MAX_LENGTH_CFG_BMSK 0xc +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA1_READ_AXI_MAX_LENGTH_CFG_SHFT 2 +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA0_READ_AXI_MAX_LENGTH_CFG_BMSK 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA0_READ_AXI_MAX_LENGTH_CFG_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_PHYS(x) ((x) + 0xa8) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_OFFS (0xa8) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_RMSK 0x1ffff +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_POR 0x0000ffff +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_CE_IDLE_INTR_STSRING_TPEQHP_EN_BMSK 0x10000 +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_CE_IDLE_INTR_STSRING_TPEQHP_EN_SHFT 16 +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_CE_CSM_IDLE_REQ_EN_BMSK 0xffff +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_CE_CSM_IDLE_REQ_EN_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_ADDR(x) ((x) + 0xac) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_PHYS(x) ((x) + 0xac) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_OFFS (0xac) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_RMSK 0x1ffff +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_POR 0x0001ffff +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_GXI_IDLE_BMSK 0x10000 +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_GXI_IDLE_SHFT 16 +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_CE_CSM_IDLE_BMSK 0xffff +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_CE_CSM_IDLE_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_PHYS(x) ((x) + 0xb0) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_OFFS (0xb0) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_RMSK 0x100ff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_POR 0x000000b5 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_BUS_SINGLE_TRIGGER_EN_BMSK 0x10000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_BUS_SINGLE_TRIGGER_EN_SHFT 16 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_WR_GRANT_HP_CNT_INIT_BMSK 0xe0 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_WR_GRANT_HP_CNT_INIT_SHFT 5 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_RD_GRANT_HP_CNT_INIT_BMSK 0x1c +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_RD_GRANT_HP_CNT_INIT_SHFT 2 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_WEIGHTED_ROUNDROBIN_EN_BMSK 0x2 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_WEIGHTED_ROUNDROBIN_EN_SHFT 1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_PRIORITY_EN_BMSK 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_PRIORITY_EN_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_ADDR(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_PHYS(x) ((x) + 0xb4) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_OFFS (0xb4) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_GXI_BUS_STATUS_0_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_GXI_BUS_STATUS_0_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_ADDR(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_PHYS(x) ((x) + 0xb8) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_OFFS (0xb8) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_GXI_BUS_STATUS_1_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_GXI_BUS_STATUS_1_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_ADDR(x) ((x) + 0xbc) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_PHYS(x) ((x) + 0xbc) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_OFFS (0xbc) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_GXI_BUS_STATUS_2_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_GXI_BUS_STATUS_2_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_ADDR(x) ((x) + 0xc0) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_PHYS(x) ((x) + 0xc0) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_OFFS (0xc0) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_GXI_BUS_STATUS_3_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_GXI_BUS_STATUS_3_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_ADDR(x) ((x) + 0xc4) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_PHYS(x) ((x) + 0xc4) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_OFFS (0xc4) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_GXI_BUS_STATUS_4_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_GXI_BUS_STATUS_4_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_ADDR(x) ((x) + 0xc8) +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_PHYS(x) ((x) + 0xc8) +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_OFFS (0xc8) +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RMSK 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_POR 0x00000003 +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RESET_CONFIG_N_BMSK 0x2 +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RESET_CONFIG_N_SHFT 1 +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RESET_CE_N_BMSK 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RESET_CE_N_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x) ((x) + 0x400) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_PHYS(x) ((x) + 0x400) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OFFS (0x400) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK 0x100ff +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x10000 +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 16 +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_BMSK 0xff +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x) ((x) + 0x404) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_PHYS(x) ((x) + 0x404) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OFFS (0x404) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_POR 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN(x)) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x) ((x) + 0x408) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_PHYS(x) ((x) + 0x408) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OFFS (0x408) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_POR 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN(x)) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_2_ADDR(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_2_PHYS(x) ((x) + 0x40c) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_2_OFFS (0x40c) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_2_RMSK 0xfff +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_2_POR 0x00000fff +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_2_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_2_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_2_ADDR(x), HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_2_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_2_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_2_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_2_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_2_IN(x)) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_2_MASK_BMSK 0xfff +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_2_MASK_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x) ((x) + 0x410) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_PHYS(x) ((x) + 0x410) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_OFFS (0x410) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x) ((x) + 0x414) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_PHYS(x) ((x) + 0x414) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_OFFS (0x414) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK 0xff +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_BMSK 0xff +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) ((x) + 0x418) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) ((x) + 0x418) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OFFS (0x418) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_POR 0x7ffe0002 +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 17 +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x1fffc +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 2 +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x2 +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 1 +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x1 +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0 + +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x) ((x) + 0x41c) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_PHYS(x) ((x) + 0x41c) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OFFS (0x41c) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK 0x1 +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_POR 0x00000000 +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_POR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN(x)) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0 + + +#endif -- GitLab From 5051c33aecd10b3732e20ba447d71872e4a5d71c Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 25 Jan 2022 06:00:50 -0800 Subject: [PATCH 11/42] fw-api: CL 17040921 - update fw common interface files Modify copyright to be Qualcomm Innovation Center in files modified in 2022 Change-Id: Ie04aac9816e43ac664f31a88270083673b5722cf CRs-Fixed: 2262693 --- fw/wmi_services.h | 3 ++- fw/wmi_tlv_defs.h | 3 ++- fw/wmi_unified.h | 3 ++- fw/wmi_version.h | 3 ++- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 92d4f2fe9f60..e25f5db1b74b 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2011-2022 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 6f3ab3fcba78..65cfc1f6b718 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2010-2022 The Linux Foundation. All rights reserved. + * Copyright (c) 2010-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 575c93fff50d..da191985c1b9 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2010-2022 The Linux Foundation. All rights reserved. + * Copyright (c) 2010-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * diff --git a/fw/wmi_version.h b/fw/wmi_version.h index c2589fd43247..70d1202b4e2c 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2012-2022 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * -- GitLab From e3147c936315dcdfdbc546767368bca2d678927d Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 26 Jan 2022 06:00:49 -0800 Subject: [PATCH 12/42] fw-api: CL 17052075 - update fw common interface files HTT stats: add TX_PDEV_SAWF_RATE stats defs (+ minor HTT stats doc improvements) Change-Id: I8cb1bf90e911c36f72ba7091e2de8fbe63875434 CRs-Fixed: 2262693 --- fw/htt.h | 2 ++ fw/htt_stats.h | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/fw/htt.h b/fw/htt.h index 2eff2c74616d..8f39e3ba1ea0 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2011-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -725,6 +726,7 @@ typedef enum { HTT_STATS_RX_PDEV_BE_UL_MIMO_USER_STATS_TAG = 141, /* htt_rx_pdev_be_ul_mimo_user_stats_tlv */ HTT_STATS_RX_RING_STATS_TAG = 142, /* htt_rx_fw_ring_stats_tlv_v */ HTT_STATS_RX_PDEV_BE_UL_TRIG_STATS_TAG = 143, /* htt_rx_pdev_be_ul_trigger_stats_tlv */ + HTT_STATS_TX_PDEV_SAWF_RATE_STATS_TAG = 144, /* htt_tx_pdev_rate_stats_sawf_tlv */ HTT_STATS_MAX_TAG, diff --git a/fw/htt_stats.h b/fw/htt_stats.h index cc069582153c..2c3ba33babc3 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -4105,6 +4105,13 @@ typedef struct { ((_var) |= ((_val) << HTT_TX_PDEV_RATE_STATS_MAC_ID_S)); \ } while (0) +#define HTT_TX_PDEV_STATS_NUM_MCS_DROP_COUNTERS \ + (HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS + \ + HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + \ + HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS) + +#define HTT_TX_PDEV_STATS_NUM_PER_COUNTERS 101 + /* * Introduce new TX counters to support 320MHz support and punctured modes */ @@ -4261,6 +4268,46 @@ typedef struct { A_UINT32 be_mu_mimo_tx_ldpc; } htt_tx_pdev_rate_stats_be_tlv; +typedef struct { + /* + * SAWF pdev rate stats; + * placed in a separate TLV to adhere to size restrictions + */ + htt_tlv_hdr_t tlv_hdr; + + /** + * Counter incremented when MCS is dropped due to the successive retries + * to a peer reaching the configured limit. + */ + A_UINT32 rate_retry_mcs_drop_cnt; + + /** + * histogram of MCS rate drop down, indexed by pre-drop MCS + */ + A_UINT32 mcs_drop_rate[HTT_TX_PDEV_STATS_NUM_MCS_DROP_COUNTERS]; + + /** + * PPDU PER histogram - each PPDU has its PER computed, + * and the bin corresponding to that PER percentage is incremented. + */ + A_UINT32 per_histogram_cnt[HTT_TX_PDEV_STATS_NUM_PER_COUNTERS]; + + /** + * When the service class contains delay bound rate parameters which + * indicate low latency and we enable latency-based RA params then + * the low_latency_rate_count will be incremented. + * This counts the number of peer-TIDs that have been categorized as + * low-latency. + */ + A_UINT32 low_latency_rate_cnt; + + /** Indicate how many times rate drop happened within SIFS burst */ + A_UINT32 su_burst_rate_drop_cnt; + + /** Indicates how many within SIFS burst failed to deliver any pkt */ + A_UINT32 su_burst_rate_drop_fail_cnt; +} htt_tx_pdev_rate_stats_sawf_tlv; + typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -4295,6 +4342,7 @@ typedef struct { typedef struct { htt_tx_pdev_rate_stats_tlv rate_tlv; htt_tx_pdev_rate_stats_be_tlv rate_be_tlv; + htt_tx_pdev_rate_stats_sawf_tlv rate_sawf_tlv; } htt_tx_pdev_rate_stats_t; /* == PDEV RX RATE CTRL STATS == */ -- GitLab From 050e1f5a1045aca9d4cab47f74916b48bd607f70 Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 26 Jan 2022 06:01:27 -0800 Subject: [PATCH 13/42] fw-api: CL 17053323 - update fw common interface files add WOW_P2P_NOA_EVENT def Change-Id: I56f522b2045c3c353ee850573df3750f0397eb95 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 2 ++ fw/wmi_version.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index da191985c1b9..4b5f4e0e3310 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -18088,6 +18088,7 @@ typedef enum event_type_e { WOW_DCS_INTERFERENCE_DET, /* 32 + 11 */ WOW_ROAM_STATS_EVENT, /* 32 + 12 */ WOW_RTT_11AZ_EVENT, /* 32 + 13 */ + WOW_P2P_NOA_EVENT, /* 32 + 14 */ } WOW_WAKE_EVENT_TYPE; typedef enum wake_reason_e { @@ -18166,6 +18167,7 @@ typedef enum wake_reason_e { WOW_REASON_ROAM_STATS, WOW_REASON_MDNS_WAKEUP, WOW_REASON_RTT_11AZ, + WOW_REASON_P2P_NOA_UPDATE, /* add new WOW_REASON_ defs before this line */ WOW_REASON_MAX, diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 70d1202b4e2c..1f1dbeb3062e 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1110 +#define __WMI_REVISION_ 1111 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 8aa63826c149a6f83d7ec7fefa32946305e96e09 Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 2 Feb 2022 12:01:00 -0800 Subject: [PATCH 14/42] fw-api: CL 17114670 - update fw common interface files Change-Id: I9ec8eaadf43fc083fe457958f44d90c60ad66295 WMI: add pdev_id in vdev_multiple_peer_group_cmd TLV CRs-Fixed: 2262693 --- fw/wmi_unified.h | 1 + fw/wmi_version.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 4b5f4e0e3310..0cdbc0719760 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -37324,6 +37324,7 @@ typedef struct { typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_multiple_peer_group_cmd_fixed_param */ A_UINT32 vdev_id; + A_UINT32 pdev_id; /** Sub command id - Currently supported command ids are * WMI_PEER_REMOVE_WDS_ENTRY_CMDID */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 1f1dbeb3062e..8ea20fa9fd85 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1111 +#define __WMI_REVISION_ 1112 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 445e2c769dcdd0f609eb0b29b3cdb256cddc8263 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 4 Feb 2022 18:00:56 -0800 Subject: [PATCH 15/42] fw-api: CL 17146895 - update fw common interface files HTT: add rx_mon_global_en + tx_mon_global_en flags add flags to enable rx + tx monitor mode, also fix errors in existing bitfield set macro defs Change-Id: Ida129c372a25cfd4b7ad64dfbd0ab95f2f6bcd72 CRs-Fixed: 2262693 --- fw/htt.h | 46 +++++++++++++++++++++++++++++++++++++--------- 1 file changed, 37 insertions(+), 9 deletions(-) diff --git a/fw/htt.h b/fw/htt.h index 8f39e3ba1ea0..fa6f4648b772 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -5543,7 +5543,9 @@ enum htt_srng_ring_id { * configuration fields are valid * b'27 - drop_thresh_valid (DT): flag to indicate if the * rx_drop_threshold field is valid - * b'28:31 - rsvd1: reserved for future use + * b'28 - rx_mon_global_en: Enable/Disable global register + 8 configuration in Rx monitor module. + * b'29:31 - rsvd1: reserved for future use * dword1 - b'0:15 - ring_buffer_size: size of bufferes referenced by rx ring, * in byte units. * Valid only for HW_TO_SW_RING and SW_TO_HW_RING @@ -5699,7 +5701,8 @@ PREPACK struct htt_rx_ring_selection_cfg_t { pkt_swap: 1, rx_offsets_valid: 1, drop_thresh_valid: 1, - rsvd1: 4; + rx_mon_global_en: 1, + rsvd1: 3; A_UINT32 ring_buffer_size: 16, config_length_mgmt:3, config_length_ctrl:3, @@ -5811,6 +5814,17 @@ PREPACK struct htt_rx_ring_selection_cfg_t { ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_S)); \ } while (0) +#define HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_M 0x10000000 +#define HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_S 28 +#define HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_GET(_var) \ + (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_M) >> \ + HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_S) +#define HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_S)); \ + } while (0) + #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_M 0x0000ffff #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_S 0 #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_GET(_var) \ @@ -5830,7 +5844,7 @@ PREPACK struct htt_rx_ring_selection_cfg_t { #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_S)); \ + ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_S)); \ } while (0) #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_M 0x00380000 @@ -6701,7 +6715,9 @@ PREPACK struct htt_rx_ring_selection_cfg_t { * b'25 - pkt_swap (PS): 1 is to swap packet TLV - refer to * BUF_RING_CFG_0 defs within HW .h files, * e.g. wmac_top_reg_seq_hwioreg.h - * b'26:31 - rsvd1: reserved for future use + * b'26 - tx_mon_global_en: Enable/Disable global register + * configuration in Tx monitor module. + * b'27:31 - rsvd1: reserved for future use * dword1 - b'0:15 - ring_buffer_size: size of bufferes referenced by rx ring, * in byte units. * Valid only for HW_TO_SW_RING and SW_TO_HW_RING @@ -6846,7 +6862,8 @@ PREPACK struct htt_tx_monitor_cfg_t { ring_id: 8, status_swap: 1, pkt_swap: 1, - rsvd1: 6; + tx_mon_global_en: 1, + rsvd1: 5; A_UINT32 ring_buffer_size: 16, config_length_mgmt: 3, config_length_ctrl: 3, @@ -6930,6 +6947,17 @@ PREPACK struct htt_tx_monitor_cfg_t { ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PKT_SWAP_S)); \ } while (0) +#define HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_M 0x04000000 +#define HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_S 26 +#define HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_GET(_var) \ + (((_var) & HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_M) >> \ + HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_S) +#define HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN, _val); \ + ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_S)); \ + } while (0) + #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_M 0x0000ffff #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_S 0 #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_GET(_var) \ @@ -7005,7 +7033,7 @@ PREPACK struct htt_tx_monitor_cfg_t { do { \ HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL, _val); \ ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_S)); \ - } while (0 + } while (0) #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_M 0x00000020 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_S 5 @@ -7038,7 +7066,7 @@ PREPACK struct htt_tx_monitor_cfg_t { do { \ HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL, _val); \ ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_S)); \ - } while (0 + } while (0) #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_M 0x00000100 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_S 8 @@ -7071,7 +7099,7 @@ PREPACK struct htt_tx_monitor_cfg_t { do { \ HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL, _val); \ ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_S)); \ - } while (0 + } while (0) #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_M 0x00000800 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_S 11 @@ -7104,7 +7132,7 @@ PREPACK struct htt_tx_monitor_cfg_t { do { \ HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL, _val); \ ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_S)); \ - } while (0 + } while (0) #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_M 0x00004000 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_S 14 -- GitLab From 44452904a99c826e72f2b10c0ea2e3ac2023fce8 Mon Sep 17 00:00:00 2001 From: spuligil Date: Sat, 5 Feb 2022 06:00:53 -0800 Subject: [PATCH 16/42] fw-api: CL 17148867 - update fw common interface files Change-Id: I52133248d94c871fbdfae85df16b45255768307d WMI: ext WMI_VDEV_PARAM_BA_MODE values, add tx+rx mgmt ext params CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 8 +++-- fw/wmi_unified.h | 76 +++++++++++++++++++++++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 83 insertions(+), 3 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 65cfc1f6b718..0036baeff2a7 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1240,6 +1240,8 @@ typedef enum { WMITLV_TAG_STRUC_wmi_rtt_pasn_peer_delete_event_fixed_param, WMITLV_TAG_STRUC_wmi_rtt_pasn_peer_delete_param, WMITLV_TAG_STRUC_wmi_rtt_pasn_deauth_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_tx_send_params_ext, + WMITLV_TAG_STRUC_wmi_mgmt_rx_params_ext, } WMITLV_TAG_ID; /* @@ -2871,7 +2873,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MGMT_TX_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mgmt_tx_send_cmd_fixed_param, wmi_mgmt_tx_send_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tx_send_params, wmi_tx_send_params, tx_send_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_tx_send_params, mlo_tx_send_params, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_tx_send_params, mlo_tx_send_params, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tx_send_params_ext, tx_send_params_ext, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_MGMT_TX_SEND_CMDID); @@ -5192,7 +5195,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STA_KICKOUT_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mgmt_rx_hdr, wmi_mgmt_rx_hdr, hdr, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rssi_ctl_ext, rssi_ctl_ext, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mgmt_rx_reo_params, wmi_mgmt_rx_reo_params, reo_params, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mgmt_rx_reo_params, wmi_mgmt_rx_reo_params, reo_params, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mgmt_rx_params_ext, mgmt_rx_params_ext, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_MGMT_RX_EVENTID); /* Management Rx FW Consumed Event */ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 0cdbc0719760..cf27c6e69767 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -5556,6 +5556,44 @@ typedef struct { A_UINT32 mgmt_pkt_ctr_link_info; } wmi_mgmt_rx_reo_params; +/** Helper macro for param GET/SET */ +#define WMI_RX_PARAM_EXT_META_ID_GET(mgmt_rx_params_ext_dword0) WMI_GET_BITS(mgmt_rx_params_ext_dword0, 0, 3) +#define WMI_RX_PARAM_EXT_META_ID_SET(mgmt_rx_params_ext_dword0, value) WMI_SET_BITS(mgmt_rx_params_ext_dword0, 0, 3, value) + +#define WMI_RX_PARAM_EXT_BA_WIN_SIZE_GET(mgmt_rx_params_ext_dword1) WMI_GET_BITS(mgmt_rx_params_ext_dword1, 0, 16) +#define WMI_RX_PARAM_EXT_BA_WIN_SIZE_SET(mgmt_rx_params_ext_dword1, value) WMI_SET_BITS(mgmt_rx_params_ext_dword1, 0, 16, value) + +#define WMI_RX_PARAM_EXT_REO_WIN_SIZE_GET(mgmt_rx_params_ext_dword1) WMI_GET_BITS(mgmt_rx_params_ext_dword1, 16, 16) +#define WMI_RX_PARAM_EXT_REO_WIN_SIZE_SET(mgmt_rx_params_ext_dword1, value) WMI_SET_BITS(mgmt_rx_params_ext_dword1, 16, 16, value) + +typedef enum { + WMI_RX_PARAMS_EXT_META_ADDBA = 0x0, +} wmi_mgmt_rx_params_ext_meta_t; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag (WMITLV_TAG_STRUC_wmi_mgmt_rx_params_ext) and len */ + union { + struct { + A_UINT32 + /* Describes the representation of the data in rx_param_ext_dword1 + * Full set shown in wmi_mgmt_rx_params_ext_meta_t */ + meta_id : 3, + /* Dedicated for commonly used parameters only */ + reserved_0 : 29; + }; + A_UINT32 mgmt_rx_params_ext_dword0; + }; + union { + struct { + /* WMI_RX_PARAMS_EXT_META_ADDBA */ + A_UINT32 + ba_win_size :16, /* negotiated BA window size */ + reo_win_size :16; /* 2x the negotiated BA window size to handle any latency across MLO */ + }; + A_UINT32 mgmt_rx_params_ext_dword1; + }; +} wmi_mgmt_rx_params_ext; + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mgmt_rx_hdr */ /** channel on which this frame is received (channel number) */ @@ -5614,6 +5652,10 @@ typedef struct { * This TLV is followed by struct: * wmi_mgmt_rx_reo_params reo_params;// MGMT rx REO params */ +/* + * This TLV is optionally followed by struct: + * wmi_mgmt_rx_params_ext mgmt_rx_params_ext[0 or 1]; + */ } wmi_mgmt_rx_hdr; /* WMI CMD to receive the management filter criteria from the host */ @@ -6020,6 +6062,36 @@ typedef struct { */ } wmi_mgmt_tx_hdr; +#define WMI_TX_SEND_PARAM_EXT_META_ID_GET(tx_param_ext_dword0) WMI_GET_BITS(tx_param_dword0, 0, 3) +#define WMI_TX_SEND_PARAM_EXT_META_ID_SET(tx_param_ext_dword0, value) WMI_SET_BITS(tx_param_dword0, 0, 3, value) + +#define WMI_TX_SEND_PARAM_EXT_WIN_SIZE_GET(tx_param_ext_dword1) WMI_GET_BITS(tx_param_dword1, 0, 16) +#define WMI_TX_SEND_PARAM_EXT_WIN_SIZE_SET(tx_param_ext_dword1, value) WMI_SET_BITS(tx_param_dword1, 0, 16, value) + +typedef enum { + WMI_TX_SEND_PARAMS_EXT_META_ADDBA = 0x0, + WMI_TX_SEND_PARAMS_EXT_META_DELBA = 0x1, +} wmi_tx_send_params_ext_meta_t; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag (WMITLV_TAG_STRUC_wmi_tx_send_params_ext) and len */ + union { + struct { + A_UINT32 meta_id : 3, /* Describes the representation of the data in tx_param_ext_dword1 Full set shown in wmi_tx_send_params_ext_meta_t */ + reserved_0 : 29; /* Dedicated for commonly used parameters only */ + }; + A_UINT32 tx_param_ext_dword0; + }; + union { + struct { + /* WMI_TX_SEND_PARAMS_EXT_META_ADDBA */ + A_UINT32 win_size : 16, + reserved_1 : 16; + }; + A_UINT32 tx_param_ext_dword1; + }; +} wmi_tx_send_params_ext; + #define WMI_TX_SEND_PARAM_PWR_GET(tx_param_dword0) WMI_GET_BITS(tx_param_dword0, 0, 8) #define WMI_TX_SEND_PARAM_PWR_SET(tx_param_dword0, value) WMI_SET_BITS(tx_param_dword0, 0, 8, value) @@ -6262,6 +6334,7 @@ typedef struct { /* This TLV is followed by wmi_tx_send_params * wmi_tx_send_params tx_send_params; * wmi_mlo_tx_send_params mlo_tx_send_params[]; + * wmi_tx_send_params_ext tx_send_params_ext[0 or 1]; */ } wmi_mgmt_tx_send_cmd_fixed_param; @@ -13089,6 +13162,9 @@ typedef enum { * 1- Manual mode(addba req not sent). * 2- buffer size 64 * 3- buffer size 256 + * 4- buffer size 128 // placeholder, not valid + * 5- buffer size 512 + * 6- buffer size 1024 */ WMI_VDEV_PARAM_BA_MODE, /* 0x7e */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 8ea20fa9fd85..f1ab7adc336d 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1112 +#define __WMI_REVISION_ 1113 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 13a718c427ce65aca6485d08bb56b12516b53213 Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 8 Feb 2022 18:00:59 -0800 Subject: [PATCH 17/42] fw-api: CL 17178398 - update fw common interface files add WMI_IS_RADAR_FOUND_CHAN_FREQ_IS_CENTER_FREQ def Change-Id: Iabed3a011b669e819a96770e9c797c65b726ed19 CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + fw/wmi_version.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index e25f5db1b74b..2d95602afac7 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -575,6 +575,7 @@ typedef enum { WMI_SERVICE_MULTIPLE_PEER_GROUP_CMD_SUPPORT = 322, /* FW support for multiple peer group command */ WMI_SERVICE_AFC_RESET_SUPPORT = 323, /* Indicates FW supports AFC reset */ WMI_SERVICE_FP_PHY_ERR_FILTER_SUPPORT = 324, /* FW supports monitor ring configurations for filtering in PHY error packets */ + WMI_IS_RADAR_FOUND_CHAN_FREQ_IS_CENTER_FREQ = 325, /* FW Supporting radar event on the actual center frequency radar was detected */ WMI_MAX_EXT2_SERVICE diff --git a/fw/wmi_version.h b/fw/wmi_version.h index f1ab7adc336d..1af8f408ac81 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1113 +#define __WMI_REVISION_ 1114 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From dce3d0a306c9b6a4ef0c746d68521bcbe3a6c0b8 Mon Sep 17 00:00:00 2001 From: Srinivas Girigowda Date: Tue, 18 Jan 2022 19:14:36 -0800 Subject: [PATCH 18/42] fw-api: kiwi: Get V2 HW header files for kiwi Bring in V2 HW header files for kiwi, also cleanup the header files 1. Remove comments; 2. Add appropriate copyright header; 3. Remove references to HW sensitive IP (structs, macros and etc). Change-Id: I1137bc7f05780305d9c6213ef70a06648a10386f CRs-Fixed: 3122903 --- hw/kiwi/v2/HALcomdef.h | 52 + hw/kiwi/v2/HALhwio.h | 301 +++++ hw/kiwi/v2/beryllium_top_reg.h | 27 + hw/kiwi/v2/buffer_addr_info.h | 63 + hw/kiwi/v2/ce_src_desc.h | 140 +++ hw/kiwi/v2/ce_stat_desc.h | 133 ++ hw/kiwi/v2/com_dtypes.h | 182 +++ hw/kiwi/v2/he_sig_a_mu_dl_info.h | 189 +++ hw/kiwi/v2/he_sig_a_mu_ul_info.h | 119 ++ hw/kiwi/v2/he_sig_a_su_info.h | 224 ++++ hw/kiwi/v2/he_sig_b1_mu_info.h | 56 + hw/kiwi/v2/he_sig_b2_mu_info.h | 112 ++ hw/kiwi/v2/he_sig_b2_ofdma_info.h | 112 ++ hw/kiwi/v2/ht_sig_info.h | 147 +++ hw/kiwi/v2/l_sig_a_info.h | 98 ++ hw/kiwi/v2/l_sig_b_info.h | 63 + hw/kiwi/v2/macrx_abort_request_info.h | 49 + hw/kiwi/v2/msmhwiobase.h | 191 +++ hw/kiwi/v2/msmhwioreg.h | 134 ++ hw/kiwi/v2/phyrx_abort_request_info.h | 70 ++ hw/kiwi/v2/phyrx_common_user_info.h | 170 +++ hw/kiwi/v2/phyrx_he_sig_a_mu_dl.h | 150 +++ hw/kiwi/v2/phyrx_he_sig_a_mu_ul.h | 100 ++ hw/kiwi/v2/phyrx_he_sig_a_su.h | 175 +++ hw/kiwi/v2/phyrx_he_sig_b1_mu.h | 62 + hw/kiwi/v2/phyrx_he_sig_b2_mu.h | 95 ++ hw/kiwi/v2/phyrx_he_sig_b2_ofdma.h | 95 ++ hw/kiwi/v2/phyrx_ht_sig.h | 120 ++ hw/kiwi/v2/phyrx_l_sig_a.h | 92 ++ hw/kiwi/v2/phyrx_l_sig_b.h | 67 + hw/kiwi/v2/phyrx_location.h | 355 ++++++ .../v2/phyrx_other_receive_info_ru_details.h | 65 + hw/kiwi/v2/phyrx_pkt_end.h | 440 +++++++ hw/kiwi/v2/phyrx_pkt_end_info.h | 471 +++++++ hw/kiwi/v2/phyrx_rssi_legacy.h | 836 +++++++++++++ hw/kiwi/v2/phyrx_user_info.h | 210 ++++ hw/kiwi/v2/phyrx_vht_sig_a.h | 130 ++ hw/kiwi/v2/receive_rssi_info.h | 483 ++++++++ hw/kiwi/v2/receive_user_info.h | 275 ++++ .../reo_descriptor_threshold_reached_status.h | 275 ++++ hw/kiwi/v2/reo_destination_ring.h | 286 +++++ hw/kiwi/v2/reo_destination_ring_with_pn.h | 244 ++++ hw/kiwi/v2/reo_entrance_ring.h | 258 ++++ hw/kiwi/v2/reo_flush_cache.h | 174 +++ hw/kiwi/v2/reo_flush_cache_status.h | 303 +++++ hw/kiwi/v2/reo_flush_queue.h | 139 +++ hw/kiwi/v2/reo_flush_queue_status.h | 247 ++++ hw/kiwi/v2/reo_flush_timeout_list.h | 132 ++ hw/kiwi/v2/reo_flush_timeout_list_status.h | 261 ++++ hw/kiwi/v2/reo_get_queue_stats.h | 132 ++ hw/kiwi/v2/reo_get_queue_stats_status.h | 324 +++++ hw/kiwi/v2/reo_unblock_cache.h | 132 ++ hw/kiwi/v2/reo_unblock_cache_status.h | 254 ++++ hw/kiwi/v2/reo_update_rx_reo_queue.h | 440 +++++++ hw/kiwi/v2/reo_update_rx_reo_queue_status.h | 240 ++++ hw/kiwi/v2/rx_attention.h | 394 ++++++ hw/kiwi/v2/rx_flow_search_entry.h | 231 ++++ hw/kiwi/v2/rx_location_info.h | 476 +++++++ hw/kiwi/v2/rx_mpdu_desc_info.h | 119 ++ hw/kiwi/v2/rx_mpdu_details.h | 121 ++ hw/kiwi/v2/rx_mpdu_end.h | 200 +++ hw/kiwi/v2/rx_mpdu_info.h | 836 +++++++++++++ hw/kiwi/v2/rx_mpdu_link_ptr.h | 58 + hw/kiwi/v2/rx_mpdu_start.h | 620 +++++++++ hw/kiwi/v2/rx_msdu_desc_info.h | 154 +++ hw/kiwi/v2/rx_msdu_details.h | 179 +++ hw/kiwi/v2/rx_msdu_end.h | 1103 +++++++++++++++++ hw/kiwi/v2/rx_msdu_ext_desc_info.h | 77 ++ hw/kiwi/v2/rx_msdu_link.h | 948 ++++++++++++++ hw/kiwi/v2/rx_msdu_start.h | 317 +++++ hw/kiwi/v2/rx_ppdu_end_user_stats.h | 599 +++++++++ hw/kiwi/v2/rx_ppdu_end_user_stats_ext.h | 151 +++ hw/kiwi/v2/rx_ppdu_start.h | 93 ++ hw/kiwi/v2/rx_ppdu_start_user_info.h | 210 ++++ hw/kiwi/v2/rx_reo_queue.h | 515 ++++++++ hw/kiwi/v2/rx_reo_queue_ext.h | 391 ++++++ hw/kiwi/v2/rx_rxpcu_classification_overview.h | 112 ++ hw/kiwi/v2/rx_timing_offset_info.h | 49 + hw/kiwi/v2/rxpcu_ppdu_end_info.h | 788 ++++++++++++ hw/kiwi/v2/rxpcu_ppdu_end_layout_info.h | 338 +++++ hw/kiwi/v2/rxpt_classify_info.h | 133 ++ hw/kiwi/v2/seq_hwio.h | 56 + hw/kiwi/v2/tcl_data_cmd.h | 296 +++++ hw/kiwi/v2/tcl_gse_cmd.h | 161 +++ hw/kiwi/v2/tcl_status_ring.h | 147 +++ hw/kiwi/v2/tlv_hdr.h | 424 +++++++ hw/kiwi/v2/tlv_tag_def.h | 501 ++++++++ hw/kiwi/v2/tx_msdu_extension.h | 378 ++++++ hw/kiwi/v2/tx_rate_stats_info.h | 112 ++ hw/kiwi/v2/uniform_descriptor_header.h | 56 + hw/kiwi/v2/uniform_reo_cmd_header.h | 56 + hw/kiwi/v2/uniform_reo_status_header.h | 70 ++ hw/kiwi/v2/vht_sig_a_info.h | 161 +++ hw/kiwi/v2/wbm2sw_completion_ring_rx.h | 312 +++++ hw/kiwi/v2/wbm2sw_completion_ring_tx.h | 261 ++++ hw/kiwi/v2/wbm_buffer_ring.h | 58 + hw/kiwi/v2/wbm_link_descriptor_ring.h | 58 + hw/kiwi/v2/wbm_release_ring.h | 135 ++ hw/kiwi/v2/wbm_release_ring_rx.h | 321 +++++ hw/kiwi/v2/wbm_release_ring_tx.h | 277 +++++ hw/kiwi/v2/wcss_seq_hwiobase.h | 111 ++ hw/kiwi/v2/wcss_seq_hwioreg_umac.h | 324 +++++ hw/kiwi/v2/wcss_version.h | 20 + 103 files changed, 24201 insertions(+) create mode 100644 hw/kiwi/v2/HALcomdef.h create mode 100644 hw/kiwi/v2/HALhwio.h create mode 100644 hw/kiwi/v2/beryllium_top_reg.h create mode 100644 hw/kiwi/v2/buffer_addr_info.h create mode 100644 hw/kiwi/v2/ce_src_desc.h create mode 100644 hw/kiwi/v2/ce_stat_desc.h create mode 100644 hw/kiwi/v2/com_dtypes.h create mode 100644 hw/kiwi/v2/he_sig_a_mu_dl_info.h create mode 100644 hw/kiwi/v2/he_sig_a_mu_ul_info.h create mode 100644 hw/kiwi/v2/he_sig_a_su_info.h create mode 100644 hw/kiwi/v2/he_sig_b1_mu_info.h create mode 100644 hw/kiwi/v2/he_sig_b2_mu_info.h create mode 100644 hw/kiwi/v2/he_sig_b2_ofdma_info.h create mode 100644 hw/kiwi/v2/ht_sig_info.h create mode 100644 hw/kiwi/v2/l_sig_a_info.h create mode 100644 hw/kiwi/v2/l_sig_b_info.h create mode 100644 hw/kiwi/v2/macrx_abort_request_info.h create mode 100644 hw/kiwi/v2/msmhwiobase.h create mode 100644 hw/kiwi/v2/msmhwioreg.h create mode 100644 hw/kiwi/v2/phyrx_abort_request_info.h create mode 100644 hw/kiwi/v2/phyrx_common_user_info.h create mode 100644 hw/kiwi/v2/phyrx_he_sig_a_mu_dl.h create mode 100644 hw/kiwi/v2/phyrx_he_sig_a_mu_ul.h create mode 100644 hw/kiwi/v2/phyrx_he_sig_a_su.h create mode 100644 hw/kiwi/v2/phyrx_he_sig_b1_mu.h create mode 100644 hw/kiwi/v2/phyrx_he_sig_b2_mu.h create mode 100644 hw/kiwi/v2/phyrx_he_sig_b2_ofdma.h create mode 100644 hw/kiwi/v2/phyrx_ht_sig.h create mode 100644 hw/kiwi/v2/phyrx_l_sig_a.h create mode 100644 hw/kiwi/v2/phyrx_l_sig_b.h create mode 100644 hw/kiwi/v2/phyrx_location.h create mode 100644 hw/kiwi/v2/phyrx_other_receive_info_ru_details.h create mode 100644 hw/kiwi/v2/phyrx_pkt_end.h create mode 100644 hw/kiwi/v2/phyrx_pkt_end_info.h create mode 100644 hw/kiwi/v2/phyrx_rssi_legacy.h create mode 100644 hw/kiwi/v2/phyrx_user_info.h create mode 100644 hw/kiwi/v2/phyrx_vht_sig_a.h create mode 100644 hw/kiwi/v2/receive_rssi_info.h create mode 100644 hw/kiwi/v2/receive_user_info.h create mode 100644 hw/kiwi/v2/reo_descriptor_threshold_reached_status.h create mode 100644 hw/kiwi/v2/reo_destination_ring.h create mode 100644 hw/kiwi/v2/reo_destination_ring_with_pn.h create mode 100644 hw/kiwi/v2/reo_entrance_ring.h create mode 100644 hw/kiwi/v2/reo_flush_cache.h create mode 100644 hw/kiwi/v2/reo_flush_cache_status.h create mode 100644 hw/kiwi/v2/reo_flush_queue.h create mode 100644 hw/kiwi/v2/reo_flush_queue_status.h create mode 100644 hw/kiwi/v2/reo_flush_timeout_list.h create mode 100644 hw/kiwi/v2/reo_flush_timeout_list_status.h create mode 100644 hw/kiwi/v2/reo_get_queue_stats.h create mode 100644 hw/kiwi/v2/reo_get_queue_stats_status.h create mode 100644 hw/kiwi/v2/reo_unblock_cache.h create mode 100644 hw/kiwi/v2/reo_unblock_cache_status.h create mode 100644 hw/kiwi/v2/reo_update_rx_reo_queue.h create mode 100644 hw/kiwi/v2/reo_update_rx_reo_queue_status.h create mode 100644 hw/kiwi/v2/rx_attention.h create mode 100644 hw/kiwi/v2/rx_flow_search_entry.h create mode 100644 hw/kiwi/v2/rx_location_info.h create mode 100644 hw/kiwi/v2/rx_mpdu_desc_info.h create mode 100644 hw/kiwi/v2/rx_mpdu_details.h create mode 100644 hw/kiwi/v2/rx_mpdu_end.h create mode 100644 hw/kiwi/v2/rx_mpdu_info.h create mode 100644 hw/kiwi/v2/rx_mpdu_link_ptr.h create mode 100644 hw/kiwi/v2/rx_mpdu_start.h create mode 100644 hw/kiwi/v2/rx_msdu_desc_info.h create mode 100644 hw/kiwi/v2/rx_msdu_details.h create mode 100644 hw/kiwi/v2/rx_msdu_end.h create mode 100644 hw/kiwi/v2/rx_msdu_ext_desc_info.h create mode 100644 hw/kiwi/v2/rx_msdu_link.h create mode 100644 hw/kiwi/v2/rx_msdu_start.h create mode 100644 hw/kiwi/v2/rx_ppdu_end_user_stats.h create mode 100644 hw/kiwi/v2/rx_ppdu_end_user_stats_ext.h create mode 100644 hw/kiwi/v2/rx_ppdu_start.h create mode 100644 hw/kiwi/v2/rx_ppdu_start_user_info.h create mode 100644 hw/kiwi/v2/rx_reo_queue.h create mode 100644 hw/kiwi/v2/rx_reo_queue_ext.h create mode 100644 hw/kiwi/v2/rx_rxpcu_classification_overview.h create mode 100644 hw/kiwi/v2/rx_timing_offset_info.h create mode 100644 hw/kiwi/v2/rxpcu_ppdu_end_info.h create mode 100644 hw/kiwi/v2/rxpcu_ppdu_end_layout_info.h create mode 100644 hw/kiwi/v2/rxpt_classify_info.h create mode 100644 hw/kiwi/v2/seq_hwio.h create mode 100644 hw/kiwi/v2/tcl_data_cmd.h create mode 100644 hw/kiwi/v2/tcl_gse_cmd.h create mode 100644 hw/kiwi/v2/tcl_status_ring.h create mode 100644 hw/kiwi/v2/tlv_hdr.h create mode 100644 hw/kiwi/v2/tlv_tag_def.h create mode 100644 hw/kiwi/v2/tx_msdu_extension.h create mode 100644 hw/kiwi/v2/tx_rate_stats_info.h create mode 100644 hw/kiwi/v2/uniform_descriptor_header.h create mode 100644 hw/kiwi/v2/uniform_reo_cmd_header.h create mode 100644 hw/kiwi/v2/uniform_reo_status_header.h create mode 100644 hw/kiwi/v2/vht_sig_a_info.h create mode 100644 hw/kiwi/v2/wbm2sw_completion_ring_rx.h create mode 100644 hw/kiwi/v2/wbm2sw_completion_ring_tx.h create mode 100644 hw/kiwi/v2/wbm_buffer_ring.h create mode 100644 hw/kiwi/v2/wbm_link_descriptor_ring.h create mode 100644 hw/kiwi/v2/wbm_release_ring.h create mode 100644 hw/kiwi/v2/wbm_release_ring_rx.h create mode 100644 hw/kiwi/v2/wbm_release_ring_tx.h create mode 100644 hw/kiwi/v2/wcss_seq_hwiobase.h create mode 100644 hw/kiwi/v2/wcss_seq_hwioreg_umac.h create mode 100644 hw/kiwi/v2/wcss_version.h diff --git a/hw/kiwi/v2/HALcomdef.h b/hw/kiwi/v2/HALcomdef.h new file mode 100644 index 000000000000..93f1b161cd5e --- /dev/null +++ b/hw/kiwi/v2/HALcomdef.h @@ -0,0 +1,52 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef HAL_COMDEF_H +#define HAL_COMDEF_H + +#ifndef _ARM_ASM_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "com_dtypes.h" + +#ifndef _BOOL32_DEFINED +typedef unsigned long int bool32; +#define _BOOL32_DEFINED +#endif + +#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF + + #define inp(port) (*((volatile byte *) (port))) + #define inpw(port) (*((volatile word *) (port))) + #define inpdw(port) (*((volatile dword *)(port))) + + #define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val))) + #define outpw(port, val) (*((volatile word *) (port)) = ((word) (val))) + #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val))) + +#ifdef __cplusplus +} +#endif + +#endif + +#endif diff --git a/hw/kiwi/v2/HALhwio.h b/hw/kiwi/v2/HALhwio.h new file mode 100644 index 000000000000..13838379ad30 --- /dev/null +++ b/hw/kiwi/v2/HALhwio.h @@ -0,0 +1,301 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef HAL_HWIO_H +#define HAL_HWIO_H + +#include "HALcomdef.h" + +#define HWIO_BASE_PTR(base) base##_BASE_PTR + +#ifdef __ARMCC_VERSION + #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base) +#else + #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base) +#endif + +#ifdef CONFIG_WHAL_MM +#define SEQ_WCSS_WCMN_OFFSET SEQ_WCSS_TOP_CMN_OFFSET +#define SEQ_WCSS_PMM_OFFSET SEQ_WCSS_PMM_TOP_OFFSET +#endif + +#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym) +#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index) +#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2) +#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3) + +#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym) +#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index) +#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2) +#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym) +#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index) +#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2) +#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3) + +#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym) +#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index) +#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2) +#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym) +#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index) +#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2) +#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3) + +#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym) +#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index) +#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2) +#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3) + +#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask) +#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask) +#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask) +#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) + +#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) + +#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym) +#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index) +#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2) +#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask) +#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask) +#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) +#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) + +#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) + +#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val) +#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val) +#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val) +#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val) + +#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val) +#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val) +#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val) +#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val) + +#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) + +#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) + +#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val) +#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val) +#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val) +#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) + +#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val) +#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) +#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) +#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) +#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val) +#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val) +#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val) + +#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2)) +#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) ) +#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) ) + +#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) + +#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) + +#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym) +#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index) +#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym) +#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym) +#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym) +#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val) +#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) +#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) + +#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym) +#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index) + +#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN +#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index) +#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2) +#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3) +#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask) +#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask) +#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask) +#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask) +#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val) +#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val) +#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val) +#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val) +#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val) +#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val) +#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val) +#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val) +#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR +#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index) +#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2) +#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3) +#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS +#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index) +#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2) +#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3) +#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS +#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index) +#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2) +#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3) +#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK +#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index) +#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK +#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT +#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT +#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow +#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index) +#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL + +#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base) +#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index) +#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2) +#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3) +#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask) +#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask) +#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask) +#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask) +#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val) +#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val) +#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val) +#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val) +#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val) +#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + } +#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + HWIO_##hwiosym##_OUTM(base, mask3, val3); \ + } +#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + HWIO_##hwiosym##_OUTM(base, mask3, val3); \ + HWIO_##hwiosym##_OUTM(base, mask4, val4); \ + } + +#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val) +#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val) +#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val) +#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base) +#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index) +#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2) +#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3) +#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base) +#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index) +#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2) +#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3) + +#define HWIO_INTLOCK() +#define HWIO_INTFREE() + +#define __inp(port) (*((volatile uint8 *) (port))) +#define __inpw(port) (*((volatile uint16 *) (port))) +#define __inpdw(port) (*((volatile uint32 *) (port))) +#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val))) +#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val))) +#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val))) + +#ifdef HAL_HWIO_EXTERNAL + +#undef __inp +#undef __inpw +#undef __inpdw +#undef __outp +#undef __outpw +#undef __outpdw + +#define __inp(port) __inp_extern(port) +#define __inpw(port) __inpw_extern(port) +#define __inpdw(port) __inpdw_extern(port) +#define __outp(port, val) __outp_extern(port, val) +#define __outpw(port, val) __outpw_extern(port, val) +#define __outpdw(port, val) __outpdw_extern(port, val) + +extern uint8 __inp_extern ( uint32 nAddr ); +extern uint16 __inpw_extern ( uint32 nAddr ); +extern uint32 __inpdw_extern ( uint32 nAddr ); +extern void __outp_extern ( uint32 nAddr, uint8 nData ); +extern void __outpw_extern ( uint32 nAddr, uint16 nData ); +extern void __outpdw_extern ( uint32 nAddr, uint32 nData ); + +#endif + +#define in_byte(addr) (__inp(addr)) +#define in_byte_masked(addr, mask) (__inp(addr) & (mask)) +#define out_byte(addr, val) __outp(addr,val) +#define out_byte_masked(io, mask, val, shadow) \ + HWIO_INTLOCK(); \ + out_byte( io, shadow); \ + shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ + HWIO_INTFREE() +#define out_byte_masked_ns(io, mask, val, current_reg_content) \ + out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \ + ((uint16)((val) & (mask)))) ) + +#define in_word(addr) (__inpw(addr)) +#define in_word_masked(addr, mask) (__inpw(addr) & (mask)) +#define out_word(addr, val) __outpw(addr,val) +#define out_word_masked(io, mask, val, shadow) \ + HWIO_INTLOCK( ); \ + shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ + out_word( io, shadow); \ + HWIO_INTFREE( ) +#define out_word_masked_ns(io, mask, val, current_reg_content) \ + out_word( io, ((current_reg_content & (uint16)(~(mask))) | \ + ((uint16)((val) & (mask)))) ) + +#define in_dword(addr) (__inpdw(addr)) +#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask)) +#define out_dword(addr, val) __outpdw(addr,val) +#define out_dword_masked(io, mask, val, shadow) \ + HWIO_INTLOCK(); \ + shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \ + out_dword( io, shadow); \ + HWIO_INTFREE() +#define out_dword_masked_ns(io, mask, val, current_reg_content) \ + out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \ + ((uint32)((val) & (mask)))) ) + +#endif diff --git a/hw/kiwi/v2/beryllium_top_reg.h b/hw/kiwi/v2/beryllium_top_reg.h new file mode 100644 index 000000000000..31ff184148e6 --- /dev/null +++ b/hw/kiwi/v2/beryllium_top_reg.h @@ -0,0 +1,27 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef BERYLLIUM_TOP_REG_H +#define BERYLLIUM_TOP_REG_H + +#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0 (0x01B9804C) +#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1 (0x01B98050) + +#endif diff --git a/hw/kiwi/v2/buffer_addr_info.h b/hw/kiwi/v2/buffer_addr_info.h new file mode 100644 index 000000000000..468a6432798a --- /dev/null +++ b/hw/kiwi/v2/buffer_addr_info.h @@ -0,0 +1,63 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _BUFFER_ADDR_INFO_H_ +#define _BUFFER_ADDR_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 + +struct buffer_addr_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_addr_31_0 : 32; + uint32_t buffer_addr_39_32 : 8, + return_buffer_manager : 4, + sw_buffer_cookie : 20; +#else + uint32_t buffer_addr_31_0 : 32; + uint32_t sw_buffer_cookie : 20, + return_buffer_manager : 4, + buffer_addr_39_32 : 8; +#endif +}; + +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#endif diff --git a/hw/kiwi/v2/ce_src_desc.h b/hw/kiwi/v2/ce_src_desc.h new file mode 100644 index 000000000000..073a53ddd244 --- /dev/null +++ b/hw/kiwi/v2/ce_src_desc.h @@ -0,0 +1,140 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _CE_SRC_DESC_H_ +#define _CE_SRC_DESC_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_CE_SRC_DESC 4 + +struct ce_src_desc { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t src_buffer_low : 32; + uint32_t src_buffer_high : 8, + toeplitz_en : 1, + src_swap : 1, + dest_swap : 1, + gather : 1, + ce_res_0 : 1, + barrier_read : 1, + ce_res_1 : 2, + length : 16; + uint32_t fw_metadata : 16, + ce_res_2 : 16; + uint32_t ce_res_3 : 20, + ring_id : 8, + looping_count : 4; +#else + uint32_t src_buffer_low : 32; + uint32_t length : 16, + ce_res_1 : 2, + barrier_read : 1, + ce_res_0 : 1, + gather : 1, + dest_swap : 1, + src_swap : 1, + toeplitz_en : 1, + src_buffer_high : 8; + uint32_t ce_res_2 : 16, + fw_metadata : 16; + uint32_t looping_count : 4, + ring_id : 8, + ce_res_3 : 20; +#endif +}; + +#define CE_SRC_DESC_SRC_BUFFER_LOW_OFFSET 0x00000000 +#define CE_SRC_DESC_SRC_BUFFER_LOW_LSB 0 +#define CE_SRC_DESC_SRC_BUFFER_LOW_MSB 31 +#define CE_SRC_DESC_SRC_BUFFER_LOW_MASK 0xffffffff + +#define CE_SRC_DESC_SRC_BUFFER_HIGH_OFFSET 0x00000004 +#define CE_SRC_DESC_SRC_BUFFER_HIGH_LSB 0 +#define CE_SRC_DESC_SRC_BUFFER_HIGH_MSB 7 +#define CE_SRC_DESC_SRC_BUFFER_HIGH_MASK 0x000000ff + +#define CE_SRC_DESC_TOEPLITZ_EN_OFFSET 0x00000004 +#define CE_SRC_DESC_TOEPLITZ_EN_LSB 8 +#define CE_SRC_DESC_TOEPLITZ_EN_MSB 8 +#define CE_SRC_DESC_TOEPLITZ_EN_MASK 0x00000100 + +#define CE_SRC_DESC_SRC_SWAP_OFFSET 0x00000004 +#define CE_SRC_DESC_SRC_SWAP_LSB 9 +#define CE_SRC_DESC_SRC_SWAP_MSB 9 +#define CE_SRC_DESC_SRC_SWAP_MASK 0x00000200 + +#define CE_SRC_DESC_DEST_SWAP_OFFSET 0x00000004 +#define CE_SRC_DESC_DEST_SWAP_LSB 10 +#define CE_SRC_DESC_DEST_SWAP_MSB 10 +#define CE_SRC_DESC_DEST_SWAP_MASK 0x00000400 + +#define CE_SRC_DESC_GATHER_OFFSET 0x00000004 +#define CE_SRC_DESC_GATHER_LSB 11 +#define CE_SRC_DESC_GATHER_MSB 11 +#define CE_SRC_DESC_GATHER_MASK 0x00000800 + +#define CE_SRC_DESC_CE_RES_0_OFFSET 0x00000004 +#define CE_SRC_DESC_CE_RES_0_LSB 12 +#define CE_SRC_DESC_CE_RES_0_MSB 12 +#define CE_SRC_DESC_CE_RES_0_MASK 0x00001000 + +#define CE_SRC_DESC_BARRIER_READ_OFFSET 0x00000004 +#define CE_SRC_DESC_BARRIER_READ_LSB 13 +#define CE_SRC_DESC_BARRIER_READ_MSB 13 +#define CE_SRC_DESC_BARRIER_READ_MASK 0x00002000 + +#define CE_SRC_DESC_CE_RES_1_OFFSET 0x00000004 +#define CE_SRC_DESC_CE_RES_1_LSB 14 +#define CE_SRC_DESC_CE_RES_1_MSB 15 +#define CE_SRC_DESC_CE_RES_1_MASK 0x0000c000 + +#define CE_SRC_DESC_LENGTH_OFFSET 0x00000004 +#define CE_SRC_DESC_LENGTH_LSB 16 +#define CE_SRC_DESC_LENGTH_MSB 31 +#define CE_SRC_DESC_LENGTH_MASK 0xffff0000 + +#define CE_SRC_DESC_FW_METADATA_OFFSET 0x00000008 +#define CE_SRC_DESC_FW_METADATA_LSB 0 +#define CE_SRC_DESC_FW_METADATA_MSB 15 +#define CE_SRC_DESC_FW_METADATA_MASK 0x0000ffff + +#define CE_SRC_DESC_CE_RES_2_OFFSET 0x00000008 +#define CE_SRC_DESC_CE_RES_2_LSB 16 +#define CE_SRC_DESC_CE_RES_2_MSB 31 +#define CE_SRC_DESC_CE_RES_2_MASK 0xffff0000 + +#define CE_SRC_DESC_CE_RES_3_OFFSET 0x0000000c +#define CE_SRC_DESC_CE_RES_3_LSB 0 +#define CE_SRC_DESC_CE_RES_3_MSB 19 +#define CE_SRC_DESC_CE_RES_3_MASK 0x000fffff + +#define CE_SRC_DESC_RING_ID_OFFSET 0x0000000c +#define CE_SRC_DESC_RING_ID_LSB 20 +#define CE_SRC_DESC_RING_ID_MSB 27 +#define CE_SRC_DESC_RING_ID_MASK 0x0ff00000 + +#define CE_SRC_DESC_LOOPING_COUNT_OFFSET 0x0000000c +#define CE_SRC_DESC_LOOPING_COUNT_LSB 28 +#define CE_SRC_DESC_LOOPING_COUNT_MSB 31 +#define CE_SRC_DESC_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/kiwi/v2/ce_stat_desc.h b/hw/kiwi/v2/ce_stat_desc.h new file mode 100644 index 000000000000..d5cf68da54a6 --- /dev/null +++ b/hw/kiwi/v2/ce_stat_desc.h @@ -0,0 +1,133 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _CE_STAT_DESC_H_ +#define _CE_STAT_DESC_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_CE_STAT_DESC 4 + +struct ce_stat_desc { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ce_res_5 : 8, + toeplitz_en : 1, + src_swap : 1, + dest_swap : 1, + gather : 1, + barrier_read : 1, + ce_res_6 : 3, + length : 16; + uint32_t toeplitz_hash_0 : 32; + uint32_t toeplitz_hash_1 : 32; + uint32_t fw_metadata : 16, + ce_res_7 : 4, + ring_id : 8, + looping_count : 4; +#else + uint32_t length : 16, + ce_res_6 : 3, + barrier_read : 1, + gather : 1, + dest_swap : 1, + src_swap : 1, + toeplitz_en : 1, + ce_res_5 : 8; + uint32_t toeplitz_hash_0 : 32; + uint32_t toeplitz_hash_1 : 32; + uint32_t looping_count : 4, + ring_id : 8, + ce_res_7 : 4, + fw_metadata : 16; +#endif +}; + +#define CE_STAT_DESC_CE_RES_5_OFFSET 0x00000000 +#define CE_STAT_DESC_CE_RES_5_LSB 0 +#define CE_STAT_DESC_CE_RES_5_MSB 7 +#define CE_STAT_DESC_CE_RES_5_MASK 0x000000ff + +#define CE_STAT_DESC_TOEPLITZ_EN_OFFSET 0x00000000 +#define CE_STAT_DESC_TOEPLITZ_EN_LSB 8 +#define CE_STAT_DESC_TOEPLITZ_EN_MSB 8 +#define CE_STAT_DESC_TOEPLITZ_EN_MASK 0x00000100 + +#define CE_STAT_DESC_SRC_SWAP_OFFSET 0x00000000 +#define CE_STAT_DESC_SRC_SWAP_LSB 9 +#define CE_STAT_DESC_SRC_SWAP_MSB 9 +#define CE_STAT_DESC_SRC_SWAP_MASK 0x00000200 + +#define CE_STAT_DESC_DEST_SWAP_OFFSET 0x00000000 +#define CE_STAT_DESC_DEST_SWAP_LSB 10 +#define CE_STAT_DESC_DEST_SWAP_MSB 10 +#define CE_STAT_DESC_DEST_SWAP_MASK 0x00000400 + +#define CE_STAT_DESC_GATHER_OFFSET 0x00000000 +#define CE_STAT_DESC_GATHER_LSB 11 +#define CE_STAT_DESC_GATHER_MSB 11 +#define CE_STAT_DESC_GATHER_MASK 0x00000800 + +#define CE_STAT_DESC_BARRIER_READ_OFFSET 0x00000000 +#define CE_STAT_DESC_BARRIER_READ_LSB 12 +#define CE_STAT_DESC_BARRIER_READ_MSB 12 +#define CE_STAT_DESC_BARRIER_READ_MASK 0x00001000 + +#define CE_STAT_DESC_CE_RES_6_OFFSET 0x00000000 +#define CE_STAT_DESC_CE_RES_6_LSB 13 +#define CE_STAT_DESC_CE_RES_6_MSB 15 +#define CE_STAT_DESC_CE_RES_6_MASK 0x0000e000 + +#define CE_STAT_DESC_LENGTH_OFFSET 0x00000000 +#define CE_STAT_DESC_LENGTH_LSB 16 +#define CE_STAT_DESC_LENGTH_MSB 31 +#define CE_STAT_DESC_LENGTH_MASK 0xffff0000 + +#define CE_STAT_DESC_TOEPLITZ_HASH_0_OFFSET 0x00000004 +#define CE_STAT_DESC_TOEPLITZ_HASH_0_LSB 0 +#define CE_STAT_DESC_TOEPLITZ_HASH_0_MSB 31 +#define CE_STAT_DESC_TOEPLITZ_HASH_0_MASK 0xffffffff + +#define CE_STAT_DESC_TOEPLITZ_HASH_1_OFFSET 0x00000008 +#define CE_STAT_DESC_TOEPLITZ_HASH_1_LSB 0 +#define CE_STAT_DESC_TOEPLITZ_HASH_1_MSB 31 +#define CE_STAT_DESC_TOEPLITZ_HASH_1_MASK 0xffffffff + +#define CE_STAT_DESC_FW_METADATA_OFFSET 0x0000000c +#define CE_STAT_DESC_FW_METADATA_LSB 0 +#define CE_STAT_DESC_FW_METADATA_MSB 15 +#define CE_STAT_DESC_FW_METADATA_MASK 0x0000ffff + +#define CE_STAT_DESC_CE_RES_7_OFFSET 0x0000000c +#define CE_STAT_DESC_CE_RES_7_LSB 16 +#define CE_STAT_DESC_CE_RES_7_MSB 19 +#define CE_STAT_DESC_CE_RES_7_MASK 0x000f0000 + +#define CE_STAT_DESC_RING_ID_OFFSET 0x0000000c +#define CE_STAT_DESC_RING_ID_LSB 20 +#define CE_STAT_DESC_RING_ID_MSB 27 +#define CE_STAT_DESC_RING_ID_MASK 0x0ff00000 + +#define CE_STAT_DESC_LOOPING_COUNT_OFFSET 0x0000000c +#define CE_STAT_DESC_LOOPING_COUNT_LSB 28 +#define CE_STAT_DESC_LOOPING_COUNT_MSB 31 +#define CE_STAT_DESC_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/kiwi/v2/com_dtypes.h b/hw/kiwi/v2/com_dtypes.h new file mode 100644 index 000000000000..3fa2997e1d6d --- /dev/null +++ b/hw/kiwi/v2/com_dtypes.h @@ -0,0 +1,182 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef COM_DTYPES_H +#define COM_DTYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef T_WINNT + #ifndef WIN32 + #define WIN32 + #endif + #include +#endif + +#ifdef TRUE +#undef TRUE +#endif + +#ifdef FALSE +#undef FALSE +#endif + +#define TRUE 1 +#define FALSE 0 + +#define ON 1 +#define OFF 0 + +#ifndef NULL + #define NULL 0 +#endif + +#ifndef _ARM_ASM_ +#ifndef _BOOLEAN_DEFINED + +typedef unsigned char boolean; +#define _BOOLEAN_DEFINED +#endif + +#if defined(DALSTDDEF_H) +#define _BOOLEAN_DEFINED +#define _UINT32_DEFINED +#define _UINT16_DEFINED +#define _UINT8_DEFINED +#define _INT32_DEFINED +#define _INT16_DEFINED +#define _INT8_DEFINED +#define _UINT64_DEFINED +#define _INT64_DEFINED +#define _BYTE_DEFINED +#endif + +#ifndef _UINT32_DEFINED + +typedef unsigned long int uint32; +#define _UINT32_DEFINED +#endif + +#ifndef _UINT16_DEFINED + +typedef unsigned short uint16; +#define _UINT16_DEFINED +#endif + +#ifndef _UINT8_DEFINED + +typedef unsigned char uint8; +#define _UINT8_DEFINED +#endif + +#ifndef _INT32_DEFINED + +typedef signed long int int32; +#define _INT32_DEFINED +#endif + +#ifndef _INT16_DEFINED + +typedef signed short int16; +#define _INT16_DEFINED +#endif + +#ifndef _INT8_DEFINED + +typedef signed char int8; +#define _INT8_DEFINED +#endif + +#ifndef _BYTE_DEFINED + +typedef unsigned char byte; +#define _BYTE_DEFINED +#endif + +typedef unsigned short word; + +typedef unsigned long dword; + +typedef unsigned char uint1; + +typedef unsigned short uint2; + +typedef unsigned long uint4; + +typedef signed char int1; + +typedef signed short int2; + +typedef long int int4; + +typedef signed long sint31; + +typedef signed short sint15; + +typedef signed char sint7; + +typedef uint16 UWord16 ; +typedef uint32 UWord32 ; +typedef int32 Word32 ; +typedef int16 Word16 ; +typedef uint8 UWord8 ; +typedef int8 Word8 ; +typedef int32 Vect32 ; + +#if (! defined T_WINNT) && (! defined __GNUC__) + + #ifndef _INT64_DEFINED + + typedef long long int64; + #define _INT64_DEFINED + #endif + #ifndef _UINT64_DEFINED + + typedef unsigned long long uint64; + #define _UINT64_DEFINED + #endif +#else + + #if (defined __GNUC__) + #ifndef _INT64_DEFINED + typedef long long int64; + #define _INT64_DEFINED + #endif + #ifndef _UINT64_DEFINED + typedef unsigned long long uint64; + #define _UINT64_DEFINED + #endif + #else + typedef __int64 int64; + #ifndef _UINT64_DEFINED + typedef unsigned __int64 uint64; + #define _UINT64_DEFINED + #endif + #endif +#endif + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hw/kiwi/v2/he_sig_a_mu_dl_info.h b/hw/kiwi/v2/he_sig_a_mu_dl_info.h new file mode 100644 index 000000000000..9bce1fdd5841 --- /dev/null +++ b/hw/kiwi/v2/he_sig_a_mu_dl_info.h @@ -0,0 +1,189 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HE_SIG_A_MU_DL_INFO_H_ +#define _HE_SIG_A_MU_DL_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2 + +struct he_sig_a_mu_dl_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t dl_ul_flag : 1, + mcs_of_sig_b : 3, + dcm_of_sig_b : 1, + bss_color_id : 6, + spatial_reuse : 4, + transmit_bw : 3, + num_sig_b_symbols : 4, + comp_mode_sig_b : 1, + cp_ltf_size : 2, + doppler_indication : 1, + reserved_0a : 6; + uint32_t txop_duration : 7, + reserved_1a : 1, + num_ltf_symbols : 3, + ldpc_extra_symbol : 1, + stbc : 1, + packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + crc : 4, + tail : 6, + reserved_1b : 5, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0a : 6, + doppler_indication : 1, + cp_ltf_size : 2, + comp_mode_sig_b : 1, + num_sig_b_symbols : 4, + transmit_bw : 3, + spatial_reuse : 4, + bss_color_id : 6, + dcm_of_sig_b : 1, + mcs_of_sig_b : 3, + dl_ul_flag : 1; + uint32_t rx_integrity_check_passed : 1, + reserved_1b : 5, + tail : 6, + crc : 4, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2, + stbc : 1, + ldpc_extra_symbol : 1, + num_ltf_symbols : 3, + reserved_1a : 1, + txop_duration : 7; +#endif +}; + +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_LSB 0 +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MSB 0 +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MASK 0x00000001 + +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_LSB 1 +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MSB 3 +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MASK 0x0000000e + +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_LSB 4 +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MSB 4 +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MASK 0x00000010 + +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_LSB 5 +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MSB 10 +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MASK 0x000007e0 + +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_LSB 11 +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MSB 14 +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MASK 0x00007800 + +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_LSB 15 +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MSB 17 +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MASK 0x00038000 + +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_LSB 18 +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MSB 21 +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 + +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_LSB 22 +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MSB 22 +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MASK 0x00400000 + +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_LSB 23 +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MSB 24 +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MASK 0x01800000 + +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_LSB 25 +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MSB 25 +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MASK 0x02000000 + +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_LSB 26 +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MSB 31 +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MASK 0xfc000000 + +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_LSB 0 +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MSB 6 +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MASK 0x0000007f + +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_LSB 7 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MSB 7 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MASK 0x00000080 + +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_LSB 8 +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MSB 10 +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MASK 0x00000700 + +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_LSB 11 +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MSB 11 +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000800 + +#define HE_SIG_A_MU_DL_INFO_STBC_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_STBC_LSB 12 +#define HE_SIG_A_MU_DL_INFO_STBC_MSB 12 +#define HE_SIG_A_MU_DL_INFO_STBC_MASK 0x00001000 + +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_LSB 13 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MSB 14 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 + +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 + +#define HE_SIG_A_MU_DL_INFO_CRC_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_CRC_LSB 16 +#define HE_SIG_A_MU_DL_INFO_CRC_MSB 19 +#define HE_SIG_A_MU_DL_INFO_CRC_MASK 0x000f0000 + +#define HE_SIG_A_MU_DL_INFO_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_TAIL_LSB 20 +#define HE_SIG_A_MU_DL_INFO_TAIL_MSB 25 +#define HE_SIG_A_MU_DL_INFO_TAIL_MASK 0x03f00000 + +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_LSB 26 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MSB 30 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MASK 0x7c000000 + +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/kiwi/v2/he_sig_a_mu_ul_info.h b/hw/kiwi/v2/he_sig_a_mu_ul_info.h new file mode 100644 index 000000000000..c4d70bd42188 --- /dev/null +++ b/hw/kiwi/v2/he_sig_a_mu_ul_info.h @@ -0,0 +1,119 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HE_SIG_A_MU_UL_INFO_H_ +#define _HE_SIG_A_MU_UL_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2 + +struct he_sig_a_mu_ul_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t format_indication : 1, + bss_color_id : 6, + spatial_reuse : 16, + reserved_0a : 1, + transmit_bw : 2, + reserved_0b : 6; + uint32_t txop_duration : 7, + reserved_1a : 9, + crc : 4, + tail : 6, + reserved_1b : 5, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0b : 6, + transmit_bw : 2, + reserved_0a : 1, + spatial_reuse : 16, + bss_color_id : 6, + format_indication : 1; + uint32_t rx_integrity_check_passed : 1, + reserved_1b : 5, + tail : 6, + crc : 4, + reserved_1a : 9, + txop_duration : 7; +#endif +}; + +#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB 0 +#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB 0 +#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK 0x00000001 + +#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB 1 +#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB 6 +#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK 0x0000007e + +#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB 7 +#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB 22 +#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK 0x007fff80 + +#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB 23 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB 23 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK 0x00800000 + +#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB 24 +#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB 25 +#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK 0x03000000 + +#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB 26 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB 31 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK 0xfc000000 + +#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB 0 +#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB 6 +#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK 0x0000007f + +#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB 7 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB 15 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK 0x0000ff80 + +#define HE_SIG_A_MU_UL_INFO_CRC_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_CRC_LSB 16 +#define HE_SIG_A_MU_UL_INFO_CRC_MSB 19 +#define HE_SIG_A_MU_UL_INFO_CRC_MASK 0x000f0000 + +#define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_TAIL_LSB 20 +#define HE_SIG_A_MU_UL_INFO_TAIL_MSB 25 +#define HE_SIG_A_MU_UL_INFO_TAIL_MASK 0x03f00000 + +#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB 26 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB 30 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK 0x7c000000 + +#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/kiwi/v2/he_sig_a_su_info.h b/hw/kiwi/v2/he_sig_a_su_info.h new file mode 100644 index 000000000000..963b1c0559eb --- /dev/null +++ b/hw/kiwi/v2/he_sig_a_su_info.h @@ -0,0 +1,224 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HE_SIG_A_SU_INFO_H_ +#define _HE_SIG_A_SU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2 + +struct he_sig_a_su_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t format_indication : 1, + beam_change : 1, + dl_ul_flag : 1, + transmit_mcs : 4, + dcm : 1, + bss_color_id : 6, + reserved_0a : 1, + spatial_reuse : 4, + transmit_bw : 2, + cp_ltf_size : 2, + nsts : 3, + reserved_0b : 6; + uint32_t txop_duration : 7, + coding : 1, + ldpc_extra_symbol : 1, + stbc : 1, + txbf : 1, + packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + reserved_1a : 1, + doppler_indication : 1, + crc : 4, + tail : 6, + dot11ax_su_extended : 1, + dot11ax_ext_ru_size : 3, + rx_ndp : 1, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0b : 6, + nsts : 3, + cp_ltf_size : 2, + transmit_bw : 2, + spatial_reuse : 4, + reserved_0a : 1, + bss_color_id : 6, + dcm : 1, + transmit_mcs : 4, + dl_ul_flag : 1, + beam_change : 1, + format_indication : 1; + uint32_t rx_integrity_check_passed : 1, + rx_ndp : 1, + dot11ax_ext_ru_size : 3, + dot11ax_su_extended : 1, + tail : 6, + crc : 4, + doppler_indication : 1, + reserved_1a : 1, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2, + txbf : 1, + stbc : 1, + ldpc_extra_symbol : 1, + coding : 1, + txop_duration : 7; +#endif +}; + +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_LSB 0 +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MSB 0 +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MASK 0x00000001 + +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_LSB 1 +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MSB 1 +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MASK 0x00000002 + +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_LSB 2 +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MSB 2 +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MASK 0x00000004 + +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_LSB 3 +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MSB 6 +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MASK 0x00000078 + +#define HE_SIG_A_SU_INFO_DCM_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_DCM_LSB 7 +#define HE_SIG_A_SU_INFO_DCM_MSB 7 +#define HE_SIG_A_SU_INFO_DCM_MASK 0x00000080 + +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_LSB 8 +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MSB 13 +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MASK 0x00003f00 + +#define HE_SIG_A_SU_INFO_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_RESERVED_0A_LSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_0A_MSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_0A_MASK 0x00004000 + +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_LSB 15 +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MSB 18 +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MASK 0x00078000 + +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_LSB 19 +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MSB 20 +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MASK 0x00180000 + +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_LSB 21 +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MSB 22 +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MASK 0x00600000 + +#define HE_SIG_A_SU_INFO_NSTS_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_NSTS_LSB 23 +#define HE_SIG_A_SU_INFO_NSTS_MSB 25 +#define HE_SIG_A_SU_INFO_NSTS_MASK 0x03800000 + +#define HE_SIG_A_SU_INFO_RESERVED_0B_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_RESERVED_0B_LSB 26 +#define HE_SIG_A_SU_INFO_RESERVED_0B_MSB 31 +#define HE_SIG_A_SU_INFO_RESERVED_0B_MASK 0xfc000000 + +#define HE_SIG_A_SU_INFO_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_TXOP_DURATION_LSB 0 +#define HE_SIG_A_SU_INFO_TXOP_DURATION_MSB 6 +#define HE_SIG_A_SU_INFO_TXOP_DURATION_MASK 0x0000007f + +#define HE_SIG_A_SU_INFO_CODING_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_CODING_LSB 7 +#define HE_SIG_A_SU_INFO_CODING_MSB 7 +#define HE_SIG_A_SU_INFO_CODING_MASK 0x00000080 + +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_LSB 8 +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MSB 8 +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000100 + +#define HE_SIG_A_SU_INFO_STBC_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_STBC_LSB 9 +#define HE_SIG_A_SU_INFO_STBC_MSB 9 +#define HE_SIG_A_SU_INFO_STBC_MASK 0x00000200 + +#define HE_SIG_A_SU_INFO_TXBF_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_TXBF_LSB 10 +#define HE_SIG_A_SU_INFO_TXBF_MSB 10 +#define HE_SIG_A_SU_INFO_TXBF_MASK 0x00000400 + +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_LSB 11 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MSB 12 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800 + +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000 + +#define HE_SIG_A_SU_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_RESERVED_1A_LSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_1A_MSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_1A_MASK 0x00004000 + +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_LSB 15 +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MSB 15 +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MASK 0x00008000 + +#define HE_SIG_A_SU_INFO_CRC_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_CRC_LSB 16 +#define HE_SIG_A_SU_INFO_CRC_MSB 19 +#define HE_SIG_A_SU_INFO_CRC_MASK 0x000f0000 + +#define HE_SIG_A_SU_INFO_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_TAIL_LSB 20 +#define HE_SIG_A_SU_INFO_TAIL_MSB 25 +#define HE_SIG_A_SU_INFO_TAIL_MASK 0x03f00000 + +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_LSB 26 +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MSB 26 +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 + +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_LSB 27 +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MSB 29 +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x38000000 + +#define HE_SIG_A_SU_INFO_RX_NDP_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_RX_NDP_LSB 30 +#define HE_SIG_A_SU_INFO_RX_NDP_MSB 30 +#define HE_SIG_A_SU_INFO_RX_NDP_MASK 0x40000000 + +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/kiwi/v2/he_sig_b1_mu_info.h b/hw/kiwi/v2/he_sig_b1_mu_info.h new file mode 100644 index 000000000000..86d89e4c049d --- /dev/null +++ b/hw/kiwi/v2/he_sig_b1_mu_info.h @@ -0,0 +1,56 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HE_SIG_B1_MU_INFO_H_ +#define _HE_SIG_B1_MU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1 + +struct he_sig_b1_mu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ru_allocation : 8, + reserved_0 : 23, + rx_integrity_check_passed : 1; +#else + uint32_t rx_integrity_check_passed : 1, + reserved_0 : 23, + ru_allocation : 8; +#endif +}; + +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_LSB 0 +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MSB 7 +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MASK 0x000000ff + +#define HE_SIG_B1_MU_INFO_RESERVED_0_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_RESERVED_0_LSB 8 +#define HE_SIG_B1_MU_INFO_RESERVED_0_MSB 30 +#define HE_SIG_B1_MU_INFO_RESERVED_0_MASK 0x7fffff00 + +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/kiwi/v2/he_sig_b2_mu_info.h b/hw/kiwi/v2/he_sig_b2_mu_info.h new file mode 100644 index 000000000000..9eba8de68973 --- /dev/null +++ b/hw/kiwi/v2/he_sig_b2_mu_info.h @@ -0,0 +1,112 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HE_SIG_B2_MU_INFO_H_ +#define _HE_SIG_B2_MU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 2 + +struct he_sig_b2_mu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + sta_spatial_config : 4, + sta_mcs : 4, + reserved_set_to_1 : 1, + sta_coding : 1, + reserved_0a : 7, + nsts : 3, + rx_integrity_check_passed : 1; + uint32_t user_order : 8, + cc_mask : 8, + reserved_1a : 16; +#else + uint32_t rx_integrity_check_passed : 1, + nsts : 3, + reserved_0a : 7, + sta_coding : 1, + reserved_set_to_1 : 1, + sta_mcs : 4, + sta_spatial_config : 4, + sta_id : 11; + uint32_t reserved_1a : 16, + cc_mask : 8, + user_order : 8; +#endif +}; + +#define HE_SIG_B2_MU_INFO_STA_ID_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_ID_LSB 0 +#define HE_SIG_B2_MU_INFO_STA_ID_MSB 10 +#define HE_SIG_B2_MU_INFO_STA_ID_MASK 0x000007ff + +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_LSB 11 +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MSB 14 +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MASK 0x00007800 + +#define HE_SIG_B2_MU_INFO_STA_MCS_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_MCS_LSB 15 +#define HE_SIG_B2_MU_INFO_STA_MCS_MSB 18 +#define HE_SIG_B2_MU_INFO_STA_MCS_MASK 0x00078000 + +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_LSB 19 +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MSB 19 +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MASK 0x00080000 + +#define HE_SIG_B2_MU_INFO_STA_CODING_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_CODING_LSB 20 +#define HE_SIG_B2_MU_INFO_STA_CODING_MSB 20 +#define HE_SIG_B2_MU_INFO_STA_CODING_MASK 0x00100000 + +#define HE_SIG_B2_MU_INFO_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_RESERVED_0A_LSB 21 +#define HE_SIG_B2_MU_INFO_RESERVED_0A_MSB 27 +#define HE_SIG_B2_MU_INFO_RESERVED_0A_MASK 0x0fe00000 + +#define HE_SIG_B2_MU_INFO_NSTS_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_NSTS_LSB 28 +#define HE_SIG_B2_MU_INFO_NSTS_MSB 30 +#define HE_SIG_B2_MU_INFO_NSTS_MASK 0x70000000 + +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#define HE_SIG_B2_MU_INFO_USER_ORDER_OFFSET 0x00000004 +#define HE_SIG_B2_MU_INFO_USER_ORDER_LSB 0 +#define HE_SIG_B2_MU_INFO_USER_ORDER_MSB 7 +#define HE_SIG_B2_MU_INFO_USER_ORDER_MASK 0x000000ff + +#define HE_SIG_B2_MU_INFO_CC_MASK_OFFSET 0x00000004 +#define HE_SIG_B2_MU_INFO_CC_MASK_LSB 8 +#define HE_SIG_B2_MU_INFO_CC_MASK_MSB 15 +#define HE_SIG_B2_MU_INFO_CC_MASK_MASK 0x0000ff00 + +#define HE_SIG_B2_MU_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_B2_MU_INFO_RESERVED_1A_LSB 16 +#define HE_SIG_B2_MU_INFO_RESERVED_1A_MSB 31 +#define HE_SIG_B2_MU_INFO_RESERVED_1A_MASK 0xffff0000 + +#endif diff --git a/hw/kiwi/v2/he_sig_b2_ofdma_info.h b/hw/kiwi/v2/he_sig_b2_ofdma_info.h new file mode 100644 index 000000000000..0bcbe5592f69 --- /dev/null +++ b/hw/kiwi/v2/he_sig_b2_ofdma_info.h @@ -0,0 +1,112 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HE_SIG_B2_OFDMA_INFO_H_ +#define _HE_SIG_B2_OFDMA_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 2 + +struct he_sig_b2_ofdma_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + nsts : 3, + txbf : 1, + sta_mcs : 4, + sta_dcm : 1, + sta_coding : 1, + reserved_0 : 10, + rx_integrity_check_passed : 1; + uint32_t user_order : 8, + cc_mask : 8, + reserved_1a : 16; +#else + uint32_t rx_integrity_check_passed : 1, + reserved_0 : 10, + sta_coding : 1, + sta_dcm : 1, + sta_mcs : 4, + txbf : 1, + nsts : 3, + sta_id : 11; + uint32_t reserved_1a : 16, + cc_mask : 8, + user_order : 8; +#endif +}; + +#define HE_SIG_B2_OFDMA_INFO_STA_ID_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_ID_LSB 0 +#define HE_SIG_B2_OFDMA_INFO_STA_ID_MSB 10 +#define HE_SIG_B2_OFDMA_INFO_STA_ID_MASK 0x000007ff + +#define HE_SIG_B2_OFDMA_INFO_NSTS_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_NSTS_LSB 11 +#define HE_SIG_B2_OFDMA_INFO_NSTS_MSB 13 +#define HE_SIG_B2_OFDMA_INFO_NSTS_MASK 0x00003800 + +#define HE_SIG_B2_OFDMA_INFO_TXBF_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_TXBF_LSB 14 +#define HE_SIG_B2_OFDMA_INFO_TXBF_MSB 14 +#define HE_SIG_B2_OFDMA_INFO_TXBF_MASK 0x00004000 + +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_LSB 15 +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MSB 18 +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MASK 0x00078000 + +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_LSB 19 +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MSB 19 +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MASK 0x00080000 + +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_LSB 20 +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MSB 20 +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MASK 0x00100000 + +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_LSB 21 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MSB 30 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MASK 0x7fe00000 + +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_OFFSET 0x00000004 +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_LSB 0 +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MSB 7 +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MASK 0x000000ff + +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_OFFSET 0x00000004 +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_LSB 8 +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MSB 15 +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MASK 0x0000ff00 + +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_LSB 16 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MSB 31 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MASK 0xffff0000 + +#endif diff --git a/hw/kiwi/v2/ht_sig_info.h b/hw/kiwi/v2/ht_sig_info.h new file mode 100644 index 000000000000..298d79e870be --- /dev/null +++ b/hw/kiwi/v2/ht_sig_info.h @@ -0,0 +1,147 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HT_SIG_INFO_H_ +#define _HT_SIG_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HT_SIG_INFO 2 + +struct ht_sig_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mcs : 7, + cbw : 1, + length : 16, + reserved_0 : 8; + uint32_t smoothing : 1, + not_sounding : 1, + ht_reserved : 1, + aggregation : 1, + stbc : 2, + fec_coding : 1, + short_gi : 1, + num_ext_sp_str : 2, + crc : 8, + signal_tail : 6, + reserved_1 : 7, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0 : 8, + length : 16, + cbw : 1, + mcs : 7; + uint32_t rx_integrity_check_passed : 1, + reserved_1 : 7, + signal_tail : 6, + crc : 8, + num_ext_sp_str : 2, + short_gi : 1, + fec_coding : 1, + stbc : 2, + aggregation : 1, + ht_reserved : 1, + not_sounding : 1, + smoothing : 1; +#endif +}; + +#define HT_SIG_INFO_MCS_OFFSET 0x00000000 +#define HT_SIG_INFO_MCS_LSB 0 +#define HT_SIG_INFO_MCS_MSB 6 +#define HT_SIG_INFO_MCS_MASK 0x0000007f + +#define HT_SIG_INFO_CBW_OFFSET 0x00000000 +#define HT_SIG_INFO_CBW_LSB 7 +#define HT_SIG_INFO_CBW_MSB 7 +#define HT_SIG_INFO_CBW_MASK 0x00000080 + +#define HT_SIG_INFO_LENGTH_OFFSET 0x00000000 +#define HT_SIG_INFO_LENGTH_LSB 8 +#define HT_SIG_INFO_LENGTH_MSB 23 +#define HT_SIG_INFO_LENGTH_MASK 0x00ffff00 + +#define HT_SIG_INFO_RESERVED_0_OFFSET 0x00000000 +#define HT_SIG_INFO_RESERVED_0_LSB 24 +#define HT_SIG_INFO_RESERVED_0_MSB 31 +#define HT_SIG_INFO_RESERVED_0_MASK 0xff000000 + +#define HT_SIG_INFO_SMOOTHING_OFFSET 0x00000004 +#define HT_SIG_INFO_SMOOTHING_LSB 0 +#define HT_SIG_INFO_SMOOTHING_MSB 0 +#define HT_SIG_INFO_SMOOTHING_MASK 0x00000001 + +#define HT_SIG_INFO_NOT_SOUNDING_OFFSET 0x00000004 +#define HT_SIG_INFO_NOT_SOUNDING_LSB 1 +#define HT_SIG_INFO_NOT_SOUNDING_MSB 1 +#define HT_SIG_INFO_NOT_SOUNDING_MASK 0x00000002 + +#define HT_SIG_INFO_HT_RESERVED_OFFSET 0x00000004 +#define HT_SIG_INFO_HT_RESERVED_LSB 2 +#define HT_SIG_INFO_HT_RESERVED_MSB 2 +#define HT_SIG_INFO_HT_RESERVED_MASK 0x00000004 + +#define HT_SIG_INFO_AGGREGATION_OFFSET 0x00000004 +#define HT_SIG_INFO_AGGREGATION_LSB 3 +#define HT_SIG_INFO_AGGREGATION_MSB 3 +#define HT_SIG_INFO_AGGREGATION_MASK 0x00000008 + +#define HT_SIG_INFO_STBC_OFFSET 0x00000004 +#define HT_SIG_INFO_STBC_LSB 4 +#define HT_SIG_INFO_STBC_MSB 5 +#define HT_SIG_INFO_STBC_MASK 0x00000030 + +#define HT_SIG_INFO_FEC_CODING_OFFSET 0x00000004 +#define HT_SIG_INFO_FEC_CODING_LSB 6 +#define HT_SIG_INFO_FEC_CODING_MSB 6 +#define HT_SIG_INFO_FEC_CODING_MASK 0x00000040 + +#define HT_SIG_INFO_SHORT_GI_OFFSET 0x00000004 +#define HT_SIG_INFO_SHORT_GI_LSB 7 +#define HT_SIG_INFO_SHORT_GI_MSB 7 +#define HT_SIG_INFO_SHORT_GI_MASK 0x00000080 + +#define HT_SIG_INFO_NUM_EXT_SP_STR_OFFSET 0x00000004 +#define HT_SIG_INFO_NUM_EXT_SP_STR_LSB 8 +#define HT_SIG_INFO_NUM_EXT_SP_STR_MSB 9 +#define HT_SIG_INFO_NUM_EXT_SP_STR_MASK 0x00000300 + +#define HT_SIG_INFO_CRC_OFFSET 0x00000004 +#define HT_SIG_INFO_CRC_LSB 10 +#define HT_SIG_INFO_CRC_MSB 17 +#define HT_SIG_INFO_CRC_MASK 0x0003fc00 + +#define HT_SIG_INFO_SIGNAL_TAIL_OFFSET 0x00000004 +#define HT_SIG_INFO_SIGNAL_TAIL_LSB 18 +#define HT_SIG_INFO_SIGNAL_TAIL_MSB 23 +#define HT_SIG_INFO_SIGNAL_TAIL_MASK 0x00fc0000 + +#define HT_SIG_INFO_RESERVED_1_OFFSET 0x00000004 +#define HT_SIG_INFO_RESERVED_1_LSB 24 +#define HT_SIG_INFO_RESERVED_1_MSB 30 +#define HT_SIG_INFO_RESERVED_1_MASK 0x7f000000 + +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/kiwi/v2/l_sig_a_info.h b/hw/kiwi/v2/l_sig_a_info.h new file mode 100644 index 000000000000..cb3ff29e39ff --- /dev/null +++ b/hw/kiwi/v2/l_sig_a_info.h @@ -0,0 +1,98 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _L_SIG_A_INFO_H_ +#define _L_SIG_A_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_L_SIG_A_INFO 1 + +struct l_sig_a_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rate : 4, + lsig_reserved : 1, + length : 12, + parity : 1, + tail : 6, + pkt_type : 4, + captured_implicit_sounding : 1, + reserved : 2, + rx_integrity_check_passed : 1; +#else + uint32_t rx_integrity_check_passed : 1, + reserved : 2, + captured_implicit_sounding : 1, + pkt_type : 4, + tail : 6, + parity : 1, + length : 12, + lsig_reserved : 1, + rate : 4; +#endif +}; + +#define L_SIG_A_INFO_RATE_OFFSET 0x00000000 +#define L_SIG_A_INFO_RATE_LSB 0 +#define L_SIG_A_INFO_RATE_MSB 3 +#define L_SIG_A_INFO_RATE_MASK 0x0000000f + +#define L_SIG_A_INFO_LSIG_RESERVED_OFFSET 0x00000000 +#define L_SIG_A_INFO_LSIG_RESERVED_LSB 4 +#define L_SIG_A_INFO_LSIG_RESERVED_MSB 4 +#define L_SIG_A_INFO_LSIG_RESERVED_MASK 0x00000010 + +#define L_SIG_A_INFO_LENGTH_OFFSET 0x00000000 +#define L_SIG_A_INFO_LENGTH_LSB 5 +#define L_SIG_A_INFO_LENGTH_MSB 16 +#define L_SIG_A_INFO_LENGTH_MASK 0x0001ffe0 + +#define L_SIG_A_INFO_PARITY_OFFSET 0x00000000 +#define L_SIG_A_INFO_PARITY_LSB 17 +#define L_SIG_A_INFO_PARITY_MSB 17 +#define L_SIG_A_INFO_PARITY_MASK 0x00020000 + +#define L_SIG_A_INFO_TAIL_OFFSET 0x00000000 +#define L_SIG_A_INFO_TAIL_LSB 18 +#define L_SIG_A_INFO_TAIL_MSB 23 +#define L_SIG_A_INFO_TAIL_MASK 0x00fc0000 + +#define L_SIG_A_INFO_PKT_TYPE_OFFSET 0x00000000 +#define L_SIG_A_INFO_PKT_TYPE_LSB 24 +#define L_SIG_A_INFO_PKT_TYPE_MSB 27 +#define L_SIG_A_INFO_PKT_TYPE_MASK 0x0f000000 + +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000 +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MSB 28 +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000 + +#define L_SIG_A_INFO_RESERVED_OFFSET 0x00000000 +#define L_SIG_A_INFO_RESERVED_LSB 29 +#define L_SIG_A_INFO_RESERVED_MSB 30 +#define L_SIG_A_INFO_RESERVED_MASK 0x60000000 + +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/kiwi/v2/l_sig_b_info.h b/hw/kiwi/v2/l_sig_b_info.h new file mode 100644 index 000000000000..9b79f1919243 --- /dev/null +++ b/hw/kiwi/v2/l_sig_b_info.h @@ -0,0 +1,63 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _L_SIG_B_INFO_H_ +#define _L_SIG_B_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_L_SIG_B_INFO 1 + +struct l_sig_b_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rate : 4, + length : 12, + reserved : 15, + rx_integrity_check_passed : 1; +#else + uint32_t rx_integrity_check_passed : 1, + reserved : 15, + length : 12, + rate : 4; +#endif +}; + +#define L_SIG_B_INFO_RATE_OFFSET 0x00000000 +#define L_SIG_B_INFO_RATE_LSB 0 +#define L_SIG_B_INFO_RATE_MSB 3 +#define L_SIG_B_INFO_RATE_MASK 0x0000000f + +#define L_SIG_B_INFO_LENGTH_OFFSET 0x00000000 +#define L_SIG_B_INFO_LENGTH_LSB 4 +#define L_SIG_B_INFO_LENGTH_MSB 15 +#define L_SIG_B_INFO_LENGTH_MASK 0x0000fff0 + +#define L_SIG_B_INFO_RESERVED_OFFSET 0x00000000 +#define L_SIG_B_INFO_RESERVED_LSB 16 +#define L_SIG_B_INFO_RESERVED_MSB 30 +#define L_SIG_B_INFO_RESERVED_MASK 0x7fff0000 + +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/kiwi/v2/macrx_abort_request_info.h b/hw/kiwi/v2/macrx_abort_request_info.h new file mode 100644 index 000000000000..cb9db8014060 --- /dev/null +++ b/hw/kiwi/v2/macrx_abort_request_info.h @@ -0,0 +1,49 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACRX_ABORT_REQUEST_INFO_H_ +#define _MACRX_ABORT_REQUEST_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1 + +struct macrx_abort_request_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t macrx_abort_reason : 8, + reserved_0 : 8; +#else + uint16_t reserved_0 : 8, + macrx_abort_reason : 8; +#endif +}; + +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_OFFSET 0x00000000 +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_LSB 0 +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MSB 7 +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MASK 0x000000ff + +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 8 +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000ff00 + +#endif diff --git a/hw/kiwi/v2/msmhwiobase.h b/hw/kiwi/v2/msmhwiobase.h new file mode 100644 index 000000000000..e05e60bcbe6a --- /dev/null +++ b/hw/kiwi/v2/msmhwiobase.h @@ -0,0 +1,191 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef __MSMHWIOBASE_H__ +#define __MSMHWIOBASE_H__ + +#define WCSS_WCSS_BASE 0x00000000 +#define WCSS_WCSS_BASE_SIZE 0x01000000 +#define WCSS_WCSS_BASE_PHYS 0x00000000 + +#define QDSS_STM_SIZE_BASE 0x00100000 +#define QDSS_STM_SIZE_BASE_SIZE 0x100000000 +#define QDSS_STM_SIZE_BASE_PHYS 0x00100000 + +#define BOOT_ROM_SIZE_BASE 0x00200000 +#define BOOT_ROM_SIZE_BASE_SIZE 0x100000000 +#define BOOT_ROM_SIZE_BASE_PHYS 0x00200000 + +#define SYSTEM_IRAM_SIZE_BASE 0x00400000 +#define SYSTEM_IRAM_SIZE_BASE_SIZE 0x100000000 +#define SYSTEM_IRAM_SIZE_BASE_PHYS 0x00400000 + +#define BOOT_ROM_START_ADDRESS_BASE 0x01200000 +#define BOOT_ROM_START_ADDRESS_BASE_SIZE 0x100000000 +#define BOOT_ROM_START_ADDRESS_BASE_PHYS 0x01200000 + +#define BOOT_ROM_END_ADDRESS_BASE 0x013fffff +#define BOOT_ROM_END_ADDRESS_BASE_SIZE 0x100000000 +#define BOOT_ROM_END_ADDRESS_BASE_PHYS 0x013fffff + +#define SYSTEM_IRAM_START_ADDRESS_BASE 0x01400000 +#define SYSTEM_IRAM_START_ADDRESS_BASE_SIZE 0x100000000 +#define SYSTEM_IRAM_START_ADDRESS_BASE_PHYS 0x01400000 + +#define SYSTEM_IRAM_END_ADDRESS_BASE 0x017fffff +#define SYSTEM_IRAM_END_ADDRESS_BASE_SIZE 0x100000000 +#define SYSTEM_IRAM_END_ADDRESS_BASE_PHYS 0x017fffff + +#define QDSS_STM_BASE 0x01800000 +#define QDSS_STM_BASE_SIZE 0x100000000 +#define QDSS_STM_BASE_PHYS 0x01800000 + +#define QDSS_STM_END_BASE 0x018fffff +#define QDSS_STM_END_BASE_SIZE 0x100000000 +#define QDSS_STM_END_BASE_PHYS 0x018fffff + +#define TLMM_BASE 0x01900000 +#define TLMM_BASE_SIZE 0x00200000 +#define TLMM_BASE_PHYS 0x01900000 + +#define CORE_TOP_CSR_BASE 0x01b00000 +#define CORE_TOP_CSR_BASE_SIZE 0x00040000 +#define CORE_TOP_CSR_BASE_PHYS 0x01b00000 + +#define BLSP1_BLSP_BASE 0x01b40000 +#define BLSP1_BLSP_BASE_SIZE 0x00040000 +#define BLSP1_BLSP_BASE_PHYS 0x01b40000 + +#define SOC_WFSS_CE_REG_BASE 0x01b80000 +#define SOC_WFSS_CE_REG_BASE_SIZE 0x0001c000 +#define SOC_WFSS_CE_REG_BASE_PHYS 0x01b80000 + +#define WL_TLMM_BASE 0x01bc0000 +#define WL_TLMM_BASE_SIZE 0x00020000 +#define WL_TLMM_BASE_PHYS 0x01bc0000 + +#define MEMSS_CSR_BASE 0x01be0000 +#define MEMSS_CSR_BASE_SIZE 0x0000001c +#define MEMSS_CSR_BASE_PHYS 0x01be0000 + +#define TSENS_SROT_BASE 0x01bf0000 +#define TSENS_SROT_BASE_SIZE 0x00001000 +#define TSENS_SROT_BASE_PHYS 0x01bf0000 + +#define TSENS_TM_BASE 0x01bf1000 +#define TSENS_TM_BASE_SIZE 0x00001000 +#define TSENS_TM_BASE_PHYS 0x01bf1000 + +#define QDSS_APB_DEC_QDSS_APB_BASE 0x01c00000 +#define QDSS_APB_DEC_QDSS_APB_BASE_SIZE 0x00080000 +#define QDSS_APB_DEC_QDSS_APB_BASE_PHYS 0x01c00000 + +#define QDSS_WRAPPER_TOP_BASE 0x01c80000 +#define QDSS_WRAPPER_TOP_BASE_SIZE 0x0007fffd +#define QDSS_WRAPPER_TOP_BASE_PHYS 0x01c80000 + +#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE 0x01d00000 +#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_SIZE 0x00100000 +#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_PHYS 0x01d00000 + +#define PCIE_PCIE_TOP_WRAPPER_BASE 0x01e00000 +#define PCIE_PCIE_TOP_WRAPPER_BASE_SIZE 0x00020000 +#define PCIE_PCIE_TOP_WRAPPER_BASE_PHYS 0x01e00000 + +#define SECURITY_CONTROL_WLAN_BASE 0x01e20000 +#define SECURITY_CONTROL_WLAN_BASE_SIZE 0x00008000 +#define SECURITY_CONTROL_WLAN_BASE_PHYS 0x01e20000 + +#define EDPD_CAL_ACC_BASE 0x01e28000 +#define EDPD_CAL_ACC_BASE_SIZE 0x00003000 +#define EDPD_CAL_ACC_BASE_PHYS 0x01e28000 + +#define CPR_CX_CPR3_BASE 0x01e30000 +#define CPR_CX_CPR3_BASE_SIZE 0x00004000 +#define CPR_CX_CPR3_BASE_PHYS 0x01e30000 + +#define CPR_MX_CPR3_BASE 0x01e34000 +#define CPR_MX_CPR3_BASE_SIZE 0x00004000 +#define CPR_MX_CPR3_BASE_PHYS 0x01e34000 + +#define GCC_GCC_BASE 0x01e40000 +#define GCC_GCC_BASE_SIZE 0x000003e8 +#define GCC_GCC_BASE_PHYS 0x01e40000 + +#define PRNG_PRNG_TOP_BASE 0x01e50000 +#define PRNG_PRNG_TOP_BASE_SIZE 0x00010000 +#define PRNG_PRNG_TOP_BASE_PHYS 0x01e50000 + +#define PCNOC_0_BUS_TIMEOUT_BASE 0x01e60000 +#define PCNOC_0_BUS_TIMEOUT_BASE_SIZE 0x00001000 +#define PCNOC_0_BUS_TIMEOUT_BASE_PHYS 0x01e60000 + +#define PCNOC_1_BUS_TIMEOUT_BASE 0x01e61000 +#define PCNOC_1_BUS_TIMEOUT_BASE_SIZE 0x00001000 +#define PCNOC_1_BUS_TIMEOUT_BASE_PHYS 0x01e61000 + +#define PCNOC_2_BUS_TIMEOUT_BASE 0x01e62000 +#define PCNOC_2_BUS_TIMEOUT_BASE_SIZE 0x00001000 +#define PCNOC_2_BUS_TIMEOUT_BASE_PHYS 0x01e62000 + +#define PCNOC_3_BUS_TIMEOUT_BASE 0x01e63000 +#define PCNOC_3_BUS_TIMEOUT_BASE_SIZE 0x00001000 +#define PCNOC_3_BUS_TIMEOUT_BASE_PHYS 0x01e63000 + +#define RRI_PREFETCH_REG_BASE 0x01e70000 +#define RRI_PREFETCH_REG_BASE_SIZE 0x00010000 +#define RRI_PREFETCH_REG_BASE_PHYS 0x01e70000 + +#define SYSTEM_NOC_BASE 0x01e80000 +#define SYSTEM_NOC_BASE_SIZE 0x0000a000 +#define SYSTEM_NOC_BASE_PHYS 0x01e80000 + +#define PC_NOC_BASE 0x01f00000 +#define PC_NOC_BASE_SIZE 0x00003880 +#define PC_NOC_BASE_PHYS 0x01f00000 + +#define WLAON_WL_AON_REG_BASE 0x01f80000 +#define WLAON_WL_AON_REG_BASE_SIZE 0x000007c8 +#define WLAON_WL_AON_REG_BASE_PHYS 0x01f80000 + +#define SYSPM_SYSPM_REG_BASE 0x01f82000 +#define SYSPM_SYSPM_REG_BASE_SIZE 0x00001000 +#define SYSPM_SYSPM_REG_BASE_PHYS 0x01f82000 + +#define PMU_WLAN_PMU_TOP_BASE 0x01f88000 +#define PMU_WLAN_PMU_TOP_BASE_SIZE 0x00000340 +#define PMU_WLAN_PMU_TOP_BASE_PHYS 0x01f88000 + +#define PMU_NOC_BASE 0x01f8a000 +#define PMU_NOC_BASE_SIZE 0x00000080 +#define PMU_NOC_BASE_PHYS 0x01f8a000 + +#define PCIE_ATU_REGION_BASE 0x04000000 +#define PCIE_ATU_REGION_BASE_SIZE 0x100000000 +#define PCIE_ATU_REGION_BASE_PHYS 0x04000000 + +#define PCIE_ATU_REGION_SIZE_BASE 0x40000000 +#define PCIE_ATU_REGION_SIZE_BASE_SIZE 0x100000000 +#define PCIE_ATU_REGION_SIZE_BASE_PHYS 0x40000000 + +#define PCIE_ATU_REGION_END_BASE 0x43ffffff +#define PCIE_ATU_REGION_END_BASE_SIZE 0x100000000 +#define PCIE_ATU_REGION_END_BASE_PHYS 0x43ffffff + +#endif diff --git a/hw/kiwi/v2/msmhwioreg.h b/hw/kiwi/v2/msmhwioreg.h new file mode 100644 index 000000000000..be689572652b --- /dev/null +++ b/hw/kiwi/v2/msmhwioreg.h @@ -0,0 +1,134 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef __MSMHWIOREG_H__ +#define __MSMHWIOREG_H__ + +#include "msmhwiobase.h" + +#define SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00001000) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000408) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL_SPARE_CONTROL_BMSK 0xfffffffc +#define HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL_SPARE_CONTROL_SHFT 0x2 +#define SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00003000) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000400) +#define SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00002000) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000058) + + +#endif diff --git a/hw/kiwi/v2/phyrx_abort_request_info.h b/hw/kiwi/v2/phyrx_abort_request_info.h new file mode 100644 index 000000000000..47b6059b5739 --- /dev/null +++ b/hw/kiwi/v2/phyrx_abort_request_info.h @@ -0,0 +1,70 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_ABORT_REQUEST_INFO_H_ +#define _PHYRX_ABORT_REQUEST_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1 + +struct phyrx_abort_request_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phyrx_abort_reason : 8, + phy_enters_nap_state : 1, + phy_enters_defer_state : 1, + reserved_0 : 6, + receive_duration : 16; +#else + uint32_t receive_duration : 16, + reserved_0 : 6, + phy_enters_defer_state : 1, + phy_enters_nap_state : 1, + phyrx_abort_reason : 8; +#endif +}; + +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_LSB 0 +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MSB 7 +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MASK 0x000000ff + +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_LSB 8 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MSB 8 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MASK 0x00000100 + +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_LSB 9 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MSB 9 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 + +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 10 +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000fc00 + +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_LSB 16 +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MSB 31 +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MASK 0xffff0000 + +#endif diff --git a/hw/kiwi/v2/phyrx_common_user_info.h b/hw/kiwi/v2/phyrx_common_user_info.h new file mode 100644 index 000000000000..9932384bdae0 --- /dev/null +++ b/hw/kiwi/v2/phyrx_common_user_info.h @@ -0,0 +1,170 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_COMMON_USER_INFO_H_ +#define _PHYRX_COMMON_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 4 + +#define NUM_OF_QWORDS_PHYRX_COMMON_USER_INFO 2 + +struct phyrx_common_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t receive_duration : 16, + reserved_0a : 16; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_1a : 26; + uint32_t eht_ppdu_type : 2, + bss_color_id : 6, + dl_ul_flag : 1, + txop_duration : 7, + cp_setting : 2, + ltf_size : 2, + spatial_reuse : 4, + rx_ndp : 1, + dot11be_su_extended : 1, + reserved_2a : 6; + uint32_t eht_duplicate : 2, + eht_sig_cmn_field_type : 2, + doppler_indication : 1, + sta_id : 11, + puncture_bitmap : 16; +#else + uint32_t reserved_0a : 16, + receive_duration : 16; + uint32_t reserved_1a : 26, + u_sig_puncture_pattern_encoding : 6; + uint32_t reserved_2a : 6, + dot11be_su_extended : 1, + rx_ndp : 1, + spatial_reuse : 4, + ltf_size : 2, + cp_setting : 2, + txop_duration : 7, + dl_ul_flag : 1, + bss_color_id : 6, + eht_ppdu_type : 2; + uint32_t puncture_bitmap : 16, + sta_id : 11, + doppler_indication : 1, + eht_sig_cmn_field_type : 2, + eht_duplicate : 2; +#endif +}; + +#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_OFFSET 0x0000000000000000 +#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_LSB 0 +#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MSB 15 +#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MASK 0x000000000000ffff + +#define PHYRX_COMMON_USER_INFO_RESERVED_0A_OFFSET 0x0000000000000000 +#define PHYRX_COMMON_USER_INFO_RESERVED_0A_LSB 16 +#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MSB 31 +#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MASK 0x00000000ffff0000 + +#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000000 +#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 32 +#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 37 +#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x0000003f00000000 + +#define PHYRX_COMMON_USER_INFO_RESERVED_1A_OFFSET 0x0000000000000000 +#define PHYRX_COMMON_USER_INFO_RESERVED_1A_LSB 38 +#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MSB 63 +#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MASK 0xffffffc000000000 + +#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_LSB 0 +#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_MSB 1 +#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_MASK 0x0000000000000003 + +#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_LSB 2 +#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MSB 7 +#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MASK 0x00000000000000fc + +#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_LSB 8 +#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MSB 8 +#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MASK 0x0000000000000100 + +#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_LSB 9 +#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MSB 15 +#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MASK 0x000000000000fe00 + +#define PHYRX_COMMON_USER_INFO_CP_SETTING_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_CP_SETTING_LSB 16 +#define PHYRX_COMMON_USER_INFO_CP_SETTING_MSB 17 +#define PHYRX_COMMON_USER_INFO_CP_SETTING_MASK 0x0000000000030000 + +#define PHYRX_COMMON_USER_INFO_LTF_SIZE_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_LTF_SIZE_LSB 18 +#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MSB 19 +#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MASK 0x00000000000c0000 + +#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_LSB 20 +#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MSB 23 +#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MASK 0x0000000000f00000 + +#define PHYRX_COMMON_USER_INFO_RX_NDP_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_RX_NDP_LSB 24 +#define PHYRX_COMMON_USER_INFO_RX_NDP_MSB 24 +#define PHYRX_COMMON_USER_INFO_RX_NDP_MASK 0x0000000001000000 + +#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_LSB 25 +#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_MSB 25 +#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_MASK 0x0000000002000000 + +#define PHYRX_COMMON_USER_INFO_RESERVED_2A_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_RESERVED_2A_LSB 26 +#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MSB 31 +#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MASK 0x00000000fc000000 + +#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_LSB 32 +#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MSB 33 +#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MASK 0x0000000300000000 + +#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_LSB 34 +#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_MSB 35 +#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_MASK 0x0000000c00000000 + +#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_LSB 36 +#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MSB 36 +#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MASK 0x0000001000000000 + +#define PHYRX_COMMON_USER_INFO_STA_ID_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_STA_ID_LSB 37 +#define PHYRX_COMMON_USER_INFO_STA_ID_MSB 47 +#define PHYRX_COMMON_USER_INFO_STA_ID_MASK 0x0000ffe000000000 + +#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_LSB 48 +#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MSB 63 +#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MASK 0xffff000000000000 + +#endif diff --git a/hw/kiwi/v2/phyrx_he_sig_a_mu_dl.h b/hw/kiwi/v2/phyrx_he_sig_a_mu_dl.h new file mode 100644 index 000000000000..3663ba18b82f --- /dev/null +++ b/hw/kiwi/v2/phyrx_he_sig_a_mu_dl.h @@ -0,0 +1,150 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HE_SIG_A_MU_DL_H_ +#define _PHYRX_HE_SIG_A_MU_DL_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_mu_dl_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2 + +#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_DL 1 + +struct phyrx_he_sig_a_mu_dl { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; +#else + struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; +#endif +}; + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + +#endif diff --git a/hw/kiwi/v2/phyrx_he_sig_a_mu_ul.h b/hw/kiwi/v2/phyrx_he_sig_a_mu_ul.h new file mode 100644 index 000000000000..eb2e99ee0df3 --- /dev/null +++ b/hw/kiwi/v2/phyrx_he_sig_a_mu_ul.h @@ -0,0 +1,100 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HE_SIG_A_MU_UL_H_ +#define _PHYRX_HE_SIG_A_MU_UL_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_mu_ul_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2 + +#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_UL 1 + +struct phyrx_he_sig_a_mu_ul { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; +#else + struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; +#endif +}; + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000000000000007e + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00000000007fff80 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000800000 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000003000000 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 32 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 38 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 39 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 47 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff8000000000 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 48 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 51 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f000000000000 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 52 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 57 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 58 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 62 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + +#endif diff --git a/hw/kiwi/v2/phyrx_he_sig_a_su.h b/hw/kiwi/v2/phyrx_he_sig_a_su.h new file mode 100644 index 000000000000..799744f63299 --- /dev/null +++ b/hw/kiwi/v2/phyrx_he_sig_a_su.h @@ -0,0 +1,175 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HE_SIG_A_SU_H_ +#define _PHYRX_HE_SIG_A_SU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_su_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2 + +#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_SU 1 + +struct phyrx_he_sig_a_su { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; +#else + struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; +#endif +}; + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + +#endif diff --git a/hw/kiwi/v2/phyrx_he_sig_b1_mu.h b/hw/kiwi/v2/phyrx_he_sig_b1_mu.h new file mode 100644 index 000000000000..017b823c6cf3 --- /dev/null +++ b/hw/kiwi/v2/phyrx_he_sig_b1_mu.h @@ -0,0 +1,62 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HE_SIG_B1_MU_H_ +#define _PHYRX_HE_SIG_B1_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b1_mu_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 2 + +#define NUM_OF_QWORDS_PHYRX_HE_SIG_B1_MU 1 + +struct phyrx_he_sig_b1_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; + uint32_t tlv64_padding : 32; +#else + struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; + uint32_t tlv64_padding : 32; +#endif +}; + +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff + +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00 + +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + +#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32 +#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63 +#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/phyrx_he_sig_b2_mu.h b/hw/kiwi/v2/phyrx_he_sig_b2_mu.h new file mode 100644 index 000000000000..35eaeffd8633 --- /dev/null +++ b/hw/kiwi/v2/phyrx_he_sig_b2_mu.h @@ -0,0 +1,95 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HE_SIG_B2_MU_H_ +#define _PHYRX_HE_SIG_B2_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b2_mu_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 2 + +#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_MU 1 + +struct phyrx_he_sig_b2_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; +#else + struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; +#endif +}; + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 40 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 47 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 48 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 + +#endif diff --git a/hw/kiwi/v2/phyrx_he_sig_b2_ofdma.h b/hw/kiwi/v2/phyrx_he_sig_b2_ofdma.h new file mode 100644 index 000000000000..cd517deed774 --- /dev/null +++ b/hw/kiwi/v2/phyrx_he_sig_b2_ofdma.h @@ -0,0 +1,95 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_ +#define _PHYRX_HE_SIG_B2_OFDMA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b2_ofdma_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 2 + +#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_OFDMA 1 + +struct phyrx_he_sig_b2_ofdma { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; +#else + struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; +#endif +}; + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 40 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 47 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 48 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 + +#endif diff --git a/hw/kiwi/v2/phyrx_ht_sig.h b/hw/kiwi/v2/phyrx_ht_sig.h new file mode 100644 index 000000000000..3c664392c8a9 --- /dev/null +++ b/hw/kiwi/v2/phyrx_ht_sig.h @@ -0,0 +1,120 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HT_SIG_H_ +#define _PHYRX_HT_SIG_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "ht_sig_info.h" +#define NUM_OF_DWORDS_PHYRX_HT_SIG 2 + +#define NUM_OF_QWORDS_PHYRX_HT_SIG 1 + +struct phyrx_ht_sig { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct ht_sig_info phyrx_ht_sig_info_details; +#else + struct ht_sig_info phyrx_ht_sig_info_details; +#endif +}; + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB 0 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MSB 6 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB 7 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MSB 7 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB 36 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MSB 37 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB 42 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MSB 49 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + +#endif diff --git a/hw/kiwi/v2/phyrx_l_sig_a.h b/hw/kiwi/v2/phyrx_l_sig_a.h new file mode 100644 index 000000000000..14745ec4c02a --- /dev/null +++ b/hw/kiwi/v2/phyrx_l_sig_a.h @@ -0,0 +1,92 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_L_SIG_A_H_ +#define _PHYRX_L_SIG_A_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "l_sig_a_info.h" +#define NUM_OF_DWORDS_PHYRX_L_SIG_A 2 + +#define NUM_OF_QWORDS_PHYRX_L_SIG_A 1 + +struct phyrx_l_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_a_info phyrx_l_sig_a_info_details; + uint32_t tlv64_padding : 32; +#else + struct l_sig_a_info phyrx_l_sig_a_info_details; + uint32_t tlv64_padding : 32; +#endif +}; + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MSB 3 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + +#define PHYRX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_TLV64_PADDING_LSB 32 +#define PHYRX_L_SIG_A_TLV64_PADDING_MSB 63 +#define PHYRX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/phyrx_l_sig_b.h b/hw/kiwi/v2/phyrx_l_sig_b.h new file mode 100644 index 000000000000..a14d0b5feeb5 --- /dev/null +++ b/hw/kiwi/v2/phyrx_l_sig_b.h @@ -0,0 +1,67 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_L_SIG_B_H_ +#define _PHYRX_L_SIG_B_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "l_sig_b_info.h" +#define NUM_OF_DWORDS_PHYRX_L_SIG_B 2 + +#define NUM_OF_QWORDS_PHYRX_L_SIG_B 1 + +struct phyrx_l_sig_b { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_b_info phyrx_l_sig_b_info_details; + uint32_t tlv64_padding : 32; +#else + struct l_sig_b_info phyrx_l_sig_b_info_details; + uint32_t tlv64_padding : 32; +#endif +}; + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0 + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000 + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + +#define PHYRX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_B_TLV64_PADDING_LSB 32 +#define PHYRX_L_SIG_B_TLV64_PADDING_MSB 63 +#define PHYRX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/phyrx_location.h b/hw/kiwi/v2/phyrx_location.h new file mode 100644 index 000000000000..cef9b1fd8877 --- /dev/null +++ b/hw/kiwi/v2/phyrx_location.h @@ -0,0 +1,355 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_LOCATION_H_ +#define _PHYRX_LOCATION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_location_info.h" +#define NUM_OF_DWORDS_PHYRX_LOCATION 28 + +#define NUM_OF_QWORDS_PHYRX_LOCATION 14 + +struct phyrx_location { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_location_info rx_location_info_details; +#else + struct rx_location_info rx_location_info_details; +#endif +}; + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x0000000000000001 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 1 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MSB 1 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x0000000000000002 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_LSB 2 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_MSB 3 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_MASK 0x000000000000000c + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_LSB 4 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MSB 7 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MASK 0x00000000000000f0 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_LSB 8 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MASK 0x000000000000ff00 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MSB 23 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x0000000000ff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_LSB 24 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MASK 0x00000000ff000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MSB 39 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff00000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_LSB 40 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff0000000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MSB 55 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00ff000000000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 56 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0xff00000000000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x0000000000000008 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0x00000000ffffffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000000000008 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 39 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff00000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 40 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x0000ff0000000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x0000000000000008 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MSB 51 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x000f000000000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x0000000000000008 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 52 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MSB 55 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x00f0000000000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x0000000000000008 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 56 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0xff00000000000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x0000000000000010 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x000000000000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x0000000000000010 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MSB 23 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000000000ff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x0000000000000010 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 24 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000000ff000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x0000000000000010 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff00000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_OFFSET 0x0000000000000018 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MASK 0x00000000ffffffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x0000000000000018 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff00000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MASK 0x000000000000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_OFFSET 0x0000000000000020 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MASK 0x00000000ffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_OFFSET 0x0000000000000020 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MASK 0x0000ffff00000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_OFFSET 0x0000000000000020 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MASK 0xffff000000000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_OFFSET 0x0000000000000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MSB 7 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MASK 0x00000000000000ff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x0000000000000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 8 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x000000000000ff00 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_OFFSET 0x0000000000000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MASK 0x00000000ffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_OFFSET 0x0000000000000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MASK 0x0000ffff00000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_OFFSET 0x0000000000000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MASK 0xffff000000000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_OFFSET 0x0000000000000030 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MASK 0x000000000000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_OFFSET 0x0000000000000030 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MASK 0x00000000ffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_OFFSET 0x0000000000000030 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MASK 0x0000ffff00000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_OFFSET 0x0000000000000030 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MASK 0xffff000000000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_OFFSET 0x0000000000000038 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MASK 0x000000000000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_OFFSET 0x0000000000000038 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MASK 0x00000000ffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_OFFSET 0x0000000000000038 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MASK 0x0000ffff00000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_OFFSET 0x0000000000000038 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MASK 0xffff000000000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_OFFSET 0x0000000000000040 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MASK 0x000000000000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_OFFSET 0x0000000000000040 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MASK 0x00000000ffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_OFFSET 0x0000000000000040 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MASK 0x0000ffff00000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_OFFSET 0x0000000000000040 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MASK 0xffff000000000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_OFFSET 0x0000000000000048 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MASK 0x000000000000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_OFFSET 0x0000000000000048 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MASK 0x00000000ffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_OFFSET 0x0000000000000048 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MASK 0x0000ffff00000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_OFFSET 0x0000000000000048 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MASK 0xffff000000000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_OFFSET 0x0000000000000050 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MASK 0x000000000000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_OFFSET 0x0000000000000050 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MASK 0x00000000ffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_OFFSET 0x0000000000000050 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MASK 0x0000ffff00000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_OFFSET 0x0000000000000050 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MASK 0xffff000000000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_OFFSET 0x0000000000000058 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MASK 0x000000000000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_OFFSET 0x0000000000000058 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MASK 0x00000000ffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_OFFSET 0x0000000000000058 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MASK 0x0000ffff00000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_OFFSET 0x0000000000000058 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MASK 0xffff000000000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_OFFSET 0x0000000000000060 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MASK 0x000000000000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_OFFSET 0x0000000000000060 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MASK 0x00000000ffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_OFFSET 0x0000000000000060 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MASK 0x0000ffff00000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_OFFSET 0x0000000000000060 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MASK 0xffff000000000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_OFFSET 0x0000000000000068 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MASK 0x000000000000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_OFFSET 0x0000000000000068 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MASK 0x00000000ffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000000000000068 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/phyrx_other_receive_info_ru_details.h b/hw/kiwi/v2/phyrx_other_receive_info_ru_details.h new file mode 100644 index 000000000000..829bf92f56de --- /dev/null +++ b/hw/kiwi/v2/phyrx_other_receive_info_ru_details.h @@ -0,0 +1,65 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ +#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 4 + +#define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 2 + +struct phyrx_other_receive_info_ru_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ru_details_channel_0 : 32; + uint32_t ru_details_channel_1 : 32; + uint32_t spare : 32; + uint32_t tlv64_padding : 32; +#else + uint32_t ru_details_channel_0 : 32; + uint32_t ru_details_channel_1 : 32; + uint32_t spare : 32; + uint32_t tlv64_padding : 32; +#endif +}; + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MASK 0x00000000ffffffff + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MASK 0xffffffff00000000 + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_OFFSET 0x0000000000000008 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MASK 0x00000000ffffffff + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_OFFSET 0x0000000000000008 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/phyrx_pkt_end.h b/hw/kiwi/v2/phyrx_pkt_end.h new file mode 100644 index 000000000000..16ca0cfa51cd --- /dev/null +++ b/hw/kiwi/v2/phyrx_pkt_end.h @@ -0,0 +1,440 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_PKT_END_H_ +#define _PHYRX_PKT_END_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phyrx_pkt_end_info.h" +#define NUM_OF_DWORDS_PHYRX_PKT_END 24 + +#define NUM_OF_QWORDS_PHYRX_PKT_END 12 + +struct phyrx_pkt_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct phyrx_pkt_end_info rx_pkt_end_details; +#else + struct phyrx_pkt_end_info rx_pkt_end_details; +#endif +}; + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB 1 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MSB 1 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK 0x0000000000000002 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB 2 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MSB 2 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK 0x0000000000000004 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB 3 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MSB 3 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK 0x0000000000000008 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_LSB 4 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MSB 4 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MASK 0x0000000000000010 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MSB 5 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x0000000000000020 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_LSB 6 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MASK 0x00000000000000c0 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MASK 0x000000000000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MASK 0x00000000ffff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff00000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x0000000000000008 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0x00000000ffffffff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000000000008 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff00000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000000000010 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0x00000000ffffffff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x0000000000000010 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 43 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff00000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000010 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 44 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff00000000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x0000000000000058 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK 0x00000000ffffffff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x0000000000000058 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/phyrx_pkt_end_info.h b/hw/kiwi/v2/phyrx_pkt_end_info.h new file mode 100644 index 000000000000..cf1a617684b8 --- /dev/null +++ b/hw/kiwi/v2/phyrx_pkt_end_info.h @@ -0,0 +1,471 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_PKT_END_INFO_H_ +#define _PHYRX_PKT_END_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "receive_rssi_info.h" +#include "rx_timing_offset_info.h" +#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 24 + +struct phyrx_pkt_end_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t __reserved_g_0001 : 1, + location_info_valid : 1, + timing_info_valid : 1, + rssi_info_valid : 1, + reserved_0a : 1, + frameless_frame_received : 1, + reserved_0b : 2, + rssi_comb : 8, + reserved_0c : 16; + uint32_t phy_timestamp_1_lower_32 : 32; + uint32_t phy_timestamp_1_upper_32 : 32; + uint32_t phy_timestamp_2_lower_32 : 32; + uint32_t phy_timestamp_2_upper_32 : 32; + struct rx_timing_offset_info rx_timing_offset_info_details; + struct receive_rssi_info post_rssi_info_details; + uint32_t phy_sw_status_31_0 : 32; + uint32_t phy_sw_status_63_32 : 32; +#else + uint32_t reserved_0c : 16, + rssi_comb : 8, + reserved_0b : 2, + frameless_frame_received : 1, + reserved_0a : 1, + rssi_info_valid : 1, + timing_info_valid : 1, + location_info_valid : 1, + __reserved_g_0001 : 1; + uint32_t phy_timestamp_1_lower_32 : 32; + uint32_t phy_timestamp_1_upper_32 : 32; + uint32_t phy_timestamp_2_lower_32 : 32; + uint32_t phy_timestamp_2_upper_32 : 32; + struct rx_timing_offset_info rx_timing_offset_info_details; + struct receive_rssi_info post_rssi_info_details; + uint32_t phy_sw_status_31_0 : 32; + uint32_t phy_sw_status_63_32 : 32; +#endif +}; + +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_LSB 1 +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MSB 1 +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MASK 0x00000002 + +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_LSB 2 +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MSB 2 +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MASK 0x00000004 + +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_LSB 3 +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MSB 3 +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MASK 0x00000008 + +#define PHYRX_PKT_END_INFO_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RESERVED_0A_LSB 4 +#define PHYRX_PKT_END_INFO_RESERVED_0A_MSB 4 +#define PHYRX_PKT_END_INFO_RESERVED_0A_MASK 0x00000010 + +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_LSB 5 +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MSB 5 +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 + +#define PHYRX_PKT_END_INFO_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RESERVED_0B_LSB 6 +#define PHYRX_PKT_END_INFO_RESERVED_0B_MSB 7 +#define PHYRX_PKT_END_INFO_RESERVED_0B_MASK 0x000000c0 + +#define PHYRX_PKT_END_INFO_RSSI_COMB_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RSSI_COMB_LSB 8 +#define PHYRX_PKT_END_INFO_RSSI_COMB_MSB 15 +#define PHYRX_PKT_END_INFO_RSSI_COMB_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_RESERVED_0C_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RESERVED_0C_LSB 16 +#define PHYRX_PKT_END_INFO_RESERVED_0C_MSB 31 +#define PHYRX_PKT_END_INFO_RESERVED_0C_MASK 0xffff0000 + +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000014 +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 11 +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000014 +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12 +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MSB 31 +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_OFFSET 0x00000058 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_OFFSET 0x0000005c +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MASK 0xffffffff + +#endif diff --git a/hw/kiwi/v2/phyrx_rssi_legacy.h b/hw/kiwi/v2/phyrx_rssi_legacy.h new file mode 100644 index 000000000000..807532335662 --- /dev/null +++ b/hw/kiwi/v2/phyrx_rssi_legacy.h @@ -0,0 +1,836 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_RSSI_LEGACY_H_ +#define _PHYRX_RSSI_LEGACY_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "receive_rssi_info.h" +#define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 42 + +#define NUM_OF_QWORDS_PHYRX_RSSI_LEGACY 21 + +struct phyrx_rssi_legacy { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reception_type : 4, + rx_chain_mask_type : 1, + receive_bandwidth : 3, + rx_chain_mask : 8, + phy_ppdu_id : 16; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t reserved_4a : 32; + uint32_t preamble_time_to_rxframe : 8, + standalone_snifer_mode : 1, + reserved_5a : 23; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + struct receive_rssi_info pre_rssi_info_details; + struct receive_rssi_info preamble_rssi_info_details; + uint32_t pre_rssi_comb : 8, + rssi_comb : 8, + normalized_pre_rssi_comb : 8, + normalized_rssi_comb : 8; + uint32_t rssi_comb_ppdu : 8, + rssi_db_to_dbm_offset : 8, + rssi_for_spatial_reuse : 8, + rssi_for_trigger_resp : 8; +#else + uint32_t phy_ppdu_id : 16, + rx_chain_mask : 8, + receive_bandwidth : 3, + rx_chain_mask_type : 1, + reception_type : 4; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 23, + standalone_snifer_mode : 1, + preamble_time_to_rxframe : 8; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + struct receive_rssi_info pre_rssi_info_details; + struct receive_rssi_info preamble_rssi_info_details; + uint32_t normalized_rssi_comb : 8, + normalized_pre_rssi_comb : 8, + rssi_comb : 8, + pre_rssi_comb : 8; + uint32_t rssi_for_trigger_resp : 8, + rssi_for_spatial_reuse : 8, + rssi_db_to_dbm_offset : 8, + rssi_comb_ppdu : 8; +#endif +}; + +#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_OFFSET 0x0000000000000000 +#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_LSB 0 +#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_MSB 3 +#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_MASK 0x000000000000000f + +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000000 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_LSB 4 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_MSB 4 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_MASK 0x0000000000000010 + +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_LSB 5 +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MSB 7 +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MASK 0x00000000000000e0 + +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_OFFSET 0x0000000000000000 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_LSB 8 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_MSB 15 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_MASK 0x000000000000ff00 + +#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_LSB 16 +#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_MSB 31 +#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_MASK 0x00000000ffff0000 + +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_OFFSET 0x0000000000000000 +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_LSB 32 +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MSB 63 +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MASK 0xffffffff00000000 + +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000008 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff + +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_LSB 32 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_MSB 63 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 + +#define PHYRX_RSSI_LEGACY_RESERVED_4A_OFFSET 0x0000000000000010 +#define PHYRX_RSSI_LEGACY_RESERVED_4A_LSB 0 +#define PHYRX_RSSI_LEGACY_RESERVED_4A_MSB 31 +#define PHYRX_RSSI_LEGACY_RESERVED_4A_MASK 0x00000000ffffffff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000010 +#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff00000000 + +#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFER_MODE_OFFSET 0x0000000000000010 +#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFER_MODE_LSB 40 +#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFER_MODE_MSB 40 +#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFER_MODE_MASK 0x0000010000000000 + +#define PHYRX_RSSI_LEGACY_RESERVED_5A_OFFSET 0x0000000000000010 +#define PHYRX_RSSI_LEGACY_RESERVED_5A_LSB 41 +#define PHYRX_RSSI_LEGACY_RESERVED_5A_MSB 63 +#define PHYRX_RSSI_LEGACY_RESERVED_5A_MASK 0xfffffe0000000000 + +#define PHYRX_RSSI_LEGACY_RESERVED_6A_OFFSET 0x0000000000000018 +#define PHYRX_RSSI_LEGACY_RESERVED_6A_LSB 0 +#define PHYRX_RSSI_LEGACY_RESERVED_6A_MSB 31 +#define PHYRX_RSSI_LEGACY_RESERVED_6A_MASK 0x00000000ffffffff + +#define PHYRX_RSSI_LEGACY_RESERVED_7A_OFFSET 0x0000000000000018 +#define PHYRX_RSSI_LEGACY_RESERVED_7A_LSB 32 +#define PHYRX_RSSI_LEGACY_RESERVED_7A_MSB 63 +#define PHYRX_RSSI_LEGACY_RESERVED_7A_MASK 0xffffffff00000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MASK 0x00000000000000ff + +#define PHYRX_RSSI_LEGACY_RSSI_COMB_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_LSB 8 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_MSB 15 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_MASK 0x000000000000ff00 + +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_LSB 16 +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MSB 23 +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000 + +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_LSB 24 +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MSB 31 +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000 + +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_LSB 32 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MSB 39 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MASK 0x000000ff00000000 + +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_LSB 40 +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MSB 47 +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MASK 0x0000ff0000000000 + +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_LSB 48 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MSB 55 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MASK 0x00ff000000000000 + +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_LSB 56 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MSB 63 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MASK 0xff00000000000000 + +#endif diff --git a/hw/kiwi/v2/phyrx_user_info.h b/hw/kiwi/v2/phyrx_user_info.h new file mode 100644 index 000000000000..5ef8f2589df5 --- /dev/null +++ b/hw/kiwi/v2/phyrx_user_info.h @@ -0,0 +1,210 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_USER_INFO_H_ +#define _PHYRX_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "receive_user_info.h" +#define NUM_OF_DWORDS_PHYRX_USER_INFO 8 + +#define NUM_OF_QWORDS_PHYRX_USER_INFO 4 + +struct phyrx_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct receive_user_info receive_user_info_details; +#else + struct receive_user_info receive_user_info_details; +#endif +}; + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x000000000000ffff + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x0000000000000000 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x0000000000ff0000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x0000000010000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0x00000000e0000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x0000000000000000 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 32 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 35 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f00000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x0000000000000000 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 36 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 37 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x0000003000000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_LSB 39 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MSB 39 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x0000000000000000 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 40 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 47 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff0000000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 48 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 50 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x0007000000000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 51 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 55 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f8000000000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x0000000000000000 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 56 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 63 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff00000000000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x0000000000000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x0000000000000001 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 7 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x00000000000000fe + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x0000000000000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x0000000000000700 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x0000000000000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x0000000000003800 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x0000000000004000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x0000000000000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x0000000000008000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x0000000000000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x00000000000f0000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x0000000000000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x0000000000f00000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x0000000000000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x000000000f000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x0000000000000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0x00000000f0000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000000000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 32 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 37 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f00000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 38 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 39 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c000000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000000000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 40 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 45 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f0000000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 46 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 47 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c00000000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000000000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 48 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 53 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f000000000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000000000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 54 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 55 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c0000000000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000000000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 56 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 61 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f00000000000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000000000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 62 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 63 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0xc000000000000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET 0x0000000000000010 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK 0x00000000ffffffff + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET 0x0000000000000010 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB 32 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB 63 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK 0xffffffff00000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET 0x0000000000000018 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK 0x00000000ffffffff + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET 0x0000000000000018 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB 32 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB 63 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/phyrx_vht_sig_a.h b/hw/kiwi/v2/phyrx_vht_sig_a.h new file mode 100644 index 000000000000..ce349d77e4e0 --- /dev/null +++ b/hw/kiwi/v2/phyrx_vht_sig_a.h @@ -0,0 +1,130 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_VHT_SIG_A_H_ +#define _PHYRX_VHT_SIG_A_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_a_info.h" +#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2 + +#define NUM_OF_QWORDS_PHYRX_VHT_SIG_A 1 + +struct phyrx_vht_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_a_info phyrx_vht_sig_a_info_details; +#else + struct vht_sig_a_info phyrx_vht_sig_a_info_details; +#endif +}; + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + +#endif diff --git a/hw/kiwi/v2/receive_rssi_info.h b/hw/kiwi/v2/receive_rssi_info.h new file mode 100644 index 000000000000..a003781d6684 --- /dev/null +++ b/hw/kiwi/v2/receive_rssi_info.h @@ -0,0 +1,483 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVE_RSSI_INFO_H_ +#define _RECEIVE_RSSI_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16 + +struct receive_rssi_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rssi_pri20_chain0 : 8, + rssi_ext20_chain0 : 8, + rssi_ext40_low20_chain0 : 8, + rssi_ext40_high20_chain0 : 8; + uint32_t rssi_ext80_low20_chain0 : 8, + rssi_ext80_low_high20_chain0 : 8, + rssi_ext80_high_low20_chain0 : 8, + rssi_ext80_high20_chain0 : 8; + uint32_t rssi_ext160_0_chain0 : 8, + rssi_ext160_1_chain0 : 8, + rssi_ext160_2_chain0 : 8, + rssi_ext160_3_chain0 : 8; + uint32_t rssi_ext160_4_chain0 : 8, + rssi_ext160_5_chain0 : 8, + rssi_ext160_6_chain0 : 8, + rssi_ext160_7_chain0 : 8; + uint32_t rssi_pri20_chain1 : 8, + rssi_ext20_chain1 : 8, + rssi_ext40_low20_chain1 : 8, + rssi_ext40_high20_chain1 : 8; + uint32_t rssi_ext80_low20_chain1 : 8, + rssi_ext80_low_high20_chain1 : 8, + rssi_ext80_high_low20_chain1 : 8, + rssi_ext80_high20_chain1 : 8; + uint32_t rssi_ext160_0_chain1 : 8, + rssi_ext160_1_chain1 : 8, + rssi_ext160_2_chain1 : 8, + rssi_ext160_3_chain1 : 8; + uint32_t rssi_ext160_4_chain1 : 8, + rssi_ext160_5_chain1 : 8, + rssi_ext160_6_chain1 : 8, + rssi_ext160_7_chain1 : 8; + uint32_t rssi_pri20_chain2 : 8, + rssi_ext20_chain2 : 8, + rssi_ext40_low20_chain2 : 8, + rssi_ext40_high20_chain2 : 8; + uint32_t rssi_ext80_low20_chain2 : 8, + rssi_ext80_low_high20_chain2 : 8, + rssi_ext80_high_low20_chain2 : 8, + rssi_ext80_high20_chain2 : 8; + uint32_t rssi_ext160_0_chain2 : 8, + rssi_ext160_1_chain2 : 8, + rssi_ext160_2_chain2 : 8, + rssi_ext160_3_chain2 : 8; + uint32_t rssi_ext160_4_chain2 : 8, + rssi_ext160_5_chain2 : 8, + rssi_ext160_6_chain2 : 8, + rssi_ext160_7_chain2 : 8; + uint32_t rssi_pri20_chain3 : 8, + rssi_ext20_chain3 : 8, + rssi_ext40_low20_chain3 : 8, + rssi_ext40_high20_chain3 : 8; + uint32_t rssi_ext80_low20_chain3 : 8, + rssi_ext80_low_high20_chain3 : 8, + rssi_ext80_high_low20_chain3 : 8, + rssi_ext80_high20_chain3 : 8; + uint32_t rssi_ext160_0_chain3 : 8, + rssi_ext160_1_chain3 : 8, + rssi_ext160_2_chain3 : 8, + rssi_ext160_3_chain3 : 8; + uint32_t rssi_ext160_4_chain3 : 8, + rssi_ext160_5_chain3 : 8, + rssi_ext160_6_chain3 : 8, + rssi_ext160_7_chain3 : 8; +#else + uint32_t rssi_ext40_high20_chain0 : 8, + rssi_ext40_low20_chain0 : 8, + rssi_ext20_chain0 : 8, + rssi_pri20_chain0 : 8; + uint32_t rssi_ext80_high20_chain0 : 8, + rssi_ext80_high_low20_chain0 : 8, + rssi_ext80_low_high20_chain0 : 8, + rssi_ext80_low20_chain0 : 8; + uint32_t rssi_ext160_3_chain0 : 8, + rssi_ext160_2_chain0 : 8, + rssi_ext160_1_chain0 : 8, + rssi_ext160_0_chain0 : 8; + uint32_t rssi_ext160_7_chain0 : 8, + rssi_ext160_6_chain0 : 8, + rssi_ext160_5_chain0 : 8, + rssi_ext160_4_chain0 : 8; + uint32_t rssi_ext40_high20_chain1 : 8, + rssi_ext40_low20_chain1 : 8, + rssi_ext20_chain1 : 8, + rssi_pri20_chain1 : 8; + uint32_t rssi_ext80_high20_chain1 : 8, + rssi_ext80_high_low20_chain1 : 8, + rssi_ext80_low_high20_chain1 : 8, + rssi_ext80_low20_chain1 : 8; + uint32_t rssi_ext160_3_chain1 : 8, + rssi_ext160_2_chain1 : 8, + rssi_ext160_1_chain1 : 8, + rssi_ext160_0_chain1 : 8; + uint32_t rssi_ext160_7_chain1 : 8, + rssi_ext160_6_chain1 : 8, + rssi_ext160_5_chain1 : 8, + rssi_ext160_4_chain1 : 8; + uint32_t rssi_ext40_high20_chain2 : 8, + rssi_ext40_low20_chain2 : 8, + rssi_ext20_chain2 : 8, + rssi_pri20_chain2 : 8; + uint32_t rssi_ext80_high20_chain2 : 8, + rssi_ext80_high_low20_chain2 : 8, + rssi_ext80_low_high20_chain2 : 8, + rssi_ext80_low20_chain2 : 8; + uint32_t rssi_ext160_3_chain2 : 8, + rssi_ext160_2_chain2 : 8, + rssi_ext160_1_chain2 : 8, + rssi_ext160_0_chain2 : 8; + uint32_t rssi_ext160_7_chain2 : 8, + rssi_ext160_6_chain2 : 8, + rssi_ext160_5_chain2 : 8, + rssi_ext160_4_chain2 : 8; + uint32_t rssi_ext40_high20_chain3 : 8, + rssi_ext40_low20_chain3 : 8, + rssi_ext20_chain3 : 8, + rssi_pri20_chain3 : 8; + uint32_t rssi_ext80_high20_chain3 : 8, + rssi_ext80_high_low20_chain3 : 8, + rssi_ext80_low_high20_chain3 : 8, + rssi_ext80_low20_chain3 : 8; + uint32_t rssi_ext160_3_chain3 : 8, + rssi_ext160_2_chain3 : 8, + rssi_ext160_1_chain3 : 8, + rssi_ext160_0_chain3 : 8; + uint32_t rssi_ext160_7_chain3 : 8, + rssi_ext160_6_chain3 : 8, + rssi_ext160_5_chain3 : 8, + rssi_ext160_4_chain3 : 8; +#endif +}; + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 + +#endif diff --git a/hw/kiwi/v2/receive_user_info.h b/hw/kiwi/v2/receive_user_info.h new file mode 100644 index 000000000000..6e44c1049579 --- /dev/null +++ b/hw/kiwi/v2/receive_user_info.h @@ -0,0 +1,275 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVE_USER_INFO_H_ +#define _RECEIVE_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RECEIVE_USER_INFO 8 + +struct receive_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_ppdu_id : 16, + user_rssi : 8, + pkt_type : 4, + stbc : 1, + reception_type : 3; + uint32_t rate_mcs : 4, + sgi : 2, + __reserved_g_0004 : 1, + reserved_1a : 1, + mimo_ss_bitmap : 8, + receive_bandwidth : 3, + reserved_1b : 5, + dl_ofdma_user_index : 8; + uint32_t dl_ofdma_content_channel : 1, + reserved_2a : 7, + nss : 3, + stream_offset : 3, + sta_dcm : 1, + ldpc : 1, + ru_type_80_0 : 4, + ru_type_80_1 : 4, + ru_type_80_2 : 4, + ru_type_80_3 : 4; + uint32_t ru_start_index_80_0 : 6, + reserved_3a : 2, + ru_start_index_80_1 : 6, + reserved_3b : 2, + ru_start_index_80_2 : 6, + reserved_3c : 2, + ru_start_index_80_3 : 6, + reserved_3d : 2; + uint32_t user_fd_rssi_seg0 : 32; + uint32_t user_fd_rssi_seg1 : 32; + uint32_t user_fd_rssi_seg2 : 32; + uint32_t user_fd_rssi_seg3 : 32; +#else + uint32_t reception_type : 3, + stbc : 1, + pkt_type : 4, + user_rssi : 8, + phy_ppdu_id : 16; + uint32_t dl_ofdma_user_index : 8, + reserved_1b : 5, + receive_bandwidth : 3, + mimo_ss_bitmap : 8, + reserved_1a : 1, + __reserved_g_0004 : 1, + sgi : 2, + rate_mcs : 4; + uint32_t ru_type_80_3 : 4, + ru_type_80_2 : 4, + ru_type_80_1 : 4, + ru_type_80_0 : 4, + ldpc : 1, + sta_dcm : 1, + stream_offset : 3, + nss : 3, + reserved_2a : 7, + dl_ofdma_content_channel : 1; + uint32_t reserved_3d : 2, + ru_start_index_80_3 : 6, + reserved_3c : 2, + ru_start_index_80_2 : 6, + reserved_3b : 2, + ru_start_index_80_1 : 6, + reserved_3a : 2, + ru_start_index_80_0 : 6; + uint32_t user_fd_rssi_seg0 : 32; + uint32_t user_fd_rssi_seg1 : 32; + uint32_t user_fd_rssi_seg2 : 32; + uint32_t user_fd_rssi_seg3 : 32; +#endif +}; + +#define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB 0 +#define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB 15 +#define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK 0x0000ffff + +#define RECEIVE_USER_INFO_USER_RSSI_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_USER_RSSI_LSB 16 +#define RECEIVE_USER_INFO_USER_RSSI_MSB 23 +#define RECEIVE_USER_INFO_USER_RSSI_MASK 0x00ff0000 + +#define RECEIVE_USER_INFO_PKT_TYPE_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_PKT_TYPE_LSB 24 +#define RECEIVE_USER_INFO_PKT_TYPE_MSB 27 +#define RECEIVE_USER_INFO_PKT_TYPE_MASK 0x0f000000 + +#define RECEIVE_USER_INFO_STBC_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_STBC_LSB 28 +#define RECEIVE_USER_INFO_STBC_MSB 28 +#define RECEIVE_USER_INFO_STBC_MASK 0x10000000 + +#define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB 29 +#define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB 31 +#define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK 0xe0000000 + +#define RECEIVE_USER_INFO_RATE_MCS_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RATE_MCS_LSB 0 +#define RECEIVE_USER_INFO_RATE_MCS_MSB 3 +#define RECEIVE_USER_INFO_RATE_MCS_MASK 0x0000000f + +#define RECEIVE_USER_INFO_SGI_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_SGI_LSB 4 +#define RECEIVE_USER_INFO_SGI_MSB 5 +#define RECEIVE_USER_INFO_SGI_MASK 0x00000030 + +#define RECEIVE_USER_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RESERVED_1A_LSB 7 +#define RECEIVE_USER_INFO_RESERVED_1A_MSB 7 +#define RECEIVE_USER_INFO_RESERVED_1A_MASK 0x00000080 + +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB 8 +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB 15 +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK 0x0000ff00 + +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB 16 +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB 18 +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK 0x00070000 + +#define RECEIVE_USER_INFO_RESERVED_1B_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RESERVED_1B_LSB 19 +#define RECEIVE_USER_INFO_RESERVED_1B_MSB 23 +#define RECEIVE_USER_INFO_RESERVED_1B_MASK 0x00f80000 + +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB 24 +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB 31 +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK 0xff000000 + +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB 0 +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB 0 +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001 + +#define RECEIVE_USER_INFO_RESERVED_2A_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RESERVED_2A_LSB 1 +#define RECEIVE_USER_INFO_RESERVED_2A_MSB 7 +#define RECEIVE_USER_INFO_RESERVED_2A_MASK 0x000000fe + +#define RECEIVE_USER_INFO_NSS_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_NSS_LSB 8 +#define RECEIVE_USER_INFO_NSS_MSB 10 +#define RECEIVE_USER_INFO_NSS_MASK 0x00000700 + +#define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_STREAM_OFFSET_LSB 11 +#define RECEIVE_USER_INFO_STREAM_OFFSET_MSB 13 +#define RECEIVE_USER_INFO_STREAM_OFFSET_MASK 0x00003800 + +#define RECEIVE_USER_INFO_STA_DCM_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_STA_DCM_LSB 14 +#define RECEIVE_USER_INFO_STA_DCM_MSB 14 +#define RECEIVE_USER_INFO_STA_DCM_MASK 0x00004000 + +#define RECEIVE_USER_INFO_LDPC_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_LDPC_LSB 15 +#define RECEIVE_USER_INFO_LDPC_MSB 15 +#define RECEIVE_USER_INFO_LDPC_MASK 0x00008000 + +#define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB 16 +#define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB 19 +#define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK 0x000f0000 + +#define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB 20 +#define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB 23 +#define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK 0x00f00000 + +#define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB 24 +#define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB 27 +#define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK 0x0f000000 + +#define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB 28 +#define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB 31 +#define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK 0xf0000000 + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB 0 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB 5 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK 0x0000003f + +#define RECEIVE_USER_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3A_LSB 6 +#define RECEIVE_USER_INFO_RESERVED_3A_MSB 7 +#define RECEIVE_USER_INFO_RESERVED_3A_MASK 0x000000c0 + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB 8 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB 13 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK 0x00003f00 + +#define RECEIVE_USER_INFO_RESERVED_3B_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3B_LSB 14 +#define RECEIVE_USER_INFO_RESERVED_3B_MSB 15 +#define RECEIVE_USER_INFO_RESERVED_3B_MASK 0x0000c000 + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB 16 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB 21 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK 0x003f0000 + +#define RECEIVE_USER_INFO_RESERVED_3C_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3C_LSB 22 +#define RECEIVE_USER_INFO_RESERVED_3C_MSB 23 +#define RECEIVE_USER_INFO_RESERVED_3C_MASK 0x00c00000 + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB 24 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB 29 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK 0x3f000000 + +#define RECEIVE_USER_INFO_RESERVED_3D_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3D_LSB 30 +#define RECEIVE_USER_INFO_RESERVED_3D_MSB 31 +#define RECEIVE_USER_INFO_RESERVED_3D_MASK 0xc0000000 + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_OFFSET 0x00000010 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MASK 0xffffffff + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_OFFSET 0x00000014 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MASK 0xffffffff + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_OFFSET 0x00000018 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MASK 0xffffffff + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_OFFSET 0x0000001c +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MASK 0xffffffff + +#endif diff --git a/hw/kiwi/v2/reo_descriptor_threshold_reached_status.h b/hw/kiwi/v2/reo_descriptor_threshold_reached_status.h new file mode 100644 index 000000000000..3cde4b9cc014 --- /dev/null +++ b/hw/kiwi/v2/reo_descriptor_threshold_reached_status.h @@ -0,0 +1,275 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ +#define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 26 + +#define NUM_OF_QWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 13 + +struct reo_descriptor_threshold_reached_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t threshold_index : 2, + reserved_2 : 30; + uint32_t link_descriptor_counter0 : 24, + reserved_3 : 8; + uint32_t link_descriptor_counter1 : 24, + reserved_4 : 8; + uint32_t link_descriptor_counter2 : 24, + reserved_5 : 8; + uint32_t link_descriptor_counter_sum : 26, + reserved_6 : 6; + uint32_t reserved_7 : 32; + uint32_t reserved_8 : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2 : 30, + threshold_index : 2; + uint32_t reserved_3 : 8, + link_descriptor_counter0 : 24; + uint32_t reserved_4 : 8, + link_descriptor_counter1 : 24; + uint32_t reserved_5 : 8, + link_descriptor_counter2 : 24; + uint32_t reserved_6 : 6, + link_descriptor_counter_sum : 26; + uint32_t reserved_7 : 32; + uint32_t reserved_8 : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_OFFSET 0x0000000000000008 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MSB 1 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MASK 0x0000000000000003 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_OFFSET 0x0000000000000008 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_LSB 2 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MASK 0x00000000fffffffc + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x0000000000000008 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MSB 55 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff00000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_OFFSET 0x0000000000000008 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_LSB 56 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MASK 0xff00000000000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x0000000000000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MSB 23 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MASK 0x0000000000ffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_OFFSET 0x0000000000000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_LSB 24 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MASK 0x00000000ff000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x0000000000000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MSB 55 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff00000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_OFFSET 0x0000000000000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_LSB 56 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MASK 0xff00000000000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x0000000000000018 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MSB 25 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x0000000003ffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_OFFSET 0x0000000000000018 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_LSB 26 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MASK 0x00000000fc000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_OFFSET 0x0000000000000018 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MASK 0xffffffff00000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_OFFSET 0x0000000000000020 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MASK 0x00000000ffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MASK 0xffffffff00000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MASK 0x00000000ffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MASK 0xffffffff00000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MASK 0x00000000ffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MASK 0xffffffff00000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MASK 0x00000000ffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MASK 0xffffffff00000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MASK 0x00000000ffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MASK 0xffffffff00000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MASK 0x00000000ffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MASK 0xffffffff00000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MASK 0x00000000ffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MASK 0xffffffff00000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MASK 0x00000000ffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MASK 0xffffffff00000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MASK 0x00000000ffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MSB 59 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_LSB 60 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + +#endif diff --git a/hw/kiwi/v2/reo_destination_ring.h b/hw/kiwi/v2/reo_destination_ring.h new file mode 100644 index 000000000000..13fda8bbf514 --- /dev/null +++ b/hw/kiwi/v2/reo_destination_ring.h @@ -0,0 +1,286 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_DESTINATION_RING_H_ +#define _REO_DESTINATION_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_msdu_desc_info.h" +#include "rx_mpdu_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_REO_DESTINATION_RING 8 + +struct reo_destination_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buf_or_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t reo_dest_buffer_type : 1, + reo_push_reason : 2, + reo_error_code : 5, + captured_msdu_data_size : 4, + sw_exception : 1, + src_link_id : 3, + reo_destination_struct_signature : 4, + ring_id : 8, + looping_count : 4; +#else + struct buffer_addr_info buf_or_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t looping_count : 4, + ring_id : 8, + reo_destination_struct_signature : 4, + src_link_id : 3, + sw_exception : 1, + captured_msdu_data_size : 4, + reo_error_code : 5, + reo_push_reason : 2, + reo_dest_buffer_type : 1; +#endif +}; + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000 + +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000014 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000018 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_LSB 0 +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MSB 0 +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MASK 0x00000001 + +#define REO_DESTINATION_RING_REO_PUSH_REASON_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_PUSH_REASON_LSB 1 +#define REO_DESTINATION_RING_REO_PUSH_REASON_MSB 2 +#define REO_DESTINATION_RING_REO_PUSH_REASON_MASK 0x00000006 + +#define REO_DESTINATION_RING_REO_ERROR_CODE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_ERROR_CODE_LSB 3 +#define REO_DESTINATION_RING_REO_ERROR_CODE_MSB 7 +#define REO_DESTINATION_RING_REO_ERROR_CODE_MASK 0x000000f8 + +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_LSB 8 +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MSB 11 +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00 + +#define REO_DESTINATION_RING_SW_EXCEPTION_OFFSET 0x0000001c +#define REO_DESTINATION_RING_SW_EXCEPTION_LSB 12 +#define REO_DESTINATION_RING_SW_EXCEPTION_MSB 12 +#define REO_DESTINATION_RING_SW_EXCEPTION_MASK 0x00001000 + +#define REO_DESTINATION_RING_SRC_LINK_ID_OFFSET 0x0000001c +#define REO_DESTINATION_RING_SRC_LINK_ID_LSB 13 +#define REO_DESTINATION_RING_SRC_LINK_ID_MSB 15 +#define REO_DESTINATION_RING_SRC_LINK_ID_MASK 0x0000e000 + +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16 +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19 +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000 + +#define REO_DESTINATION_RING_RING_ID_OFFSET 0x0000001c +#define REO_DESTINATION_RING_RING_ID_LSB 20 +#define REO_DESTINATION_RING_RING_ID_MSB 27 +#define REO_DESTINATION_RING_RING_ID_MASK 0x0ff00000 + +#define REO_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define REO_DESTINATION_RING_LOOPING_COUNT_LSB 28 +#define REO_DESTINATION_RING_LOOPING_COUNT_MSB 31 +#define REO_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/kiwi/v2/reo_destination_ring_with_pn.h b/hw/kiwi/v2/reo_destination_ring_with_pn.h new file mode 100644 index 000000000000..0eb57922ff2a --- /dev/null +++ b/hw/kiwi/v2/reo_destination_ring_with_pn.h @@ -0,0 +1,244 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_DESTINATION_RING_WITH_PN_H_ +#define _REO_DESTINATION_RING_WITH_PN_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_msdu_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_REO_DESTINATION_RING_WITH_PN 8 + +struct reo_destination_ring_with_pn { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buf_or_link_desc_addr_info; + uint32_t msdu_count : 8, + prev_pn_23_0 : 24; + uint32_t prev_pn_55_24 : 32; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t reo_dest_buffer_type : 1, + reo_push_reason : 2, + reo_error_code : 5, + captured_msdu_data_size : 4, + sw_exception : 1, + src_link_id : 3, + reo_destination_struct_signature : 4, + ring_id : 8, + looping_count : 4; +#else + struct buffer_addr_info buf_or_link_desc_addr_info; + uint32_t prev_pn_23_0 : 24, + msdu_count : 8; + uint32_t prev_pn_55_24 : 32; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t looping_count : 4, + ring_id : 8, + reo_destination_struct_signature : 4, + src_link_id : 3, + sw_exception : 1, + captured_msdu_data_size : 4, + reo_error_code : 5, + reo_push_reason : 2, + reo_dest_buffer_type : 1; +#endif +}; + +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MSB 7 +#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MASK 0x000000ff + +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_OFFSET 0x00000008 +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_LSB 8 +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MASK 0xffffff00 + +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_OFFSET 0x0000000c +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_MASK 0xffffffff + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000 + +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000014 +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000018 +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + +#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MSB 0 +#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MASK 0x00000001 + +#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_LSB 1 +#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MSB 2 +#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MASK 0x00000006 + +#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_LSB 3 +#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MSB 7 +#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MASK 0x000000f8 + +#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_LSB 8 +#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MSB 11 +#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00 + +#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_LSB 12 +#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MSB 12 +#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MASK 0x00001000 + +#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_LSB 13 +#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MSB 15 +#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MASK 0x0000e000 + +#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16 +#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19 +#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000 + +#define REO_DESTINATION_RING_WITH_PN_RING_ID_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_RING_ID_LSB 20 +#define REO_DESTINATION_RING_WITH_PN_RING_ID_MSB 27 +#define REO_DESTINATION_RING_WITH_PN_RING_ID_MASK 0x0ff00000 + +#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_LSB 28 +#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/kiwi/v2/reo_entrance_ring.h b/hw/kiwi/v2/reo_entrance_ring.h new file mode 100644 index 000000000000..860b678ef3a6 --- /dev/null +++ b/hw/kiwi/v2/reo_entrance_ring.h @@ -0,0 +1,258 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_ENTRANCE_RING_H_ +#define _REO_ENTRANCE_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_details.h" +#define NUM_OF_DWORDS_REO_ENTRANCE_RING 8 + +struct reo_entrance_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_mpdu_details reo_level_mpdu_frame_info; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + rounded_mpdu_byte_count : 14, + reo_destination_indication : 5, + frameless_bar : 1, + reserved_5a : 4; + uint32_t rxdma_push_reason : 2, + rxdma_error_code : 5, + mpdu_fragment_number : 4, + sw_exception : 1, + sw_exception_mpdu_delink : 1, + sw_exception_destination_ring_valid : 1, + sw_exception_destination_ring : 5, + mpdu_sequence_number : 12, + reserved_6a : 1; + uint32_t phy_ppdu_id : 16, + src_link_id : 3, + reserved_7a : 1, + ring_id : 8, + looping_count : 4; +#else + struct rx_mpdu_details reo_level_mpdu_frame_info; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t reserved_5a : 4, + frameless_bar : 1, + reo_destination_indication : 5, + rounded_mpdu_byte_count : 14, + rx_reo_queue_desc_addr_39_32 : 8; + uint32_t reserved_6a : 1, + mpdu_sequence_number : 12, + sw_exception_destination_ring : 5, + sw_exception_destination_ring_valid : 1, + sw_exception_mpdu_delink : 1, + sw_exception : 1, + mpdu_fragment_number : 4, + rxdma_error_code : 5, + rxdma_push_reason : 2; + uint32_t looping_count : 4, + ring_id : 8, + reserved_7a : 1, + src_link_id : 3, + phy_ppdu_id : 16; +#endif +}; + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_LSB 8 +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MSB 21 +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 + +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_LSB 22 +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MSB 26 +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MASK 0x07c00000 + +#define REO_ENTRANCE_RING_FRAMELESS_BAR_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_FRAMELESS_BAR_LSB 27 +#define REO_ENTRANCE_RING_FRAMELESS_BAR_MSB 27 +#define REO_ENTRANCE_RING_FRAMELESS_BAR_MASK 0x08000000 + +#define REO_ENTRANCE_RING_RESERVED_5A_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_RESERVED_5A_LSB 28 +#define REO_ENTRANCE_RING_RESERVED_5A_MSB 31 +#define REO_ENTRANCE_RING_RESERVED_5A_MASK 0xf0000000 + +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB 0 +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MSB 1 +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK 0x00000003 + +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB 2 +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MSB 6 +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK 0x0000007c + +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_LSB 7 +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MSB 10 +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 + +#define REO_ENTRANCE_RING_SW_EXCEPTION_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_LSB 11 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MSB 11 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MASK 0x00000800 + +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_LSB 12 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MSB 12 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000 + +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MSB 13 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000 + +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_LSB 14 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MSB 18 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000 + +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_LSB 19 +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MSB 30 +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MASK 0x7ff80000 + +#define REO_ENTRANCE_RING_RESERVED_6A_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_RESERVED_6A_LSB 31 +#define REO_ENTRANCE_RING_RESERVED_6A_MSB 31 +#define REO_ENTRANCE_RING_RESERVED_6A_MASK 0x80000000 + +#define REO_ENTRANCE_RING_PHY_PPDU_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_PHY_PPDU_ID_LSB 0 +#define REO_ENTRANCE_RING_PHY_PPDU_ID_MSB 15 +#define REO_ENTRANCE_RING_PHY_PPDU_ID_MASK 0x0000ffff + +#define REO_ENTRANCE_RING_SRC_LINK_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_SRC_LINK_ID_LSB 16 +#define REO_ENTRANCE_RING_SRC_LINK_ID_MSB 18 +#define REO_ENTRANCE_RING_SRC_LINK_ID_MASK 0x00070000 + +#define REO_ENTRANCE_RING_RESERVED_7A_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_RESERVED_7A_LSB 19 +#define REO_ENTRANCE_RING_RESERVED_7A_MSB 19 +#define REO_ENTRANCE_RING_RESERVED_7A_MASK 0x00080000 + +#define REO_ENTRANCE_RING_RING_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_RING_ID_LSB 20 +#define REO_ENTRANCE_RING_RING_ID_MSB 27 +#define REO_ENTRANCE_RING_RING_ID_MASK 0x0ff00000 + +#define REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_LOOPING_COUNT_LSB 28 +#define REO_ENTRANCE_RING_LOOPING_COUNT_MSB 31 +#define REO_ENTRANCE_RING_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/kiwi/v2/reo_flush_cache.h b/hw/kiwi/v2/reo_flush_cache.h new file mode 100644 index 000000000000..6bab2fd46b11 --- /dev/null +++ b/hw/kiwi/v2/reo_flush_cache.h @@ -0,0 +1,174 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_FLUSH_CACHE_H_ +#define _REO_FLUSH_CACHE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_CACHE 10 + +#define NUM_OF_QWORDS_REO_FLUSH_CACHE 5 + +struct reo_flush_cache { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_addr_31_0 : 32; + uint32_t flush_addr_39_32 : 8, + forward_all_mpdus_in_queue : 1, + release_cache_block_index : 1, + cache_block_resource_index : 2, + flush_without_invalidate : 1, + block_cache_usage_after_flush : 1, + flush_entire_cache : 1, + flush_queue_1k_desc : 1, + reserved_2b : 16; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t tlv64_padding : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_addr_31_0 : 32; + uint32_t reserved_2b : 16, + flush_queue_1k_desc : 1, + flush_entire_cache : 1, + block_cache_usage_after_flush : 1, + flush_without_invalidate : 1, + cache_block_resource_index : 2, + release_cache_block_index : 1, + forward_all_mpdus_in_queue : 1, + flush_addr_39_32 : 8; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t tlv64_padding : 32; +#endif +}; + +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff + +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 + +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 + +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_LSB 32 +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MSB 63 +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MASK 0xffffffff00000000 + +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_LSB 0 +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MSB 7 +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MASK 0x00000000000000ff + +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8 +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MSB 8 +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x0000000000000100 + +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_LSB 9 +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MSB 9 +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MASK 0x0000000000000200 + +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 10 +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 11 +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000c00 + +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_LSB 12 +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MSB 12 +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MASK 0x0000000000001000 + +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13 +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MSB 13 +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x0000000000002000 + +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_LSB 14 +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MSB 14 +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MASK 0x0000000000004000 + +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_LSB 15 +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MSB 15 +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MASK 0x0000000000008000 + +#define REO_FLUSH_CACHE_RESERVED_2B_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_RESERVED_2B_LSB 16 +#define REO_FLUSH_CACHE_RESERVED_2B_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_2B_MASK 0x00000000ffff0000 + +#define REO_FLUSH_CACHE_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_RESERVED_3A_LSB 32 +#define REO_FLUSH_CACHE_RESERVED_3A_MSB 63 +#define REO_FLUSH_CACHE_RESERVED_3A_MASK 0xffffffff00000000 + +#define REO_FLUSH_CACHE_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_FLUSH_CACHE_RESERVED_4A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_4A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_4A_MASK 0x00000000ffffffff + +#define REO_FLUSH_CACHE_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_FLUSH_CACHE_RESERVED_5A_LSB 32 +#define REO_FLUSH_CACHE_RESERVED_5A_MSB 63 +#define REO_FLUSH_CACHE_RESERVED_5A_MASK 0xffffffff00000000 + +#define REO_FLUSH_CACHE_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_FLUSH_CACHE_RESERVED_6A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_6A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_6A_MASK 0x00000000ffffffff + +#define REO_FLUSH_CACHE_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_FLUSH_CACHE_RESERVED_7A_LSB 32 +#define REO_FLUSH_CACHE_RESERVED_7A_MSB 63 +#define REO_FLUSH_CACHE_RESERVED_7A_MASK 0xffffffff00000000 + +#define REO_FLUSH_CACHE_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_FLUSH_CACHE_RESERVED_8A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_8A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_8A_MASK 0x00000000ffffffff + +#define REO_FLUSH_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020 +#define REO_FLUSH_CACHE_TLV64_PADDING_LSB 32 +#define REO_FLUSH_CACHE_TLV64_PADDING_MSB 63 +#define REO_FLUSH_CACHE_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/reo_flush_cache_status.h b/hw/kiwi/v2/reo_flush_cache_status.h new file mode 100644 index 000000000000..fd715d9b456d --- /dev/null +++ b/hw/kiwi/v2/reo_flush_cache_status.h @@ -0,0 +1,303 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_FLUSH_CACHE_STATUS_H_ +#define _REO_FLUSH_CACHE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 26 + +#define NUM_OF_QWORDS_REO_FLUSH_CACHE_STATUS 13 + +struct reo_flush_cache_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + block_error_details : 2, + reserved_2a : 5, + cache_controller_flush_status_hit : 1, + cache_controller_flush_status_desc_type : 3, + cache_controller_flush_status_client_id : 4, + cache_controller_flush_status_error : 2, + cache_controller_flush_count : 8, + flush_queue_1k_desc : 1, + reserved_2b : 5; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2b : 5, + flush_queue_1k_desc : 1, + cache_controller_flush_count : 8, + cache_controller_flush_status_error : 2, + cache_controller_flush_status_client_id : 4, + cache_controller_flush_status_desc_type : 3, + cache_controller_flush_status_hit : 1, + reserved_2a : 5, + block_error_details : 2, + error_detected : 1; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MSB 0 +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 + +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_LSB 1 +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MSB 2 +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MASK 0x0000000000000006 + +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_LSB 3 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MSB 7 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MASK 0x00000000000000f8 + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MSB 8 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x0000000000000100 + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MSB 11 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x0000000000000e00 + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MSB 15 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x000000000000f000 + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MSB 17 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x0000000000030000 + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MSB 25 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x0000000003fc0000 + +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_LSB 26 +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MSB 26 +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MASK 0x0000000004000000 + +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_LSB 27 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MASK 0x00000000f8000000 + +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 + +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 + +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 + +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 + +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 + +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 + +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 + +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 + +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 + +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 + +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 + +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MSB 59 +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 + +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_LSB 60 +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MSB 63 +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + +#endif diff --git a/hw/kiwi/v2/reo_flush_queue.h b/hw/kiwi/v2/reo_flush_queue.h new file mode 100644 index 000000000000..a56c85d18e43 --- /dev/null +++ b/hw/kiwi/v2/reo_flush_queue.h @@ -0,0 +1,139 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_FLUSH_QUEUE_H_ +#define _REO_FLUSH_QUEUE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 10 + +#define NUM_OF_QWORDS_REO_FLUSH_QUEUE 5 + +struct reo_flush_queue { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_desc_addr_31_0 : 32; + uint32_t flush_desc_addr_39_32 : 8, + block_desc_addr_usage_after_flush : 1, + block_resource_index : 2, + reserved_2a : 21; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t tlv64_padding : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_desc_addr_31_0 : 32; + uint32_t reserved_2a : 21, + block_resource_index : 2, + block_desc_addr_usage_after_flush : 1, + flush_desc_addr_39_32 : 8; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t tlv64_padding : 32; +#endif +}; + +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff + +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 + +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 + +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB 32 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB 63 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff00000000 + +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB 0 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB 7 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK 0x00000000000000ff + +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8 +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB 8 +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x0000000000000100 + +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB 9 +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB 10 +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000600 + +#define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_RESERVED_2A_LSB 11 +#define REO_FLUSH_QUEUE_RESERVED_2A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_2A_MASK 0x00000000fffff800 + +#define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_RESERVED_3A_LSB 32 +#define REO_FLUSH_QUEUE_RESERVED_3A_MSB 63 +#define REO_FLUSH_QUEUE_RESERVED_3A_MASK 0xffffffff00000000 + +#define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_FLUSH_QUEUE_RESERVED_4A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_4A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_4A_MASK 0x00000000ffffffff + +#define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_FLUSH_QUEUE_RESERVED_5A_LSB 32 +#define REO_FLUSH_QUEUE_RESERVED_5A_MSB 63 +#define REO_FLUSH_QUEUE_RESERVED_5A_MASK 0xffffffff00000000 + +#define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_FLUSH_QUEUE_RESERVED_6A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_6A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_6A_MASK 0x00000000ffffffff + +#define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_FLUSH_QUEUE_RESERVED_7A_LSB 32 +#define REO_FLUSH_QUEUE_RESERVED_7A_MSB 63 +#define REO_FLUSH_QUEUE_RESERVED_7A_MASK 0xffffffff00000000 + +#define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_FLUSH_QUEUE_RESERVED_8A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_8A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_8A_MASK 0x00000000ffffffff + +#define REO_FLUSH_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020 +#define REO_FLUSH_QUEUE_TLV64_PADDING_LSB 32 +#define REO_FLUSH_QUEUE_TLV64_PADDING_MSB 63 +#define REO_FLUSH_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/reo_flush_queue_status.h b/hw/kiwi/v2/reo_flush_queue_status.h new file mode 100644 index 000000000000..11531ce12ecd --- /dev/null +++ b/hw/kiwi/v2/reo_flush_queue_status.h @@ -0,0 +1,247 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_FLUSH_QUEUE_STATUS_H_ +#define _REO_FLUSH_QUEUE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 26 + +#define NUM_OF_QWORDS_REO_FLUSH_QUEUE_STATUS 13 + +struct reo_flush_queue_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + reserved_2a : 31; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 31, + error_detected : 1; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MSB 0 +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_LSB 1 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MASK 0x00000000fffffffe + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MSB 59 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 + +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_LSB 60 +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + +#endif diff --git a/hw/kiwi/v2/reo_flush_timeout_list.h b/hw/kiwi/v2/reo_flush_timeout_list.h new file mode 100644 index 000000000000..eea2e0c79a38 --- /dev/null +++ b/hw/kiwi/v2/reo_flush_timeout_list.h @@ -0,0 +1,132 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_FLUSH_TIMEOUT_LIST_H_ +#define _REO_FLUSH_TIMEOUT_LIST_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 10 + +#define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST 5 + +struct reo_flush_timeout_list { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t ac_timout_list : 2, + reserved_1 : 30; + uint32_t minimum_release_desc_count : 16, + minimum_forward_buf_count : 16; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t tlv64_padding : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t reserved_1 : 30, + ac_timout_list : 2; + uint32_t minimum_forward_buf_count : 16, + minimum_release_desc_count : 16; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t tlv64_padding : 32; +#endif +}; + +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff + +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 + +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 + +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MSB 33 +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MASK 0x0000000300000000 + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_LSB 34 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MASK 0xfffffffc00000000 + +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MSB 15 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MASK 0x000000000000ffff + +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MASK 0x00000000ffff0000 + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MASK 0xffffffff00000000 + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MASK 0x00000000ffffffff + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MASK 0xffffffff00000000 + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MASK 0x00000000ffffffff + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MASK 0xffffffff00000000 + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MASK 0x00000000ffffffff + +#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_OFFSET 0x0000000000000020 +#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/reo_flush_timeout_list_status.h b/hw/kiwi/v2/reo_flush_timeout_list_status.h new file mode 100644 index 000000000000..d5fb37fa11a6 --- /dev/null +++ b/hw/kiwi/v2/reo_flush_timeout_list_status.h @@ -0,0 +1,261 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ +#define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 26 + +#define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 13 + +struct reo_flush_timeout_list_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + timout_list_empty : 1, + reserved_2a : 30; + uint32_t release_desc_count : 16, + forward_buf_count : 16; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 30, + timout_list_empty : 1, + error_detected : 1; + uint32_t forward_buf_count : 16, + release_desc_count : 16; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_LSB 1 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MSB 1 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MASK 0x0000000000000002 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_LSB 2 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MASK 0x00000000fffffffc + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MSB 47 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MASK 0x0000ffff00000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_LSB 48 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MASK 0xffff000000000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MASK 0x00000000ffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MASK 0xffffffff00000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MASK 0x00000000ffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MASK 0xffffffff00000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MASK 0x00000000ffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MASK 0xffffffff00000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MASK 0x00000000ffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MASK 0xffffffff00000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MASK 0x00000000ffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MASK 0xffffffff00000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MASK 0x00000000ffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MASK 0xffffffff00000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MASK 0x00000000ffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MASK 0xffffffff00000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MASK 0x00000000ffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MASK 0xffffffff00000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MASK 0x00000000ffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MASK 0xffffffff00000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MASK 0x00000000ffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MASK 0xffffffff00000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MASK 0x00000000ffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MSB 59 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_LSB 60 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + +#endif diff --git a/hw/kiwi/v2/reo_get_queue_stats.h b/hw/kiwi/v2/reo_get_queue_stats.h new file mode 100644 index 000000000000..9315b2aa9762 --- /dev/null +++ b/hw/kiwi/v2/reo_get_queue_stats.h @@ -0,0 +1,132 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_GET_QUEUE_STATS_H_ +#define _REO_GET_QUEUE_STATS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 10 + +#define NUM_OF_QWORDS_REO_GET_QUEUE_STATS 5 + +struct reo_get_queue_stats { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + clear_stats : 1, + reserved_2a : 23; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t tlv64_padding : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t reserved_2a : 23, + clear_stats : 1, + rx_reo_queue_desc_addr_39_32 : 8; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t tlv64_padding : 32; +#endif +}; + +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff + +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 + +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 + +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000 + +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff + +#define REO_GET_QUEUE_STATS_CLEAR_STATS_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_CLEAR_STATS_LSB 8 +#define REO_GET_QUEUE_STATS_CLEAR_STATS_MSB 8 +#define REO_GET_QUEUE_STATS_CLEAR_STATS_MASK 0x0000000000000100 + +#define REO_GET_QUEUE_STATS_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_RESERVED_2A_LSB 9 +#define REO_GET_QUEUE_STATS_RESERVED_2A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_2A_MASK 0x00000000fffffe00 + +#define REO_GET_QUEUE_STATS_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_RESERVED_3A_LSB 32 +#define REO_GET_QUEUE_STATS_RESERVED_3A_MSB 63 +#define REO_GET_QUEUE_STATS_RESERVED_3A_MASK 0xffffffff00000000 + +#define REO_GET_QUEUE_STATS_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_GET_QUEUE_STATS_RESERVED_4A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_4A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_4A_MASK 0x00000000ffffffff + +#define REO_GET_QUEUE_STATS_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_GET_QUEUE_STATS_RESERVED_5A_LSB 32 +#define REO_GET_QUEUE_STATS_RESERVED_5A_MSB 63 +#define REO_GET_QUEUE_STATS_RESERVED_5A_MASK 0xffffffff00000000 + +#define REO_GET_QUEUE_STATS_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_GET_QUEUE_STATS_RESERVED_6A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_6A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_6A_MASK 0x00000000ffffffff + +#define REO_GET_QUEUE_STATS_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_GET_QUEUE_STATS_RESERVED_7A_LSB 32 +#define REO_GET_QUEUE_STATS_RESERVED_7A_MSB 63 +#define REO_GET_QUEUE_STATS_RESERVED_7A_MASK 0xffffffff00000000 + +#define REO_GET_QUEUE_STATS_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_GET_QUEUE_STATS_RESERVED_8A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_8A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_8A_MASK 0x00000000ffffffff + +#define REO_GET_QUEUE_STATS_TLV64_PADDING_OFFSET 0x0000000000000020 +#define REO_GET_QUEUE_STATS_TLV64_PADDING_LSB 32 +#define REO_GET_QUEUE_STATS_TLV64_PADDING_MSB 63 +#define REO_GET_QUEUE_STATS_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/reo_get_queue_stats_status.h b/hw/kiwi/v2/reo_get_queue_stats_status.h new file mode 100644 index 000000000000..95787d7621b5 --- /dev/null +++ b/hw/kiwi/v2/reo_get_queue_stats_status.h @@ -0,0 +1,324 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_GET_QUEUE_STATS_STATUS_H_ +#define _REO_GET_QUEUE_STATS_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS_STATUS 26 + +#define NUM_OF_QWORDS_REO_GET_QUEUE_STATS_STATUS 13 + +struct reo_get_queue_stats_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t ssn : 12, + current_index : 10, + reserved_2 : 10; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t last_rx_enqueue_timestamp : 32; + uint32_t last_rx_dequeue_timestamp : 32; + uint32_t rx_bitmap_31_0 : 32; + uint32_t rx_bitmap_63_32 : 32; + uint32_t rx_bitmap_95_64 : 32; + uint32_t rx_bitmap_127_96 : 32; + uint32_t rx_bitmap_159_128 : 32; + uint32_t rx_bitmap_191_160 : 32; + uint32_t rx_bitmap_223_192 : 32; + uint32_t rx_bitmap_255_224 : 32; + uint32_t rx_bitmap_287_256 : 32; + uint32_t current_mpdu_count : 7, + current_msdu_count : 25; + uint32_t window_jump_2k : 4, + timeout_count : 6, + forward_due_to_bar_count : 6, + duplicate_count : 16; + uint32_t frames_in_order_count : 24, + bar_received_count : 8; + uint32_t mpdu_frames_processed_count : 32; + uint32_t msdu_frames_processed_count : 32; + uint32_t total_processed_byte_count : 32; + uint32_t late_receive_mpdu_count : 12, + hole_count : 16, + get_queue_1k_stats_status_to_follow : 1, + reserved_24a : 3; + uint32_t aging_drop_mpdu_count : 16, + aging_drop_interval : 8, + reserved_25a : 4, + looping_count : 4; +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2 : 10, + current_index : 10, + ssn : 12; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t last_rx_enqueue_timestamp : 32; + uint32_t last_rx_dequeue_timestamp : 32; + uint32_t rx_bitmap_31_0 : 32; + uint32_t rx_bitmap_63_32 : 32; + uint32_t rx_bitmap_95_64 : 32; + uint32_t rx_bitmap_127_96 : 32; + uint32_t rx_bitmap_159_128 : 32; + uint32_t rx_bitmap_191_160 : 32; + uint32_t rx_bitmap_223_192 : 32; + uint32_t rx_bitmap_255_224 : 32; + uint32_t rx_bitmap_287_256 : 32; + uint32_t current_msdu_count : 25, + current_mpdu_count : 7; + uint32_t duplicate_count : 16, + forward_due_to_bar_count : 6, + timeout_count : 6, + window_jump_2k : 4; + uint32_t bar_received_count : 8, + frames_in_order_count : 24; + uint32_t mpdu_frames_processed_count : 32; + uint32_t msdu_frames_processed_count : 32; + uint32_t total_processed_byte_count : 32; + uint32_t reserved_24a : 3, + get_queue_1k_stats_status_to_follow : 1, + hole_count : 16, + late_receive_mpdu_count : 12; + uint32_t looping_count : 4, + reserved_25a : 4, + aging_drop_interval : 8, + aging_drop_mpdu_count : 16; +#endif +}; + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + +#define REO_GET_QUEUE_STATS_STATUS_SSN_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_STATUS_SSN_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_SSN_MSB 11 +#define REO_GET_QUEUE_STATS_STATUS_SSN_MASK 0x0000000000000fff + +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_LSB 12 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MSB 21 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MASK 0x00000000003ff000 + +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_LSB 22 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MASK 0x00000000ffc00000 + +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MASK 0xffffffff00000000 + +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_OFFSET 0x0000000000000010 +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MASK 0x00000000ffffffff + +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_OFFSET 0x0000000000000010 +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MASK 0xffffffff00000000 + +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_OFFSET 0x0000000000000018 +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MASK 0x00000000ffffffff + +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x0000000000000018 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff00000000 + +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x0000000000000020 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0x00000000ffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_OFFSET 0x0000000000000020 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MASK 0xffffffff00000000 + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_OFFSET 0x0000000000000028 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MASK 0x00000000ffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_OFFSET 0x0000000000000028 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MASK 0xffffffff00000000 + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_OFFSET 0x0000000000000030 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MASK 0x00000000ffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_OFFSET 0x0000000000000030 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MASK 0xffffffff00000000 + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_OFFSET 0x0000000000000038 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MASK 0x00000000ffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_OFFSET 0x0000000000000038 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MASK 0xffffffff00000000 + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_OFFSET 0x0000000000000040 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MASK 0x00000000ffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_OFFSET 0x0000000000000040 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MASK 0xffffffff00000000 + +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_OFFSET 0x0000000000000048 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MSB 6 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MASK 0x000000000000007f + +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_OFFSET 0x0000000000000048 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_LSB 7 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MASK 0x00000000ffffff80 + +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_OFFSET 0x0000000000000048 +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MSB 35 +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MASK 0x0000000f00000000 + +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_OFFSET 0x0000000000000048 +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_LSB 36 +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MSB 41 +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MASK 0x000003f000000000 + +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x0000000000000048 +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_LSB 42 +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MSB 47 +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc0000000000 + +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_OFFSET 0x0000000000000048 +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_LSB 48 +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MASK 0xffff000000000000 + +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_OFFSET 0x0000000000000050 +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MSB 23 +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MASK 0x0000000000ffffff + +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_OFFSET 0x0000000000000050 +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_LSB 24 +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MASK 0x00000000ff000000 + +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000000000000050 +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff00000000 + +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000000000000058 +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MASK 0x00000000ffffffff + +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x0000000000000058 +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff00000000 + +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MSB 11 +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MASK 0x0000000000000fff + +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_LSB 12 +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MSB 27 +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MASK 0x000000000ffff000 + +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MSB 28 +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MASK 0x0000000010000000 + +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_LSB 29 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MASK 0x00000000e0000000 + +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_MSB 47 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_MASK 0x0000ffff00000000 + +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_LSB 48 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_MSB 55 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_MASK 0x00ff000000000000 + +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_LSB 56 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MSB 59 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MASK 0x0f00000000000000 + +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_LSB 60 +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + +#endif diff --git a/hw/kiwi/v2/reo_unblock_cache.h b/hw/kiwi/v2/reo_unblock_cache.h new file mode 100644 index 000000000000..2a8197fd4b4b --- /dev/null +++ b/hw/kiwi/v2/reo_unblock_cache.h @@ -0,0 +1,132 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_UNBLOCK_CACHE_H_ +#define _REO_UNBLOCK_CACHE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 10 + +#define NUM_OF_QWORDS_REO_UNBLOCK_CACHE 5 + +struct reo_unblock_cache { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t unblock_type : 1, + cache_block_resource_index : 2, + reserved_1a : 29; + uint32_t reserved_2a : 32; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t tlv64_padding : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t reserved_1a : 29, + cache_block_resource_index : 2, + unblock_type : 1; + uint32_t reserved_2a : 32; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t tlv64_padding : 32; +#endif +}; + +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff + +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 + +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 + +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_LSB 32 +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MSB 32 +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MASK 0x0000000100000000 + +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 33 +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 34 +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000600000000 + +#define REO_UNBLOCK_CACHE_RESERVED_1A_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_RESERVED_1A_LSB 35 +#define REO_UNBLOCK_CACHE_RESERVED_1A_MSB 63 +#define REO_UNBLOCK_CACHE_RESERVED_1A_MASK 0xfffffff800000000 + +#define REO_UNBLOCK_CACHE_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_UNBLOCK_CACHE_RESERVED_2A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_2A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_2A_MASK 0x00000000ffffffff + +#define REO_UNBLOCK_CACHE_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_UNBLOCK_CACHE_RESERVED_3A_LSB 32 +#define REO_UNBLOCK_CACHE_RESERVED_3A_MSB 63 +#define REO_UNBLOCK_CACHE_RESERVED_3A_MASK 0xffffffff00000000 + +#define REO_UNBLOCK_CACHE_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_UNBLOCK_CACHE_RESERVED_4A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_4A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_4A_MASK 0x00000000ffffffff + +#define REO_UNBLOCK_CACHE_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_UNBLOCK_CACHE_RESERVED_5A_LSB 32 +#define REO_UNBLOCK_CACHE_RESERVED_5A_MSB 63 +#define REO_UNBLOCK_CACHE_RESERVED_5A_MASK 0xffffffff00000000 + +#define REO_UNBLOCK_CACHE_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_UNBLOCK_CACHE_RESERVED_6A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_6A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_6A_MASK 0x00000000ffffffff + +#define REO_UNBLOCK_CACHE_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_UNBLOCK_CACHE_RESERVED_7A_LSB 32 +#define REO_UNBLOCK_CACHE_RESERVED_7A_MSB 63 +#define REO_UNBLOCK_CACHE_RESERVED_7A_MASK 0xffffffff00000000 + +#define REO_UNBLOCK_CACHE_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_UNBLOCK_CACHE_RESERVED_8A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_8A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_8A_MASK 0x00000000ffffffff + +#define REO_UNBLOCK_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020 +#define REO_UNBLOCK_CACHE_TLV64_PADDING_LSB 32 +#define REO_UNBLOCK_CACHE_TLV64_PADDING_MSB 63 +#define REO_UNBLOCK_CACHE_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/reo_unblock_cache_status.h b/hw/kiwi/v2/reo_unblock_cache_status.h new file mode 100644 index 000000000000..d570cb5b722e --- /dev/null +++ b/hw/kiwi/v2/reo_unblock_cache_status.h @@ -0,0 +1,254 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_UNBLOCK_CACHE_STATUS_H_ +#define _REO_UNBLOCK_CACHE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 26 + +#define NUM_OF_QWORDS_REO_UNBLOCK_CACHE_STATUS 13 + +struct reo_unblock_cache_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + unblock_type : 1, + reserved_2a : 30; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 30, + unblock_type : 1, + error_detected : 1; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MSB 0 +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 + +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_OFFSET 0x0000000000000008 +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_LSB 1 +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MSB 1 +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MASK 0x0000000000000002 + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_LSB 2 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MASK 0x00000000fffffffc + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MSB 59 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 + +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_LSB 60 +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + +#endif diff --git a/hw/kiwi/v2/reo_update_rx_reo_queue.h b/hw/kiwi/v2/reo_update_rx_reo_queue.h new file mode 100644 index 000000000000..e6d2cf54beb5 --- /dev/null +++ b/hw/kiwi/v2/reo_update_rx_reo_queue.h @@ -0,0 +1,440 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_UPDATE_RX_REO_QUEUE_H_ +#define _REO_UPDATE_RX_REO_QUEUE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 10 + +#define NUM_OF_QWORDS_REO_UPDATE_RX_REO_QUEUE 5 + +struct reo_update_rx_reo_queue { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + update_receive_queue_number : 1, + update_vld : 1, + update_associated_link_descriptor_counter : 1, + update_disable_duplicate_detection : 1, + update_soft_reorder_enable : 1, + update_ac : 1, + update_bar : 1, + update_rty : 1, + update_chk_2k_mode : 1, + update_oor_mode : 1, + update_ba_window_size : 1, + update_pn_check_needed : 1, + update_pn_shall_be_even : 1, + update_pn_shall_be_uneven : 1, + update_pn_handling_enable : 1, + update_pn_size : 1, + update_ignore_ampdu_flag : 1, + update_svld : 1, + update_ssn : 1, + update_seq_2k_error_detected_flag : 1, + update_pn_error_detected_flag : 1, + update_pn_valid : 1, + update_pn : 1, + clear_stat_counters : 1; + uint32_t receive_queue_number : 16, + vld : 1, + associated_link_descriptor_counter : 2, + disable_duplicate_detection : 1, + soft_reorder_enable : 1, + ac : 2, + bar : 1, + rty : 1, + chk_2k_mode : 1, + oor_mode : 1, + pn_check_needed : 1, + pn_shall_be_even : 1, + pn_shall_be_uneven : 1, + pn_handling_enable : 1, + ignore_ampdu_flag : 1; + uint32_t ba_window_size : 10, + pn_size : 2, + svld : 1, + ssn : 12, + seq_2k_error_detected_flag : 1, + pn_error_detected_flag : 1, + pn_valid : 1, + flush_from_cache : 1, + reserved_4a : 3; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t tlv64_padding : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t clear_stat_counters : 1, + update_pn : 1, + update_pn_valid : 1, + update_pn_error_detected_flag : 1, + update_seq_2k_error_detected_flag : 1, + update_ssn : 1, + update_svld : 1, + update_ignore_ampdu_flag : 1, + update_pn_size : 1, + update_pn_handling_enable : 1, + update_pn_shall_be_uneven : 1, + update_pn_shall_be_even : 1, + update_pn_check_needed : 1, + update_ba_window_size : 1, + update_oor_mode : 1, + update_chk_2k_mode : 1, + update_rty : 1, + update_bar : 1, + update_ac : 1, + update_soft_reorder_enable : 1, + update_disable_duplicate_detection : 1, + update_associated_link_descriptor_counter : 1, + update_vld : 1, + update_receive_queue_number : 1, + rx_reo_queue_desc_addr_39_32 : 8; + uint32_t ignore_ampdu_flag : 1, + pn_handling_enable : 1, + pn_shall_be_uneven : 1, + pn_shall_be_even : 1, + pn_check_needed : 1, + oor_mode : 1, + chk_2k_mode : 1, + rty : 1, + bar : 1, + ac : 2, + soft_reorder_enable : 1, + disable_duplicate_detection : 1, + associated_link_descriptor_counter : 2, + vld : 1, + receive_queue_number : 16; + uint32_t reserved_4a : 3, + flush_from_cache : 1, + pn_valid : 1, + pn_error_detected_flag : 1, + seq_2k_error_detected_flag : 1, + ssn : 12, + svld : 1, + pn_size : 2, + ba_window_size : 10; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t tlv64_padding : 32; +#endif +}; + +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff + +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 + +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 + +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000 + +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_LSB 8 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MSB 8 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MASK 0x0000000000000100 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_LSB 9 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MSB 9 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MASK 0x0000000000000200 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 10 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x0000000000000400 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MSB 11 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x0000000000000800 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_LSB 12 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MSB 12 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MASK 0x0000000000001000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_LSB 13 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MSB 13 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MASK 0x0000000000002000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_LSB 14 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MSB 14 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MASK 0x0000000000004000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_LSB 15 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MSB 15 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MASK 0x0000000000008000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MSB 16 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MASK 0x0000000000010000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MSB 17 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MASK 0x0000000000020000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_LSB 18 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MSB 18 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MASK 0x0000000000040000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_LSB 19 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MSB 19 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MASK 0x0000000000080000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_LSB 20 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MSB 20 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MASK 0x0000000000100000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_LSB 21 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MSB 21 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MASK 0x0000000000200000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_LSB 22 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MSB 22 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MASK 0x0000000000400000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_LSB 23 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MSB 23 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MASK 0x0000000000800000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_LSB 24 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MSB 24 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MASK 0x0000000001000000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MSB 25 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MASK 0x0000000002000000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MSB 26 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MASK 0x0000000004000000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 27 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x0000000008000000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MSB 28 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x0000000010000000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_LSB 29 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MSB 29 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MASK 0x0000000020000000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_LSB 30 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MSB 30 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MASK 0x0000000040000000 + +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_LSB 31 +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MASK 0x0000000080000000 + +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 47 +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff00000000 + +#define REO_UPDATE_RX_REO_QUEUE_VLD_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_VLD_LSB 48 +#define REO_UPDATE_RX_REO_QUEUE_VLD_MSB 48 +#define REO_UPDATE_RX_REO_QUEUE_VLD_MASK 0x0001000000000000 + +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 49 +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 50 +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x0006000000000000 + +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 51 +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 51 +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x0008000000000000 + +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 52 +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 52 +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x0010000000000000 + +#define REO_UPDATE_RX_REO_QUEUE_AC_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_AC_LSB 53 +#define REO_UPDATE_RX_REO_QUEUE_AC_MSB 54 +#define REO_UPDATE_RX_REO_QUEUE_AC_MASK 0x0060000000000000 + +#define REO_UPDATE_RX_REO_QUEUE_BAR_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_BAR_LSB 55 +#define REO_UPDATE_RX_REO_QUEUE_BAR_MSB 55 +#define REO_UPDATE_RX_REO_QUEUE_BAR_MASK 0x0080000000000000 + +#define REO_UPDATE_RX_REO_QUEUE_RTY_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_RTY_LSB 56 +#define REO_UPDATE_RX_REO_QUEUE_RTY_MSB 56 +#define REO_UPDATE_RX_REO_QUEUE_RTY_MASK 0x0100000000000000 + +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_LSB 57 +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MSB 57 +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MASK 0x0200000000000000 + +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_LSB 58 +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MSB 58 +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MASK 0x0400000000000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 59 +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 59 +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x0800000000000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 60 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 60 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x1000000000000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 61 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 61 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x2000000000000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 62 +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 62 +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x4000000000000000 + +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 63 +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x8000000000000000 + +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 9 +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x00000000000003ff + +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_LSB 10 +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MSB 11 +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MASK 0x0000000000000c00 + +#define REO_UPDATE_RX_REO_QUEUE_SVLD_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_SVLD_LSB 12 +#define REO_UPDATE_RX_REO_QUEUE_SVLD_MSB 12 +#define REO_UPDATE_RX_REO_QUEUE_SVLD_MASK 0x0000000000001000 + +#define REO_UPDATE_RX_REO_QUEUE_SSN_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_SSN_LSB 13 +#define REO_UPDATE_RX_REO_QUEUE_SSN_MSB 24 +#define REO_UPDATE_RX_REO_QUEUE_SSN_MASK 0x0000000001ffe000 + +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 25 +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x0000000002000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 26 +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x0000000004000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MSB 27 +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MASK 0x0000000008000000 + +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MSB 28 +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MASK 0x0000000010000000 + +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_LSB 29 +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MASK 0x00000000e0000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MASK 0xffffffff00000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_OFFSET 0x0000000000000018 +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MASK 0x00000000ffffffff + +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_OFFSET 0x0000000000000018 +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MASK 0xffffffff00000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_OFFSET 0x0000000000000020 +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MASK 0x00000000ffffffff + +#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020 +#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/reo_update_rx_reo_queue_status.h b/hw/kiwi/v2/reo_update_rx_reo_queue_status.h new file mode 100644 index 000000000000..af37001ac923 --- /dev/null +++ b/hw/kiwi/v2/reo_update_rx_reo_queue_status.h @@ -0,0 +1,240 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ +#define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 26 + +#define NUM_OF_QWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 13 + +struct reo_update_rx_reo_queue_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 32; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 32; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MASK 0x00000000ffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MSB 59 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_LSB 60 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + +#endif diff --git a/hw/kiwi/v2/rx_attention.h b/hw/kiwi/v2/rx_attention.h new file mode 100644 index 000000000000..991b308959df --- /dev/null +++ b/hw/kiwi/v2/rx_attention.h @@ -0,0 +1,394 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_ATTENTION_H_ +#define _RX_ATTENTION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_ATTENTION 4 + +#define NUM_OF_QWORDS_RX_ATTENTION 2 + +struct rx_attention { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t first_mpdu : 1, + reserved_1a : 1, + mcast_bcast : 1, + ast_index_not_found : 1, + ast_index_timeout : 1, + power_mgmt : 1, + non_qos : 1, + null_data : 1, + mgmt_type : 1, + ctrl_type : 1, + more_data : 1, + eosp : 1, + a_msdu_error : 1, + fragment_flag : 1, + order : 1, + cce_match : 1, + overflow_err : 1, + msdu_length_err : 1, + tcp_udp_chksum_fail : 1, + ip_chksum_fail : 1, + sa_idx_invalid : 1, + da_idx_invalid : 1, + reserved_1b : 1, + rx_in_tx_decrypt_byp : 1, + encrypt_required : 1, + directed : 1, + buffer_fragment : 1, + mpdu_length_err : 1, + tkip_mic_err : 1, + decrypt_err : 1, + unencrypted_frame_err : 1, + fcs_err : 1; + uint32_t flow_idx_timeout : 1, + flow_idx_invalid : 1, + wifi_parser_error : 1, + amsdu_parser_error : 1, + sa_idx_timeout : 1, + da_idx_timeout : 1, + msdu_limit_error : 1, + da_is_valid : 1, + da_is_mcbc : 1, + sa_is_valid : 1, + decrypt_status_code : 3, + rx_bitmap_not_updated : 1, + reserved_2 : 17, + msdu_done : 1; + uint32_t tlv64_padding : 32; +#else + uint32_t phy_ppdu_id : 16, + reserved_0 : 7, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t fcs_err : 1, + unencrypted_frame_err : 1, + decrypt_err : 1, + tkip_mic_err : 1, + mpdu_length_err : 1, + buffer_fragment : 1, + directed : 1, + encrypt_required : 1, + rx_in_tx_decrypt_byp : 1, + reserved_1b : 1, + da_idx_invalid : 1, + sa_idx_invalid : 1, + ip_chksum_fail : 1, + tcp_udp_chksum_fail : 1, + msdu_length_err : 1, + overflow_err : 1, + cce_match : 1, + order : 1, + fragment_flag : 1, + a_msdu_error : 1, + eosp : 1, + more_data : 1, + ctrl_type : 1, + mgmt_type : 1, + null_data : 1, + non_qos : 1, + power_mgmt : 1, + ast_index_timeout : 1, + ast_index_not_found : 1, + mcast_bcast : 1, + reserved_1a : 1, + first_mpdu : 1; + uint32_t msdu_done : 1, + reserved_2 : 17, + rx_bitmap_not_updated : 1, + decrypt_status_code : 3, + sa_is_valid : 1, + da_is_mcbc : 1, + da_is_valid : 1, + msdu_limit_error : 1, + da_idx_timeout : 1, + sa_idx_timeout : 1, + amsdu_parser_error : 1, + wifi_parser_error : 1, + flow_idx_invalid : 1, + flow_idx_timeout : 1; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 + +#define RX_ATTENTION_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 +#define RX_ATTENTION_SW_FRAME_GROUP_ID_LSB 2 +#define RX_ATTENTION_SW_FRAME_GROUP_ID_MSB 8 +#define RX_ATTENTION_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc + +#define RX_ATTENTION_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_ATTENTION_RESERVED_0_LSB 9 +#define RX_ATTENTION_RESERVED_0_MSB 15 +#define RX_ATTENTION_RESERVED_0_MASK 0x000000000000fe00 + +#define RX_ATTENTION_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_ATTENTION_PHY_PPDU_ID_LSB 16 +#define RX_ATTENTION_PHY_PPDU_ID_MSB 31 +#define RX_ATTENTION_PHY_PPDU_ID_MASK 0x00000000ffff0000 + +#define RX_ATTENTION_FIRST_MPDU_OFFSET 0x0000000000000000 +#define RX_ATTENTION_FIRST_MPDU_LSB 32 +#define RX_ATTENTION_FIRST_MPDU_MSB 32 +#define RX_ATTENTION_FIRST_MPDU_MASK 0x0000000100000000 + +#define RX_ATTENTION_RESERVED_1A_OFFSET 0x0000000000000000 +#define RX_ATTENTION_RESERVED_1A_LSB 33 +#define RX_ATTENTION_RESERVED_1A_MSB 33 +#define RX_ATTENTION_RESERVED_1A_MASK 0x0000000200000000 + +#define RX_ATTENTION_MCAST_BCAST_OFFSET 0x0000000000000000 +#define RX_ATTENTION_MCAST_BCAST_LSB 34 +#define RX_ATTENTION_MCAST_BCAST_MSB 34 +#define RX_ATTENTION_MCAST_BCAST_MASK 0x0000000400000000 + +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000000 +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_LSB 35 +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MSB 35 +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MASK 0x0000000800000000 + +#define RX_ATTENTION_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000000 +#define RX_ATTENTION_AST_INDEX_TIMEOUT_LSB 36 +#define RX_ATTENTION_AST_INDEX_TIMEOUT_MSB 36 +#define RX_ATTENTION_AST_INDEX_TIMEOUT_MASK 0x0000001000000000 + +#define RX_ATTENTION_POWER_MGMT_OFFSET 0x0000000000000000 +#define RX_ATTENTION_POWER_MGMT_LSB 37 +#define RX_ATTENTION_POWER_MGMT_MSB 37 +#define RX_ATTENTION_POWER_MGMT_MASK 0x0000002000000000 + +#define RX_ATTENTION_NON_QOS_OFFSET 0x0000000000000000 +#define RX_ATTENTION_NON_QOS_LSB 38 +#define RX_ATTENTION_NON_QOS_MSB 38 +#define RX_ATTENTION_NON_QOS_MASK 0x0000004000000000 + +#define RX_ATTENTION_NULL_DATA_OFFSET 0x0000000000000000 +#define RX_ATTENTION_NULL_DATA_LSB 39 +#define RX_ATTENTION_NULL_DATA_MSB 39 +#define RX_ATTENTION_NULL_DATA_MASK 0x0000008000000000 + +#define RX_ATTENTION_MGMT_TYPE_OFFSET 0x0000000000000000 +#define RX_ATTENTION_MGMT_TYPE_LSB 40 +#define RX_ATTENTION_MGMT_TYPE_MSB 40 +#define RX_ATTENTION_MGMT_TYPE_MASK 0x0000010000000000 + +#define RX_ATTENTION_CTRL_TYPE_OFFSET 0x0000000000000000 +#define RX_ATTENTION_CTRL_TYPE_LSB 41 +#define RX_ATTENTION_CTRL_TYPE_MSB 41 +#define RX_ATTENTION_CTRL_TYPE_MASK 0x0000020000000000 + +#define RX_ATTENTION_MORE_DATA_OFFSET 0x0000000000000000 +#define RX_ATTENTION_MORE_DATA_LSB 42 +#define RX_ATTENTION_MORE_DATA_MSB 42 +#define RX_ATTENTION_MORE_DATA_MASK 0x0000040000000000 + +#define RX_ATTENTION_EOSP_OFFSET 0x0000000000000000 +#define RX_ATTENTION_EOSP_LSB 43 +#define RX_ATTENTION_EOSP_MSB 43 +#define RX_ATTENTION_EOSP_MASK 0x0000080000000000 + +#define RX_ATTENTION_A_MSDU_ERROR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_A_MSDU_ERROR_LSB 44 +#define RX_ATTENTION_A_MSDU_ERROR_MSB 44 +#define RX_ATTENTION_A_MSDU_ERROR_MASK 0x0000100000000000 + +#define RX_ATTENTION_FRAGMENT_FLAG_OFFSET 0x0000000000000000 +#define RX_ATTENTION_FRAGMENT_FLAG_LSB 45 +#define RX_ATTENTION_FRAGMENT_FLAG_MSB 45 +#define RX_ATTENTION_FRAGMENT_FLAG_MASK 0x0000200000000000 + +#define RX_ATTENTION_ORDER_OFFSET 0x0000000000000000 +#define RX_ATTENTION_ORDER_LSB 46 +#define RX_ATTENTION_ORDER_MSB 46 +#define RX_ATTENTION_ORDER_MASK 0x0000400000000000 + +#define RX_ATTENTION_CCE_MATCH_OFFSET 0x0000000000000000 +#define RX_ATTENTION_CCE_MATCH_LSB 47 +#define RX_ATTENTION_CCE_MATCH_MSB 47 +#define RX_ATTENTION_CCE_MATCH_MASK 0x0000800000000000 + +#define RX_ATTENTION_OVERFLOW_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_OVERFLOW_ERR_LSB 48 +#define RX_ATTENTION_OVERFLOW_ERR_MSB 48 +#define RX_ATTENTION_OVERFLOW_ERR_MASK 0x0001000000000000 + +#define RX_ATTENTION_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_MSDU_LENGTH_ERR_LSB 49 +#define RX_ATTENTION_MSDU_LENGTH_ERR_MSB 49 +#define RX_ATTENTION_MSDU_LENGTH_ERR_MASK 0x0002000000000000 + +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000000 +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_LSB 50 +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MSB 50 +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MASK 0x0004000000000000 + +#define RX_ATTENTION_IP_CHKSUM_FAIL_OFFSET 0x0000000000000000 +#define RX_ATTENTION_IP_CHKSUM_FAIL_LSB 51 +#define RX_ATTENTION_IP_CHKSUM_FAIL_MSB 51 +#define RX_ATTENTION_IP_CHKSUM_FAIL_MASK 0x0008000000000000 + +#define RX_ATTENTION_SA_IDX_INVALID_OFFSET 0x0000000000000000 +#define RX_ATTENTION_SA_IDX_INVALID_LSB 52 +#define RX_ATTENTION_SA_IDX_INVALID_MSB 52 +#define RX_ATTENTION_SA_IDX_INVALID_MASK 0x0010000000000000 + +#define RX_ATTENTION_DA_IDX_INVALID_OFFSET 0x0000000000000000 +#define RX_ATTENTION_DA_IDX_INVALID_LSB 53 +#define RX_ATTENTION_DA_IDX_INVALID_MSB 53 +#define RX_ATTENTION_DA_IDX_INVALID_MASK 0x0020000000000000 + +#define RX_ATTENTION_RESERVED_1B_OFFSET 0x0000000000000000 +#define RX_ATTENTION_RESERVED_1B_LSB 54 +#define RX_ATTENTION_RESERVED_1B_MSB 54 +#define RX_ATTENTION_RESERVED_1B_MASK 0x0040000000000000 + +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_LSB 55 +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MSB 55 +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MASK 0x0080000000000000 + +#define RX_ATTENTION_ENCRYPT_REQUIRED_OFFSET 0x0000000000000000 +#define RX_ATTENTION_ENCRYPT_REQUIRED_LSB 56 +#define RX_ATTENTION_ENCRYPT_REQUIRED_MSB 56 +#define RX_ATTENTION_ENCRYPT_REQUIRED_MASK 0x0100000000000000 + +#define RX_ATTENTION_DIRECTED_OFFSET 0x0000000000000000 +#define RX_ATTENTION_DIRECTED_LSB 57 +#define RX_ATTENTION_DIRECTED_MSB 57 +#define RX_ATTENTION_DIRECTED_MASK 0x0200000000000000 + +#define RX_ATTENTION_BUFFER_FRAGMENT_OFFSET 0x0000000000000000 +#define RX_ATTENTION_BUFFER_FRAGMENT_LSB 58 +#define RX_ATTENTION_BUFFER_FRAGMENT_MSB 58 +#define RX_ATTENTION_BUFFER_FRAGMENT_MASK 0x0400000000000000 + +#define RX_ATTENTION_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_MPDU_LENGTH_ERR_LSB 59 +#define RX_ATTENTION_MPDU_LENGTH_ERR_MSB 59 +#define RX_ATTENTION_MPDU_LENGTH_ERR_MASK 0x0800000000000000 + +#define RX_ATTENTION_TKIP_MIC_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_TKIP_MIC_ERR_LSB 60 +#define RX_ATTENTION_TKIP_MIC_ERR_MSB 60 +#define RX_ATTENTION_TKIP_MIC_ERR_MASK 0x1000000000000000 + +#define RX_ATTENTION_DECRYPT_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_DECRYPT_ERR_LSB 61 +#define RX_ATTENTION_DECRYPT_ERR_MSB 61 +#define RX_ATTENTION_DECRYPT_ERR_MASK 0x2000000000000000 + +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_LSB 62 +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MSB 62 +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MASK 0x4000000000000000 + +#define RX_ATTENTION_FCS_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_FCS_ERR_LSB 63 +#define RX_ATTENTION_FCS_ERR_MSB 63 +#define RX_ATTENTION_FCS_ERR_MASK 0x8000000000000000 + +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000008 +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_LSB 0 +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MSB 0 +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MASK 0x0000000000000001 + +#define RX_ATTENTION_FLOW_IDX_INVALID_OFFSET 0x0000000000000008 +#define RX_ATTENTION_FLOW_IDX_INVALID_LSB 1 +#define RX_ATTENTION_FLOW_IDX_INVALID_MSB 1 +#define RX_ATTENTION_FLOW_IDX_INVALID_MASK 0x0000000000000002 + +#define RX_ATTENTION_WIFI_PARSER_ERROR_OFFSET 0x0000000000000008 +#define RX_ATTENTION_WIFI_PARSER_ERROR_LSB 2 +#define RX_ATTENTION_WIFI_PARSER_ERROR_MSB 2 +#define RX_ATTENTION_WIFI_PARSER_ERROR_MASK 0x0000000000000004 + +#define RX_ATTENTION_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000008 +#define RX_ATTENTION_AMSDU_PARSER_ERROR_LSB 3 +#define RX_ATTENTION_AMSDU_PARSER_ERROR_MSB 3 +#define RX_ATTENTION_AMSDU_PARSER_ERROR_MASK 0x0000000000000008 + +#define RX_ATTENTION_SA_IDX_TIMEOUT_OFFSET 0x0000000000000008 +#define RX_ATTENTION_SA_IDX_TIMEOUT_LSB 4 +#define RX_ATTENTION_SA_IDX_TIMEOUT_MSB 4 +#define RX_ATTENTION_SA_IDX_TIMEOUT_MASK 0x0000000000000010 + +#define RX_ATTENTION_DA_IDX_TIMEOUT_OFFSET 0x0000000000000008 +#define RX_ATTENTION_DA_IDX_TIMEOUT_LSB 5 +#define RX_ATTENTION_DA_IDX_TIMEOUT_MSB 5 +#define RX_ATTENTION_DA_IDX_TIMEOUT_MASK 0x0000000000000020 + +#define RX_ATTENTION_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000008 +#define RX_ATTENTION_MSDU_LIMIT_ERROR_LSB 6 +#define RX_ATTENTION_MSDU_LIMIT_ERROR_MSB 6 +#define RX_ATTENTION_MSDU_LIMIT_ERROR_MASK 0x0000000000000040 + +#define RX_ATTENTION_DA_IS_VALID_OFFSET 0x0000000000000008 +#define RX_ATTENTION_DA_IS_VALID_LSB 7 +#define RX_ATTENTION_DA_IS_VALID_MSB 7 +#define RX_ATTENTION_DA_IS_VALID_MASK 0x0000000000000080 + +#define RX_ATTENTION_DA_IS_MCBC_OFFSET 0x0000000000000008 +#define RX_ATTENTION_DA_IS_MCBC_LSB 8 +#define RX_ATTENTION_DA_IS_MCBC_MSB 8 +#define RX_ATTENTION_DA_IS_MCBC_MASK 0x0000000000000100 + +#define RX_ATTENTION_SA_IS_VALID_OFFSET 0x0000000000000008 +#define RX_ATTENTION_SA_IS_VALID_LSB 9 +#define RX_ATTENTION_SA_IS_VALID_MSB 9 +#define RX_ATTENTION_SA_IS_VALID_MASK 0x0000000000000200 + +#define RX_ATTENTION_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000008 +#define RX_ATTENTION_DECRYPT_STATUS_CODE_LSB 10 +#define RX_ATTENTION_DECRYPT_STATUS_CODE_MSB 12 +#define RX_ATTENTION_DECRYPT_STATUS_CODE_MASK 0x0000000000001c00 + +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000008 +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_LSB 13 +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MSB 13 +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MASK 0x0000000000002000 + +#define RX_ATTENTION_RESERVED_2_OFFSET 0x0000000000000008 +#define RX_ATTENTION_RESERVED_2_LSB 14 +#define RX_ATTENTION_RESERVED_2_MSB 30 +#define RX_ATTENTION_RESERVED_2_MASK 0x000000007fffc000 + +#define RX_ATTENTION_MSDU_DONE_OFFSET 0x0000000000000008 +#define RX_ATTENTION_MSDU_DONE_LSB 31 +#define RX_ATTENTION_MSDU_DONE_MSB 31 +#define RX_ATTENTION_MSDU_DONE_MASK 0x0000000080000000 + +#define RX_ATTENTION_TLV64_PADDING_OFFSET 0x0000000000000008 +#define RX_ATTENTION_TLV64_PADDING_LSB 32 +#define RX_ATTENTION_TLV64_PADDING_MSB 63 +#define RX_ATTENTION_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/rx_flow_search_entry.h b/hw/kiwi/v2/rx_flow_search_entry.h new file mode 100644 index 000000000000..b2fabc9cee42 --- /dev/null +++ b/hw/kiwi/v2/rx_flow_search_entry.h @@ -0,0 +1,231 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_FLOW_SEARCH_ENTRY_H_ +#define _RX_FLOW_SEARCH_ENTRY_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16 + +struct rx_flow_search_entry { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t src_ip_127_96 : 32; + uint32_t src_ip_95_64 : 32; + uint32_t src_ip_63_32 : 32; + uint32_t src_ip_31_0 : 32; + uint32_t dest_ip_127_96 : 32; + uint32_t dest_ip_95_64 : 32; + uint32_t dest_ip_63_32 : 32; + uint32_t dest_ip_31_0 : 32; + uint32_t src_port : 16, + dest_port : 16; + uint32_t l4_protocol : 8, + valid : 1, + reserved_9 : 4, + service_code : 9, + priority_valid : 1, + use_ppe : 1, + reo_destination_indication : 5, + msdu_drop : 1, + reo_destination_handler : 2; + uint32_t metadata : 32; + uint32_t aggregation_count : 7, + lro_eligible : 1, + msdu_count : 24; + uint32_t msdu_byte_count : 32; + uint32_t timestamp : 32; + uint32_t cumulative_ip_length_pmac1 : 16, + cumulative_ip_length : 16; + uint32_t tcp_sequence_number : 32; +#else + uint32_t src_ip_127_96 : 32; + uint32_t src_ip_95_64 : 32; + uint32_t src_ip_63_32 : 32; + uint32_t src_ip_31_0 : 32; + uint32_t dest_ip_127_96 : 32; + uint32_t dest_ip_95_64 : 32; + uint32_t dest_ip_63_32 : 32; + uint32_t dest_ip_31_0 : 32; + uint32_t dest_port : 16, + src_port : 16; + uint32_t reo_destination_handler : 2, + msdu_drop : 1, + reo_destination_indication : 5, + use_ppe : 1, + priority_valid : 1, + service_code : 9, + reserved_9 : 4, + valid : 1, + l4_protocol : 8; + uint32_t metadata : 32; + uint32_t msdu_count : 24, + lro_eligible : 1, + aggregation_count : 7; + uint32_t msdu_byte_count : 32; + uint32_t timestamp : 32; + uint32_t cumulative_ip_length : 16, + cumulative_ip_length_pmac1 : 16; + uint32_t tcp_sequence_number : 32; +#endif +}; + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_OFFSET 0x00000000 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_OFFSET 0x00000004 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_OFFSET 0x00000008 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_OFFSET 0x0000000c +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_OFFSET 0x00000010 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_OFFSET 0x00000014 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_OFFSET 0x00000018 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_OFFSET 0x0000001c +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_OFFSET 0x00000020 +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MSB 15 +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MASK 0x0000ffff + +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_OFFSET 0x00000020 +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_LSB 16 +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MASK 0xffff0000 + +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MSB 7 +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MASK 0x000000ff + +#define RX_FLOW_SEARCH_ENTRY_VALID_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_VALID_LSB 8 +#define RX_FLOW_SEARCH_ENTRY_VALID_MSB 8 +#define RX_FLOW_SEARCH_ENTRY_VALID_MASK 0x00000100 + +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_LSB 9 +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MSB 12 +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MASK 0x00001e00 + +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_LSB 13 +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MSB 21 +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MASK 0x003fe000 + +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_LSB 22 +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MSB 22 +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MASK 0x00400000 + +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_LSB 23 +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MSB 23 +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MASK 0x00800000 + +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_LSB 24 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MSB 28 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MASK 0x1f000000 + +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_LSB 29 +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MSB 29 +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MASK 0x20000000 + +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_LSB 30 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MASK 0xc0000000 + +#define RX_FLOW_SEARCH_ENTRY_METADATA_OFFSET 0x00000028 +#define RX_FLOW_SEARCH_ENTRY_METADATA_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_METADATA_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_METADATA_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MSB 6 +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MASK 0x0000007f + +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_LSB 7 +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MSB 7 +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MASK 0x00000080 + +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_LSB 8 +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MASK 0xffffff00 + +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_OFFSET 0x00000030 +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_OFFSET 0x00000034 +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_OFFSET 0x00000038 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MSB 15 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MASK 0x0000ffff + +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_LSB 16 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 + +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MASK 0xffffffff + +#endif diff --git a/hw/kiwi/v2/rx_location_info.h b/hw/kiwi/v2/rx_location_info.h new file mode 100644 index 000000000000..61b95b5adb20 --- /dev/null +++ b/hw/kiwi/v2/rx_location_info.h @@ -0,0 +1,476 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_LOCATION_INFO_H_ +#define _RX_LOCATION_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_LOCATION_INFO 28 + +struct rx_location_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rx_location_info_valid : 1, + rtt_hw_ifft_mode : 1, + rtt_11az_mode : 2, + reserved_0 : 4, + rtt_num_fac : 8, + rtt_rx_chain_mask : 8, + rtt_num_streams : 8; + uint32_t rtt_first_selected_chain : 8, + rtt_second_selected_chain : 8, + rtt_cfr_status : 8, + rtt_cir_status : 8; + uint32_t rtt_che_buffer_pointer_low32 : 32; + uint32_t rtt_che_buffer_pointer_high8 : 8, + reserved_3 : 8, + rtt_pkt_bw_vht : 4, + rtt_pkt_bw_leg : 4, + rtt_mcs_rate : 8; + uint32_t rtt_cfo_measurement : 16, + rtt_preamble_type : 8, + rtt_gi_type : 8; + uint32_t rx_start_ts : 32; + uint32_t rx_start_ts_upper : 32; + uint32_t rx_end_ts : 32; + uint32_t gain_chain0 : 16, + gain_chain1 : 16; + uint32_t gain_chain2 : 16, + gain_chain3 : 16; + uint32_t gain_report_status : 8, + rtt_timing_backoff_sel : 8, + rtt_fac_combined : 16; + uint32_t rtt_fac_0 : 16, + rtt_fac_1 : 16; + uint32_t rtt_fac_2 : 16, + rtt_fac_3 : 16; + uint32_t rtt_fac_4 : 16, + rtt_fac_5 : 16; + uint32_t rtt_fac_6 : 16, + rtt_fac_7 : 16; + uint32_t rtt_fac_8 : 16, + rtt_fac_9 : 16; + uint32_t rtt_fac_10 : 16, + rtt_fac_11 : 16; + uint32_t rtt_fac_12 : 16, + rtt_fac_13 : 16; + uint32_t rtt_fac_14 : 16, + rtt_fac_15 : 16; + uint32_t rtt_fac_16 : 16, + rtt_fac_17 : 16; + uint32_t rtt_fac_18 : 16, + rtt_fac_19 : 16; + uint32_t rtt_fac_20 : 16, + rtt_fac_21 : 16; + uint32_t rtt_fac_22 : 16, + rtt_fac_23 : 16; + uint32_t rtt_fac_24 : 16, + rtt_fac_25 : 16; + uint32_t rtt_fac_26 : 16, + rtt_fac_27 : 16; + uint32_t rtt_fac_28 : 16, + rtt_fac_29 : 16; + uint32_t rtt_fac_30 : 16, + rtt_fac_31 : 16; + uint32_t reserved_27a : 32; +#else + uint32_t rtt_num_streams : 8, + rtt_rx_chain_mask : 8, + rtt_num_fac : 8, + reserved_0 : 4, + rtt_11az_mode : 2, + rtt_hw_ifft_mode : 1, + rx_location_info_valid : 1; + uint32_t rtt_cir_status : 8, + rtt_cfr_status : 8, + rtt_second_selected_chain : 8, + rtt_first_selected_chain : 8; + uint32_t rtt_che_buffer_pointer_low32 : 32; + uint32_t rtt_mcs_rate : 8, + rtt_pkt_bw_leg : 4, + rtt_pkt_bw_vht : 4, + reserved_3 : 8, + rtt_che_buffer_pointer_high8 : 8; + uint32_t rtt_gi_type : 8, + rtt_preamble_type : 8, + rtt_cfo_measurement : 16; + uint32_t rx_start_ts : 32; + uint32_t rx_start_ts_upper : 32; + uint32_t rx_end_ts : 32; + uint32_t gain_chain1 : 16, + gain_chain0 : 16; + uint32_t gain_chain3 : 16, + gain_chain2 : 16; + uint32_t rtt_fac_combined : 16, + rtt_timing_backoff_sel : 8, + gain_report_status : 8; + uint32_t rtt_fac_1 : 16, + rtt_fac_0 : 16; + uint32_t rtt_fac_3 : 16, + rtt_fac_2 : 16; + uint32_t rtt_fac_5 : 16, + rtt_fac_4 : 16; + uint32_t rtt_fac_7 : 16, + rtt_fac_6 : 16; + uint32_t rtt_fac_9 : 16, + rtt_fac_8 : 16; + uint32_t rtt_fac_11 : 16, + rtt_fac_10 : 16; + uint32_t rtt_fac_13 : 16, + rtt_fac_12 : 16; + uint32_t rtt_fac_15 : 16, + rtt_fac_14 : 16; + uint32_t rtt_fac_17 : 16, + rtt_fac_16 : 16; + uint32_t rtt_fac_19 : 16, + rtt_fac_18 : 16; + uint32_t rtt_fac_21 : 16, + rtt_fac_20 : 16; + uint32_t rtt_fac_23 : 16, + rtt_fac_22 : 16; + uint32_t rtt_fac_25 : 16, + rtt_fac_24 : 16; + uint32_t rtt_fac_27 : 16, + rtt_fac_26 : 16; + uint32_t rtt_fac_29 : 16, + rtt_fac_28 : 16; + uint32_t rtt_fac_31 : 16, + rtt_fac_30 : 16; + uint32_t reserved_27a : 32; +#endif +}; + +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_LSB 0 +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MSB 0 +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MASK 0x00000001 + +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_LSB 1 +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MSB 1 +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MASK 0x00000002 + +#define RX_LOCATION_INFO_RTT_11AZ_MODE_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_11AZ_MODE_LSB 2 +#define RX_LOCATION_INFO_RTT_11AZ_MODE_MSB 3 +#define RX_LOCATION_INFO_RTT_11AZ_MODE_MASK 0x0000000c + +#define RX_LOCATION_INFO_RESERVED_0_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RESERVED_0_LSB 4 +#define RX_LOCATION_INFO_RESERVED_0_MSB 7 +#define RX_LOCATION_INFO_RESERVED_0_MASK 0x000000f0 + +#define RX_LOCATION_INFO_RTT_NUM_FAC_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_NUM_FAC_LSB 8 +#define RX_LOCATION_INFO_RTT_NUM_FAC_MSB 15 +#define RX_LOCATION_INFO_RTT_NUM_FAC_MASK 0x0000ff00 + +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_LSB 16 +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MSB 23 +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MASK 0x00ff0000 + +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_LSB 24 +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MSB 31 +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MASK 0xff000000 + +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_LSB 0 +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MSB 7 +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff + +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_LSB 8 +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MSB 15 +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff00 + +#define RX_LOCATION_INFO_RTT_CFR_STATUS_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_CFR_STATUS_LSB 16 +#define RX_LOCATION_INFO_RTT_CFR_STATUS_MSB 23 +#define RX_LOCATION_INFO_RTT_CFR_STATUS_MASK 0x00ff0000 + +#define RX_LOCATION_INFO_RTT_CIR_STATUS_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_CIR_STATUS_LSB 24 +#define RX_LOCATION_INFO_RTT_CIR_STATUS_MSB 31 +#define RX_LOCATION_INFO_RTT_CIR_STATUS_MASK 0xff000000 + +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000008 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff + +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 0 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 7 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff + +#define RX_LOCATION_INFO_RESERVED_3_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RESERVED_3_LSB 8 +#define RX_LOCATION_INFO_RESERVED_3_MSB 15 +#define RX_LOCATION_INFO_RESERVED_3_MASK 0x0000ff00 + +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_LSB 16 +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MSB 19 +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MASK 0x000f0000 + +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_LSB 20 +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MSB 23 +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MASK 0x00f00000 + +#define RX_LOCATION_INFO_RTT_MCS_RATE_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_MCS_RATE_LSB 24 +#define RX_LOCATION_INFO_RTT_MCS_RATE_MSB 31 +#define RX_LOCATION_INFO_RTT_MCS_RATE_MASK 0xff000000 + +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_OFFSET 0x00000010 +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_LSB 0 +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MSB 15 +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_OFFSET 0x00000010 +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_LSB 16 +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MSB 23 +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MASK 0x00ff0000 + +#define RX_LOCATION_INFO_RTT_GI_TYPE_OFFSET 0x00000010 +#define RX_LOCATION_INFO_RTT_GI_TYPE_LSB 24 +#define RX_LOCATION_INFO_RTT_GI_TYPE_MSB 31 +#define RX_LOCATION_INFO_RTT_GI_TYPE_MASK 0xff000000 + +#define RX_LOCATION_INFO_RX_START_TS_OFFSET 0x00000014 +#define RX_LOCATION_INFO_RX_START_TS_LSB 0 +#define RX_LOCATION_INFO_RX_START_TS_MSB 31 +#define RX_LOCATION_INFO_RX_START_TS_MASK 0xffffffff + +#define RX_LOCATION_INFO_RX_START_TS_UPPER_OFFSET 0x00000018 +#define RX_LOCATION_INFO_RX_START_TS_UPPER_LSB 0 +#define RX_LOCATION_INFO_RX_START_TS_UPPER_MSB 31 +#define RX_LOCATION_INFO_RX_START_TS_UPPER_MASK 0xffffffff + +#define RX_LOCATION_INFO_RX_END_TS_OFFSET 0x0000001c +#define RX_LOCATION_INFO_RX_END_TS_LSB 0 +#define RX_LOCATION_INFO_RX_END_TS_MSB 31 +#define RX_LOCATION_INFO_RX_END_TS_MASK 0xffffffff + +#define RX_LOCATION_INFO_GAIN_CHAIN0_OFFSET 0x00000020 +#define RX_LOCATION_INFO_GAIN_CHAIN0_LSB 0 +#define RX_LOCATION_INFO_GAIN_CHAIN0_MSB 15 +#define RX_LOCATION_INFO_GAIN_CHAIN0_MASK 0x0000ffff + +#define RX_LOCATION_INFO_GAIN_CHAIN1_OFFSET 0x00000020 +#define RX_LOCATION_INFO_GAIN_CHAIN1_LSB 16 +#define RX_LOCATION_INFO_GAIN_CHAIN1_MSB 31 +#define RX_LOCATION_INFO_GAIN_CHAIN1_MASK 0xffff0000 + +#define RX_LOCATION_INFO_GAIN_CHAIN2_OFFSET 0x00000024 +#define RX_LOCATION_INFO_GAIN_CHAIN2_LSB 0 +#define RX_LOCATION_INFO_GAIN_CHAIN2_MSB 15 +#define RX_LOCATION_INFO_GAIN_CHAIN2_MASK 0x0000ffff + +#define RX_LOCATION_INFO_GAIN_CHAIN3_OFFSET 0x00000024 +#define RX_LOCATION_INFO_GAIN_CHAIN3_LSB 16 +#define RX_LOCATION_INFO_GAIN_CHAIN3_MSB 31 +#define RX_LOCATION_INFO_GAIN_CHAIN3_MASK 0xffff0000 + +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_OFFSET 0x00000028 +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_LSB 0 +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MSB 7 +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MASK 0x000000ff + +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000028 +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_LSB 8 +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MSB 15 +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MASK 0x0000ff00 + +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_OFFSET 0x00000028 +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_0_OFFSET 0x0000002c +#define RX_LOCATION_INFO_RTT_FAC_0_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_0_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_0_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_1_OFFSET 0x0000002c +#define RX_LOCATION_INFO_RTT_FAC_1_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_1_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_1_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_2_OFFSET 0x00000030 +#define RX_LOCATION_INFO_RTT_FAC_2_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_2_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_2_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_3_OFFSET 0x00000030 +#define RX_LOCATION_INFO_RTT_FAC_3_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_3_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_3_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_4_OFFSET 0x00000034 +#define RX_LOCATION_INFO_RTT_FAC_4_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_4_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_4_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_5_OFFSET 0x00000034 +#define RX_LOCATION_INFO_RTT_FAC_5_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_5_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_5_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_6_OFFSET 0x00000038 +#define RX_LOCATION_INFO_RTT_FAC_6_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_6_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_6_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_7_OFFSET 0x00000038 +#define RX_LOCATION_INFO_RTT_FAC_7_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_7_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_7_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_8_OFFSET 0x0000003c +#define RX_LOCATION_INFO_RTT_FAC_8_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_8_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_8_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_9_OFFSET 0x0000003c +#define RX_LOCATION_INFO_RTT_FAC_9_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_9_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_9_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_10_OFFSET 0x00000040 +#define RX_LOCATION_INFO_RTT_FAC_10_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_10_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_10_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_11_OFFSET 0x00000040 +#define RX_LOCATION_INFO_RTT_FAC_11_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_11_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_11_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_12_OFFSET 0x00000044 +#define RX_LOCATION_INFO_RTT_FAC_12_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_12_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_12_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_13_OFFSET 0x00000044 +#define RX_LOCATION_INFO_RTT_FAC_13_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_13_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_13_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_14_OFFSET 0x00000048 +#define RX_LOCATION_INFO_RTT_FAC_14_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_14_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_14_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_15_OFFSET 0x00000048 +#define RX_LOCATION_INFO_RTT_FAC_15_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_15_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_15_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_16_OFFSET 0x0000004c +#define RX_LOCATION_INFO_RTT_FAC_16_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_16_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_16_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_17_OFFSET 0x0000004c +#define RX_LOCATION_INFO_RTT_FAC_17_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_17_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_17_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_18_OFFSET 0x00000050 +#define RX_LOCATION_INFO_RTT_FAC_18_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_18_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_18_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_19_OFFSET 0x00000050 +#define RX_LOCATION_INFO_RTT_FAC_19_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_19_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_19_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_20_OFFSET 0x00000054 +#define RX_LOCATION_INFO_RTT_FAC_20_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_20_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_20_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_21_OFFSET 0x00000054 +#define RX_LOCATION_INFO_RTT_FAC_21_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_21_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_21_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_22_OFFSET 0x00000058 +#define RX_LOCATION_INFO_RTT_FAC_22_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_22_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_22_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_23_OFFSET 0x00000058 +#define RX_LOCATION_INFO_RTT_FAC_23_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_23_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_23_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_24_OFFSET 0x0000005c +#define RX_LOCATION_INFO_RTT_FAC_24_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_24_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_24_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_25_OFFSET 0x0000005c +#define RX_LOCATION_INFO_RTT_FAC_25_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_25_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_25_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_26_OFFSET 0x00000060 +#define RX_LOCATION_INFO_RTT_FAC_26_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_26_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_26_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_27_OFFSET 0x00000060 +#define RX_LOCATION_INFO_RTT_FAC_27_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_27_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_27_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_28_OFFSET 0x00000064 +#define RX_LOCATION_INFO_RTT_FAC_28_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_28_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_28_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_29_OFFSET 0x00000064 +#define RX_LOCATION_INFO_RTT_FAC_29_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_29_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_29_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_30_OFFSET 0x00000068 +#define RX_LOCATION_INFO_RTT_FAC_30_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_30_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_30_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_31_OFFSET 0x00000068 +#define RX_LOCATION_INFO_RTT_FAC_31_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_31_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_31_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RESERVED_27A_OFFSET 0x0000006c +#define RX_LOCATION_INFO_RESERVED_27A_LSB 0 +#define RX_LOCATION_INFO_RESERVED_27A_MSB 31 +#define RX_LOCATION_INFO_RESERVED_27A_MASK 0xffffffff + +#endif diff --git a/hw/kiwi/v2/rx_mpdu_desc_info.h b/hw/kiwi/v2/rx_mpdu_desc_info.h new file mode 100644 index 000000000000..dcad67636df2 --- /dev/null +++ b/hw/kiwi/v2/rx_mpdu_desc_info.h @@ -0,0 +1,119 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MPDU_DESC_INFO_H_ +#define _RX_MPDU_DESC_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2 + +struct rx_mpdu_desc_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t msdu_count : 8, + fragment_flag : 1, + mpdu_retry_bit : 1, + ampdu_flag : 1, + bar_frame : 1, + pn_fields_contain_valid_info : 1, + raw_mpdu : 1, + more_fragment_flag : 1, + src_info : 12, + mpdu_qos_control_valid : 1, + tid : 4; + uint32_t peer_meta_data : 32; +#else + uint32_t tid : 4, + mpdu_qos_control_valid : 1, + src_info : 12, + more_fragment_flag : 1, + raw_mpdu : 1, + pn_fields_contain_valid_info : 1, + bar_frame : 1, + ampdu_flag : 1, + mpdu_retry_bit : 1, + fragment_flag : 1, + msdu_count : 8; + uint32_t peer_meta_data : 32; +#endif +}; + +#define RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MSDU_COUNT_LSB 0 +#define RX_MPDU_DESC_INFO_MSDU_COUNT_MSB 7 +#define RX_MPDU_DESC_INFO_MSDU_COUNT_MASK 0x000000ff + +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_LSB 8 +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MSB 8 +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MASK 0x00000100 + +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_LSB 9 +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MSB 9 +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MASK 0x00000200 + +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_LSB 10 +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MSB 10 +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK 0x00000400 + +#define RX_MPDU_DESC_INFO_BAR_FRAME_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_BAR_FRAME_LSB 11 +#define RX_MPDU_DESC_INFO_BAR_FRAME_MSB 11 +#define RX_MPDU_DESC_INFO_BAR_FRAME_MASK 0x00000800 + +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + +#define RX_MPDU_DESC_INFO_RAW_MPDU_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_RAW_MPDU_LSB 13 +#define RX_MPDU_DESC_INFO_RAW_MPDU_MSB 13 +#define RX_MPDU_DESC_INFO_RAW_MPDU_MASK 0x00002000 + +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MSB 14 +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define RX_MPDU_DESC_INFO_SRC_INFO_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_SRC_INFO_LSB 15 +#define RX_MPDU_DESC_INFO_SRC_INFO_MSB 26 +#define RX_MPDU_DESC_INFO_SRC_INFO_MASK 0x07ff8000 + +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_LSB 27 +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MSB 27 +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + +#define RX_MPDU_DESC_INFO_TID_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_TID_LSB 28 +#define RX_MPDU_DESC_INFO_TID_MSB 31 +#define RX_MPDU_DESC_INFO_TID_MASK 0xf0000000 + +#define RX_MPDU_DESC_INFO_PEER_META_DATA_OFFSET 0x00000004 +#define RX_MPDU_DESC_INFO_PEER_META_DATA_LSB 0 +#define RX_MPDU_DESC_INFO_PEER_META_DATA_MSB 31 +#define RX_MPDU_DESC_INFO_PEER_META_DATA_MASK 0xffffffff + +#endif diff --git a/hw/kiwi/v2/rx_mpdu_details.h b/hw/kiwi/v2/rx_mpdu_details.h new file mode 100644 index 000000000000..b43fff65c28c --- /dev/null +++ b/hw/kiwi/v2/rx_mpdu_details.h @@ -0,0 +1,121 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MPDU_DETAILS_H_ +#define _RX_MPDU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_RX_MPDU_DETAILS 4 + +struct rx_mpdu_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info msdu_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; +#else + struct buffer_addr_info msdu_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; +#endif +}; + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#endif diff --git a/hw/kiwi/v2/rx_mpdu_end.h b/hw/kiwi/v2/rx_mpdu_end.h new file mode 100644 index 000000000000..1873d84c1f09 --- /dev/null +++ b/hw/kiwi/v2/rx_mpdu_end.h @@ -0,0 +1,200 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MPDU_END_H_ +#define _RX_MPDU_END_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MPDU_END 4 + +#define NUM_OF_QWORDS_RX_MPDU_END 2 + +struct rx_mpdu_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t reserved_1a : 11, + unsup_ktype_short_frame : 1, + rx_in_tx_decrypt_byp : 1, + overflow_err : 1, + mpdu_length_err : 1, + tkip_mic_err : 1, + decrypt_err : 1, + unencrypted_frame_err : 1, + pn_fields_contain_valid_info : 1, + fcs_err : 1, + msdu_length_err : 1, + rxdma0_destination_ring : 3, + rxdma1_destination_ring : 3, + decrypt_status_code : 3, + rx_bitmap_not_updated : 1, + reserved_1b : 1; + uint32_t reserved_2a : 15, + rxpcu_mgmt_sequence_nr_valid : 1, + rxpcu_mgmt_sequence_nr : 16; + uint32_t __reserved_g_0002 : 32; +#else + uint32_t phy_ppdu_id : 16, + reserved_0 : 7, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t reserved_1b : 1, + rx_bitmap_not_updated : 1, + decrypt_status_code : 3, + rxdma1_destination_ring : 3, + rxdma0_destination_ring : 3, + msdu_length_err : 1, + fcs_err : 1, + pn_fields_contain_valid_info : 1, + unencrypted_frame_err : 1, + decrypt_err : 1, + tkip_mic_err : 1, + mpdu_length_err : 1, + overflow_err : 1, + rx_in_tx_decrypt_byp : 1, + unsup_ktype_short_frame : 1, + reserved_1a : 11; + uint32_t rxpcu_mgmt_sequence_nr : 16, + rxpcu_mgmt_sequence_nr_valid : 1, + reserved_2a : 15; + uint32_t __reserved_g_0002 : 32; +#endif +}; + +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 + +#define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 +#define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc + +#define RX_MPDU_END_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RESERVED_0_LSB 9 +#define RX_MPDU_END_RESERVED_0_MSB 15 +#define RX_MPDU_END_RESERVED_0_MASK 0x000000000000fe00 + +#define RX_MPDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_MPDU_END_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_END_PHY_PPDU_ID_MSB 31 +#define RX_MPDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 + +#define RX_MPDU_END_RESERVED_1A_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RESERVED_1A_LSB 32 +#define RX_MPDU_END_RESERVED_1A_MSB 42 +#define RX_MPDU_END_RESERVED_1A_MASK 0x000007ff00000000 + +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x0000000000000000 +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB 43 +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB 43 +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK 0x0000080000000000 + +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB 44 +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB 44 +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000100000000000 + +#define RX_MPDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_OVERFLOW_ERR_LSB 45 +#define RX_MPDU_END_OVERFLOW_ERR_MSB 45 +#define RX_MPDU_END_OVERFLOW_ERR_MASK 0x0000200000000000 + +#define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_MPDU_LENGTH_ERR_LSB 46 +#define RX_MPDU_END_MPDU_LENGTH_ERR_MSB 46 +#define RX_MPDU_END_MPDU_LENGTH_ERR_MASK 0x0000400000000000 + +#define RX_MPDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_TKIP_MIC_ERR_LSB 47 +#define RX_MPDU_END_TKIP_MIC_ERR_MSB 47 +#define RX_MPDU_END_TKIP_MIC_ERR_MASK 0x0000800000000000 + +#define RX_MPDU_END_DECRYPT_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_DECRYPT_ERR_LSB 48 +#define RX_MPDU_END_DECRYPT_ERR_MSB 48 +#define RX_MPDU_END_DECRYPT_ERR_MASK 0x0001000000000000 + +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB 49 +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB 49 +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0002000000000000 + +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000000000000 +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB 50 +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB 50 +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x0004000000000000 + +#define RX_MPDU_END_FCS_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_FCS_ERR_LSB 51 +#define RX_MPDU_END_FCS_ERR_MSB 51 +#define RX_MPDU_END_FCS_ERR_MASK 0x0008000000000000 + +#define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_MSDU_LENGTH_ERR_LSB 52 +#define RX_MPDU_END_MSDU_LENGTH_ERR_MSB 52 +#define RX_MPDU_END_MSDU_LENGTH_ERR_MASK 0x0010000000000000 + +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_LSB 53 +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_MSB 55 +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_MASK 0x00e0000000000000 + +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_LSB 56 +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_MSB 58 +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_MASK 0x0700000000000000 + +#define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000000 +#define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB 59 +#define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB 61 +#define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK 0x3800000000000000 + +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB 62 +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB 62 +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x4000000000000000 + +#define RX_MPDU_END_RESERVED_1B_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RESERVED_1B_LSB 63 +#define RX_MPDU_END_RESERVED_1B_MSB 63 +#define RX_MPDU_END_RESERVED_1B_MASK 0x8000000000000000 + +#define RX_MPDU_END_RESERVED_2A_OFFSET 0x0000000000000008 +#define RX_MPDU_END_RESERVED_2A_LSB 0 +#define RX_MPDU_END_RESERVED_2A_MSB 14 +#define RX_MPDU_END_RESERVED_2A_MASK 0x0000000000007fff + +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET 0x0000000000000008 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB 15 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB 15 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK 0x0000000000008000 + +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET 0x0000000000000008 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB 16 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB 31 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK 0x00000000ffff0000 + +#endif diff --git a/hw/kiwi/v2/rx_mpdu_info.h b/hw/kiwi/v2/rx_mpdu_info.h new file mode 100644 index 000000000000..d9e6cee42973 --- /dev/null +++ b/hw/kiwi/v2/rx_mpdu_info.h @@ -0,0 +1,836 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MPDU_INFO_H_ +#define _RX_MPDU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rxpt_classify_info.h" +#define NUM_OF_DWORDS_RX_MPDU_INFO 30 + +struct rx_mpdu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rxpt_classify_info rxpt_classify_info_details; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + receive_queue_number : 16, + pre_delim_err_warning : 1, + first_delim_err : 1, + reserved_2a : 6; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t epd_en : 1, + all_frames_shall_be_encrypted : 1, + encrypt_type : 4, + wep_key_width_for_variable_key : 2, + __reserved_g_0003 : 2, + bssid_hit : 1, + bssid_number : 4, + tid : 4, + reserved_7a : 13; + uint32_t peer_meta_data : 32; + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + ndp_frame : 1, + phy_err : 1, + phy_err_during_mpdu_header : 1, + protocol_version_err : 1, + ast_based_lookup_valid : 1, + __reserved_g_0005 : 1, + reserved_9a : 1, + phy_ppdu_id : 16; + uint32_t ast_index : 16, + sw_peer_id : 16; + uint32_t mpdu_frame_control_valid : 1, + mpdu_duration_valid : 1, + mac_addr_ad1_valid : 1, + mac_addr_ad2_valid : 1, + mac_addr_ad3_valid : 1, + mac_addr_ad4_valid : 1, + mpdu_sequence_control_valid : 1, + mpdu_qos_control_valid : 1, + mpdu_ht_control_valid : 1, + frame_encryption_info_valid : 1, + mpdu_fragment_number : 4, + more_fragment_flag : 1, + reserved_11a : 1, + fr_ds : 1, + to_ds : 1, + encrypted : 1, + mpdu_retry : 1, + mpdu_sequence_number : 12; + uint32_t key_id_octet : 8, + new_peer_entry : 1, + decrypt_needed : 1, + decap_type : 2, + rx_insert_vlan_c_tag_padding : 1, + rx_insert_vlan_s_tag_padding : 1, + strip_vlan_c_tag_decap : 1, + strip_vlan_s_tag_decap : 1, + pre_delim_count : 12, + ampdu_flag : 1, + bar_frame : 1, + raw_mpdu : 1, + reserved_12 : 1; + uint32_t mpdu_length : 14, + first_mpdu : 1, + mcast_bcast : 1, + ast_index_not_found : 1, + ast_index_timeout : 1, + power_mgmt : 1, + non_qos : 1, + null_data : 1, + mgmt_type : 1, + ctrl_type : 1, + more_data : 1, + eosp : 1, + fragment_flag : 1, + order : 1, + u_apsd_trigger : 1, + encrypt_required : 1, + directed : 1, + amsdu_present : 1, + reserved_13 : 1; + uint32_t mpdu_frame_control_field : 16, + mpdu_duration_field : 16; + uint32_t mac_addr_ad1_31_0 : 32; + uint32_t mac_addr_ad1_47_32 : 16, + mac_addr_ad2_15_0 : 16; + uint32_t mac_addr_ad2_47_16 : 32; + uint32_t mac_addr_ad3_31_0 : 32; + uint32_t mac_addr_ad3_47_32 : 16, + mpdu_sequence_control_field : 16; + uint32_t mac_addr_ad4_31_0 : 32; + uint32_t mac_addr_ad4_47_32 : 16, + mpdu_qos_control_field : 16; + uint32_t mpdu_ht_control_field : 32; + uint32_t vdev_id : 8, + service_code : 9, + priority_valid : 1, + src_info : 12, + reserved_23a : 1, + __reserved_g_0006 : 1; + uint32_t __reserved_g_0007 : 32; + uint32_t __reserved_g_0008 : 16, + __reserved_g_0009 : 16; + uint32_t __reserved_g_0010 : 32; + uint32_t authorized_to_send_wds : 1, + reserved_27a : 31; + uint32_t reserved_28a : 32; + uint32_t reserved_29a : 32; +#else + struct rxpt_classify_info rxpt_classify_info_details; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t reserved_2a : 6, + first_delim_err : 1, + pre_delim_err_warning : 1, + receive_queue_number : 16, + rx_reo_queue_desc_addr_39_32 : 8; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t reserved_7a : 13, + tid : 4, + bssid_number : 4, + bssid_hit : 1, + __reserved_g_0003 : 2, + wep_key_width_for_variable_key : 2, + encrypt_type : 4, + all_frames_shall_be_encrypted : 1, + epd_en : 1; + uint32_t peer_meta_data : 32; + uint32_t phy_ppdu_id : 16, + reserved_9a : 1, + __reserved_g_0005 : 1, + ast_based_lookup_valid : 1, + protocol_version_err : 1, + phy_err_during_mpdu_header : 1, + phy_err : 1, + ndp_frame : 1, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t sw_peer_id : 16, + ast_index : 16; + uint32_t mpdu_sequence_number : 12, + mpdu_retry : 1, + encrypted : 1, + to_ds : 1, + fr_ds : 1, + reserved_11a : 1, + more_fragment_flag : 1, + mpdu_fragment_number : 4, + frame_encryption_info_valid : 1, + mpdu_ht_control_valid : 1, + mpdu_qos_control_valid : 1, + mpdu_sequence_control_valid : 1, + mac_addr_ad4_valid : 1, + mac_addr_ad3_valid : 1, + mac_addr_ad2_valid : 1, + mac_addr_ad1_valid : 1, + mpdu_duration_valid : 1, + mpdu_frame_control_valid : 1; + uint32_t reserved_12 : 1, + raw_mpdu : 1, + bar_frame : 1, + ampdu_flag : 1, + pre_delim_count : 12, + strip_vlan_s_tag_decap : 1, + strip_vlan_c_tag_decap : 1, + rx_insert_vlan_s_tag_padding : 1, + rx_insert_vlan_c_tag_padding : 1, + decap_type : 2, + decrypt_needed : 1, + new_peer_entry : 1, + key_id_octet : 8; + uint32_t reserved_13 : 1, + amsdu_present : 1, + directed : 1, + encrypt_required : 1, + u_apsd_trigger : 1, + order : 1, + fragment_flag : 1, + eosp : 1, + more_data : 1, + ctrl_type : 1, + mgmt_type : 1, + null_data : 1, + non_qos : 1, + power_mgmt : 1, + ast_index_timeout : 1, + ast_index_not_found : 1, + mcast_bcast : 1, + first_mpdu : 1, + mpdu_length : 14; + uint32_t mpdu_duration_field : 16, + mpdu_frame_control_field : 16; + uint32_t mac_addr_ad1_31_0 : 32; + uint32_t mac_addr_ad2_15_0 : 16, + mac_addr_ad1_47_32 : 16; + uint32_t mac_addr_ad2_47_16 : 32; + uint32_t mac_addr_ad3_31_0 : 32; + uint32_t mpdu_sequence_control_field : 16, + mac_addr_ad3_47_32 : 16; + uint32_t mac_addr_ad4_31_0 : 32; + uint32_t mpdu_qos_control_field : 16, + mac_addr_ad4_47_32 : 16; + uint32_t mpdu_ht_control_field : 32; + uint32_t __reserved_g_0006 : 1, + reserved_23a : 1, + src_info : 12, + priority_valid : 1, + service_code : 9, + vdev_id : 8; + uint32_t __reserved_g_0007 : 32; + uint32_t __reserved_g_0009 : 16, + __reserved_g_0008 : 16; + uint32_t __reserved_g_0010 : 32; + uint32_t reserved_27a : 31, + authorized_to_send_wds : 1; + uint32_t reserved_28a : 32; + uint32_t reserved_29a : 32; +#endif +}; + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x00040000 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x00080000 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x00100000 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x00200000 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 22 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffc00000 + +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_LSB 8 +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MSB 23 +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 + +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008 +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_LSB 24 +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MSB 24 +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MASK 0x01000000 + +#define RX_MPDU_INFO_FIRST_DELIM_ERR_OFFSET 0x00000008 +#define RX_MPDU_INFO_FIRST_DELIM_ERR_LSB 25 +#define RX_MPDU_INFO_FIRST_DELIM_ERR_MSB 25 +#define RX_MPDU_INFO_FIRST_DELIM_ERR_MASK 0x02000000 + +#define RX_MPDU_INFO_RESERVED_2A_OFFSET 0x00000008 +#define RX_MPDU_INFO_RESERVED_2A_LSB 26 +#define RX_MPDU_INFO_RESERVED_2A_MSB 31 +#define RX_MPDU_INFO_RESERVED_2A_MASK 0xfc000000 + +#define RX_MPDU_INFO_PN_31_0_OFFSET 0x0000000c +#define RX_MPDU_INFO_PN_31_0_LSB 0 +#define RX_MPDU_INFO_PN_31_0_MSB 31 +#define RX_MPDU_INFO_PN_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_PN_63_32_OFFSET 0x00000010 +#define RX_MPDU_INFO_PN_63_32_LSB 0 +#define RX_MPDU_INFO_PN_63_32_MSB 31 +#define RX_MPDU_INFO_PN_63_32_MASK 0xffffffff + +#define RX_MPDU_INFO_PN_95_64_OFFSET 0x00000014 +#define RX_MPDU_INFO_PN_95_64_LSB 0 +#define RX_MPDU_INFO_PN_95_64_MSB 31 +#define RX_MPDU_INFO_PN_95_64_MASK 0xffffffff + +#define RX_MPDU_INFO_PN_127_96_OFFSET 0x00000018 +#define RX_MPDU_INFO_PN_127_96_LSB 0 +#define RX_MPDU_INFO_PN_127_96_MSB 31 +#define RX_MPDU_INFO_PN_127_96_MASK 0xffffffff + +#define RX_MPDU_INFO_EPD_EN_OFFSET 0x0000001c +#define RX_MPDU_INFO_EPD_EN_LSB 0 +#define RX_MPDU_INFO_EPD_EN_MSB 0 +#define RX_MPDU_INFO_EPD_EN_MASK 0x00000001 + +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 1 +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 + +#define RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET 0x0000001c +#define RX_MPDU_INFO_ENCRYPT_TYPE_LSB 2 +#define RX_MPDU_INFO_ENCRYPT_TYPE_MSB 5 +#define RX_MPDU_INFO_ENCRYPT_TYPE_MASK 0x0000003c + +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 7 +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 + +#define RX_MPDU_INFO_BSSID_HIT_OFFSET 0x0000001c +#define RX_MPDU_INFO_BSSID_HIT_LSB 10 +#define RX_MPDU_INFO_BSSID_HIT_MSB 10 +#define RX_MPDU_INFO_BSSID_HIT_MASK 0x00000400 + +#define RX_MPDU_INFO_BSSID_NUMBER_OFFSET 0x0000001c +#define RX_MPDU_INFO_BSSID_NUMBER_LSB 11 +#define RX_MPDU_INFO_BSSID_NUMBER_MSB 14 +#define RX_MPDU_INFO_BSSID_NUMBER_MASK 0x00007800 + +#define RX_MPDU_INFO_TID_OFFSET 0x0000001c +#define RX_MPDU_INFO_TID_LSB 15 +#define RX_MPDU_INFO_TID_MSB 18 +#define RX_MPDU_INFO_TID_MASK 0x00078000 + +#define RX_MPDU_INFO_RESERVED_7A_OFFSET 0x0000001c +#define RX_MPDU_INFO_RESERVED_7A_LSB 19 +#define RX_MPDU_INFO_RESERVED_7A_MSB 31 +#define RX_MPDU_INFO_RESERVED_7A_MASK 0xfff80000 + +#define RX_MPDU_INFO_PEER_META_DATA_OFFSET 0x00000020 +#define RX_MPDU_INFO_PEER_META_DATA_LSB 0 +#define RX_MPDU_INFO_PEER_META_DATA_MSB 31 +#define RX_MPDU_INFO_PEER_META_DATA_MASK 0xffffffff + +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024 +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_OFFSET 0x00000024 +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MPDU_INFO_NDP_FRAME_OFFSET 0x00000024 +#define RX_MPDU_INFO_NDP_FRAME_LSB 9 +#define RX_MPDU_INFO_NDP_FRAME_MSB 9 +#define RX_MPDU_INFO_NDP_FRAME_MASK 0x00000200 + +#define RX_MPDU_INFO_PHY_ERR_OFFSET 0x00000024 +#define RX_MPDU_INFO_PHY_ERR_LSB 10 +#define RX_MPDU_INFO_PHY_ERR_MSB 10 +#define RX_MPDU_INFO_PHY_ERR_MASK 0x00000400 + +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024 +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_LSB 11 +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MSB 11 +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 + +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_OFFSET 0x00000024 +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_LSB 12 +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MSB 12 +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MASK 0x00001000 + +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024 +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_LSB 13 +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MSB 13 +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MASK 0x00002000 + +#define RX_MPDU_INFO_RESERVED_9A_OFFSET 0x00000024 +#define RX_MPDU_INFO_RESERVED_9A_LSB 15 +#define RX_MPDU_INFO_RESERVED_9A_MSB 15 +#define RX_MPDU_INFO_RESERVED_9A_MASK 0x00008000 + +#define RX_MPDU_INFO_PHY_PPDU_ID_OFFSET 0x00000024 +#define RX_MPDU_INFO_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_INFO_PHY_PPDU_ID_MSB 31 +#define RX_MPDU_INFO_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MPDU_INFO_AST_INDEX_OFFSET 0x00000028 +#define RX_MPDU_INFO_AST_INDEX_LSB 0 +#define RX_MPDU_INFO_AST_INDEX_MSB 15 +#define RX_MPDU_INFO_AST_INDEX_MASK 0x0000ffff + +#define RX_MPDU_INFO_SW_PEER_ID_OFFSET 0x00000028 +#define RX_MPDU_INFO_SW_PEER_ID_LSB 16 +#define RX_MPDU_INFO_SW_PEER_ID_MSB 31 +#define RX_MPDU_INFO_SW_PEER_ID_MASK 0xffff0000 + +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_LSB 0 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MSB 0 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 + +#define RX_MPDU_INFO_MPDU_DURATION_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_DURATION_VALID_LSB 1 +#define RX_MPDU_INFO_MPDU_DURATION_VALID_MSB 1 +#define RX_MPDU_INFO_MPDU_DURATION_VALID_MASK 0x00000002 + +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_LSB 2 +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MSB 2 +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MASK 0x00000004 + +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_LSB 3 +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MSB 3 +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MASK 0x00000008 + +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_LSB 4 +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MSB 4 +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MASK 0x00000010 + +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_LSB 5 +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MSB 5 +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MASK 0x00000020 + +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 + +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_LSB 7 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MSB 7 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 + +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_LSB 8 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MSB 8 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MASK 0x00000100 + +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_LSB 9 +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MSB 9 +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 + +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_LSB 10 +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MSB 13 +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 + +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MSB 14 +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define RX_MPDU_INFO_RESERVED_11A_OFFSET 0x0000002c +#define RX_MPDU_INFO_RESERVED_11A_LSB 15 +#define RX_MPDU_INFO_RESERVED_11A_MSB 15 +#define RX_MPDU_INFO_RESERVED_11A_MASK 0x00008000 + +#define RX_MPDU_INFO_FR_DS_OFFSET 0x0000002c +#define RX_MPDU_INFO_FR_DS_LSB 16 +#define RX_MPDU_INFO_FR_DS_MSB 16 +#define RX_MPDU_INFO_FR_DS_MASK 0x00010000 + +#define RX_MPDU_INFO_TO_DS_OFFSET 0x0000002c +#define RX_MPDU_INFO_TO_DS_LSB 17 +#define RX_MPDU_INFO_TO_DS_MSB 17 +#define RX_MPDU_INFO_TO_DS_MASK 0x00020000 + +#define RX_MPDU_INFO_ENCRYPTED_OFFSET 0x0000002c +#define RX_MPDU_INFO_ENCRYPTED_LSB 18 +#define RX_MPDU_INFO_ENCRYPTED_MSB 18 +#define RX_MPDU_INFO_ENCRYPTED_MASK 0x00040000 + +#define RX_MPDU_INFO_MPDU_RETRY_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_RETRY_LSB 19 +#define RX_MPDU_INFO_MPDU_RETRY_MSB 19 +#define RX_MPDU_INFO_MPDU_RETRY_MASK 0x00080000 + +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_LSB 20 +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MSB 31 +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 + +#define RX_MPDU_INFO_KEY_ID_OCTET_OFFSET 0x00000030 +#define RX_MPDU_INFO_KEY_ID_OCTET_LSB 0 +#define RX_MPDU_INFO_KEY_ID_OCTET_MSB 7 +#define RX_MPDU_INFO_KEY_ID_OCTET_MASK 0x000000ff + +#define RX_MPDU_INFO_NEW_PEER_ENTRY_OFFSET 0x00000030 +#define RX_MPDU_INFO_NEW_PEER_ENTRY_LSB 8 +#define RX_MPDU_INFO_NEW_PEER_ENTRY_MSB 8 +#define RX_MPDU_INFO_NEW_PEER_ENTRY_MASK 0x00000100 + +#define RX_MPDU_INFO_DECRYPT_NEEDED_OFFSET 0x00000030 +#define RX_MPDU_INFO_DECRYPT_NEEDED_LSB 9 +#define RX_MPDU_INFO_DECRYPT_NEEDED_MSB 9 +#define RX_MPDU_INFO_DECRYPT_NEEDED_MASK 0x00000200 + +#define RX_MPDU_INFO_DECAP_TYPE_OFFSET 0x00000030 +#define RX_MPDU_INFO_DECAP_TYPE_LSB 10 +#define RX_MPDU_INFO_DECAP_TYPE_MSB 11 +#define RX_MPDU_INFO_DECAP_TYPE_MASK 0x00000c00 + +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 + +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 + +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_LSB 14 +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MSB 14 +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 + +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_LSB 15 +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MSB 15 +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 + +#define RX_MPDU_INFO_PRE_DELIM_COUNT_OFFSET 0x00000030 +#define RX_MPDU_INFO_PRE_DELIM_COUNT_LSB 16 +#define RX_MPDU_INFO_PRE_DELIM_COUNT_MSB 27 +#define RX_MPDU_INFO_PRE_DELIM_COUNT_MASK 0x0fff0000 + +#define RX_MPDU_INFO_AMPDU_FLAG_OFFSET 0x00000030 +#define RX_MPDU_INFO_AMPDU_FLAG_LSB 28 +#define RX_MPDU_INFO_AMPDU_FLAG_MSB 28 +#define RX_MPDU_INFO_AMPDU_FLAG_MASK 0x10000000 + +#define RX_MPDU_INFO_BAR_FRAME_OFFSET 0x00000030 +#define RX_MPDU_INFO_BAR_FRAME_LSB 29 +#define RX_MPDU_INFO_BAR_FRAME_MSB 29 +#define RX_MPDU_INFO_BAR_FRAME_MASK 0x20000000 + +#define RX_MPDU_INFO_RAW_MPDU_OFFSET 0x00000030 +#define RX_MPDU_INFO_RAW_MPDU_LSB 30 +#define RX_MPDU_INFO_RAW_MPDU_MSB 30 +#define RX_MPDU_INFO_RAW_MPDU_MASK 0x40000000 + +#define RX_MPDU_INFO_RESERVED_12_OFFSET 0x00000030 +#define RX_MPDU_INFO_RESERVED_12_LSB 31 +#define RX_MPDU_INFO_RESERVED_12_MSB 31 +#define RX_MPDU_INFO_RESERVED_12_MASK 0x80000000 + +#define RX_MPDU_INFO_MPDU_LENGTH_OFFSET 0x00000034 +#define RX_MPDU_INFO_MPDU_LENGTH_LSB 0 +#define RX_MPDU_INFO_MPDU_LENGTH_MSB 13 +#define RX_MPDU_INFO_MPDU_LENGTH_MASK 0x00003fff + +#define RX_MPDU_INFO_FIRST_MPDU_OFFSET 0x00000034 +#define RX_MPDU_INFO_FIRST_MPDU_LSB 14 +#define RX_MPDU_INFO_FIRST_MPDU_MSB 14 +#define RX_MPDU_INFO_FIRST_MPDU_MASK 0x00004000 + +#define RX_MPDU_INFO_MCAST_BCAST_OFFSET 0x00000034 +#define RX_MPDU_INFO_MCAST_BCAST_LSB 15 +#define RX_MPDU_INFO_MCAST_BCAST_MSB 15 +#define RX_MPDU_INFO_MCAST_BCAST_MASK 0x00008000 + +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_LSB 16 +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MSB 16 +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MASK 0x00010000 + +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_OFFSET 0x00000034 +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_LSB 17 +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MSB 17 +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MASK 0x00020000 + +#define RX_MPDU_INFO_POWER_MGMT_OFFSET 0x00000034 +#define RX_MPDU_INFO_POWER_MGMT_LSB 18 +#define RX_MPDU_INFO_POWER_MGMT_MSB 18 +#define RX_MPDU_INFO_POWER_MGMT_MASK 0x00040000 + +#define RX_MPDU_INFO_NON_QOS_OFFSET 0x00000034 +#define RX_MPDU_INFO_NON_QOS_LSB 19 +#define RX_MPDU_INFO_NON_QOS_MSB 19 +#define RX_MPDU_INFO_NON_QOS_MASK 0x00080000 + +#define RX_MPDU_INFO_NULL_DATA_OFFSET 0x00000034 +#define RX_MPDU_INFO_NULL_DATA_LSB 20 +#define RX_MPDU_INFO_NULL_DATA_MSB 20 +#define RX_MPDU_INFO_NULL_DATA_MASK 0x00100000 + +#define RX_MPDU_INFO_MGMT_TYPE_OFFSET 0x00000034 +#define RX_MPDU_INFO_MGMT_TYPE_LSB 21 +#define RX_MPDU_INFO_MGMT_TYPE_MSB 21 +#define RX_MPDU_INFO_MGMT_TYPE_MASK 0x00200000 + +#define RX_MPDU_INFO_CTRL_TYPE_OFFSET 0x00000034 +#define RX_MPDU_INFO_CTRL_TYPE_LSB 22 +#define RX_MPDU_INFO_CTRL_TYPE_MSB 22 +#define RX_MPDU_INFO_CTRL_TYPE_MASK 0x00400000 + +#define RX_MPDU_INFO_MORE_DATA_OFFSET 0x00000034 +#define RX_MPDU_INFO_MORE_DATA_LSB 23 +#define RX_MPDU_INFO_MORE_DATA_MSB 23 +#define RX_MPDU_INFO_MORE_DATA_MASK 0x00800000 + +#define RX_MPDU_INFO_EOSP_OFFSET 0x00000034 +#define RX_MPDU_INFO_EOSP_LSB 24 +#define RX_MPDU_INFO_EOSP_MSB 24 +#define RX_MPDU_INFO_EOSP_MASK 0x01000000 + +#define RX_MPDU_INFO_FRAGMENT_FLAG_OFFSET 0x00000034 +#define RX_MPDU_INFO_FRAGMENT_FLAG_LSB 25 +#define RX_MPDU_INFO_FRAGMENT_FLAG_MSB 25 +#define RX_MPDU_INFO_FRAGMENT_FLAG_MASK 0x02000000 + +#define RX_MPDU_INFO_ORDER_OFFSET 0x00000034 +#define RX_MPDU_INFO_ORDER_LSB 26 +#define RX_MPDU_INFO_ORDER_MSB 26 +#define RX_MPDU_INFO_ORDER_MASK 0x04000000 + +#define RX_MPDU_INFO_U_APSD_TRIGGER_OFFSET 0x00000034 +#define RX_MPDU_INFO_U_APSD_TRIGGER_LSB 27 +#define RX_MPDU_INFO_U_APSD_TRIGGER_MSB 27 +#define RX_MPDU_INFO_U_APSD_TRIGGER_MASK 0x08000000 + +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_OFFSET 0x00000034 +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_LSB 28 +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MSB 28 +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MASK 0x10000000 + +#define RX_MPDU_INFO_DIRECTED_OFFSET 0x00000034 +#define RX_MPDU_INFO_DIRECTED_LSB 29 +#define RX_MPDU_INFO_DIRECTED_MSB 29 +#define RX_MPDU_INFO_DIRECTED_MASK 0x20000000 + +#define RX_MPDU_INFO_AMSDU_PRESENT_OFFSET 0x00000034 +#define RX_MPDU_INFO_AMSDU_PRESENT_LSB 30 +#define RX_MPDU_INFO_AMSDU_PRESENT_MSB 30 +#define RX_MPDU_INFO_AMSDU_PRESENT_MASK 0x40000000 + +#define RX_MPDU_INFO_RESERVED_13_OFFSET 0x00000034 +#define RX_MPDU_INFO_RESERVED_13_LSB 31 +#define RX_MPDU_INFO_RESERVED_13_MSB 31 +#define RX_MPDU_INFO_RESERVED_13_MASK 0x80000000 + +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_LSB 0 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MSB 15 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff + +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_OFFSET 0x00000038 +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_LSB 16 +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MASK 0xffff0000 + +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MSB 15 +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MASK 0x0000ffff + +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_LSB 16 +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MASK 0xffff0000 + +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MASK 0xffffffff + +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MSB 15 +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MASK 0x0000ffff + +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MSB 15 +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MASK 0x0000ffff + +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_LSB 16 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_LSB 0 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff + +#define RX_MPDU_INFO_VDEV_ID_OFFSET 0x0000005c +#define RX_MPDU_INFO_VDEV_ID_LSB 0 +#define RX_MPDU_INFO_VDEV_ID_MSB 7 +#define RX_MPDU_INFO_VDEV_ID_MASK 0x000000ff + +#define RX_MPDU_INFO_SERVICE_CODE_OFFSET 0x0000005c +#define RX_MPDU_INFO_SERVICE_CODE_LSB 8 +#define RX_MPDU_INFO_SERVICE_CODE_MSB 16 +#define RX_MPDU_INFO_SERVICE_CODE_MASK 0x0001ff00 + +#define RX_MPDU_INFO_PRIORITY_VALID_OFFSET 0x0000005c +#define RX_MPDU_INFO_PRIORITY_VALID_LSB 17 +#define RX_MPDU_INFO_PRIORITY_VALID_MSB 17 +#define RX_MPDU_INFO_PRIORITY_VALID_MASK 0x00020000 + +#define RX_MPDU_INFO_SRC_INFO_OFFSET 0x0000005c +#define RX_MPDU_INFO_SRC_INFO_LSB 18 +#define RX_MPDU_INFO_SRC_INFO_MSB 29 +#define RX_MPDU_INFO_SRC_INFO_MASK 0x3ffc0000 + +#define RX_MPDU_INFO_RESERVED_23A_OFFSET 0x0000005c +#define RX_MPDU_INFO_RESERVED_23A_LSB 30 +#define RX_MPDU_INFO_RESERVED_23A_MSB 30 +#define RX_MPDU_INFO_RESERVED_23A_MASK 0x40000000 + +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000006c +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_LSB 0 +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MSB 0 +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MASK 0x00000001 + +#define RX_MPDU_INFO_RESERVED_27A_OFFSET 0x0000006c +#define RX_MPDU_INFO_RESERVED_27A_LSB 1 +#define RX_MPDU_INFO_RESERVED_27A_MSB 31 +#define RX_MPDU_INFO_RESERVED_27A_MASK 0xfffffffe + +#define RX_MPDU_INFO_RESERVED_28A_OFFSET 0x00000070 +#define RX_MPDU_INFO_RESERVED_28A_LSB 0 +#define RX_MPDU_INFO_RESERVED_28A_MSB 31 +#define RX_MPDU_INFO_RESERVED_28A_MASK 0xffffffff + +#define RX_MPDU_INFO_RESERVED_29A_OFFSET 0x00000074 +#define RX_MPDU_INFO_RESERVED_29A_LSB 0 +#define RX_MPDU_INFO_RESERVED_29A_MSB 31 +#define RX_MPDU_INFO_RESERVED_29A_MASK 0xffffffff + +#endif diff --git a/hw/kiwi/v2/rx_mpdu_link_ptr.h b/hw/kiwi/v2/rx_mpdu_link_ptr.h new file mode 100644 index 000000000000..085ab5dbe756 --- /dev/null +++ b/hw/kiwi/v2/rx_mpdu_link_ptr.h @@ -0,0 +1,58 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MPDU_LINK_PTR_H_ +#define _RX_MPDU_LINK_PTR_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2 + +struct rx_mpdu_link_ptr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info mpdu_link_desc_addr_info; +#else + struct buffer_addr_info mpdu_link_desc_addr_info; +#endif +}; + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#endif diff --git a/hw/kiwi/v2/rx_mpdu_start.h b/hw/kiwi/v2/rx_mpdu_start.h new file mode 100644 index 000000000000..52bfd5dd6329 --- /dev/null +++ b/hw/kiwi/v2/rx_mpdu_start.h @@ -0,0 +1,620 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MPDU_START_H_ +#define _RX_MPDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_info.h" +#define NUM_OF_DWORDS_RX_MPDU_START 30 + +#define NUM_OF_QWORDS_RX_MPDU_START 15 + +struct rx_mpdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_mpdu_info rx_mpdu_info_details; +#else + struct rx_mpdu_info rx_mpdu_info_details; +#endif +}; + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x000000000000001f + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x0000000000000060 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x0000000000000080 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x0000000000000100 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x0000000000000200 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x0000000000000400 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x0000000000003800 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x000000000001c000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x0000000000020000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x0000000000040000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x0000000000080000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x0000000000100000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x0000000000200000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 22 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0x00000000ffc00000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MSB 23 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x0000000000ffff00 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000000000008 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 24 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MSB 24 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x0000000001000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET 0x0000000000000008 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB 25 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MSB 25 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK 0x0000000002000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB 26 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK 0x00000000fc000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET 0x0000000000000008 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MASK 0xffffffff00000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET 0x0000000000000010 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MASK 0x00000000ffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET 0x0000000000000010 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MASK 0xffffffff00000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MASK 0x00000000ffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MASK 0x0000000100000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 33 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 33 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x0000000200000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB 34 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MSB 37 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK 0x0000003c00000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 38 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 39 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB 42 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MSB 42 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK 0x0000040000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB 43 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MSB 46 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK 0x0000780000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_LSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MSB 50 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MASK 0x0007800000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB 51 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK 0xfff8000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK 0x00000000ffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 33 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000300000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB 34 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MSB 40 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK 0x000001fc00000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB 41 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MSB 41 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK 0x0000020000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB 42 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MSB 42 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK 0x0000040000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 43 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MSB 43 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x0000080000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 44 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MSB 44 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x0000100000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 45 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MSB 45 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x0000200000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_LSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_MSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_MASK 0x0000800000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK 0xffff000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK 0x000000000000ffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK 0x00000000ffff0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x0000000100000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 33 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MSB 33 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x0000000200000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 34 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MSB 34 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x0000000400000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 35 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MSB 35 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x0000000800000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 36 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MSB 36 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x0000001000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 37 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MSB 37 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x0000002000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 38 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MSB 38 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x0000004000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 39 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 39 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x0000008000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 40 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MSB 40 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x0000010000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 41 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MSB 41 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x0000020000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 42 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MSB 45 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x00003c0000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 46 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 46 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x0000400000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_LSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MASK 0x0000800000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_LSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MASK 0x0001000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_LSB 49 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MSB 49 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MASK 0x0002000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB 50 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MSB 50 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK 0x0004000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB 51 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MSB 51 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK 0x0008000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 52 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0xfff0000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK 0x00000000000000ff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK 0x0000000000000100 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK 0x0000000000000200 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MSB 11 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK 0x0000000000000c00 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x0000000000001000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x0000000000002000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x0000000000004000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x0000000000008000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MSB 27 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK 0x000000000fff0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB 28 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MSB 28 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK 0x0000000010000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB 29 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MSB 29 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK 0x0000000020000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB 30 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MSB 30 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK 0x0000000040000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK 0x0000000080000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MSB 45 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK 0x00003fff00000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB 46 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MSB 46 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK 0x0000400000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK 0x0000800000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x0001000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB 49 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MSB 49 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x0002000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB 50 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MSB 50 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK 0x0004000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_LSB 51 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MSB 51 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MASK 0x0008000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB 52 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MSB 52 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK 0x0010000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB 53 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MSB 53 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK 0x0020000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB 54 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MSB 54 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK 0x0040000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB 55 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MSB 55 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK 0x0080000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_LSB 56 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MSB 56 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MASK 0x0100000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB 57 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MSB 57 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x0200000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_LSB 58 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MSB 58 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MASK 0x0400000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB 59 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MSB 59 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK 0x0800000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB 60 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MSB 60 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK 0x1000000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_LSB 61 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MSB 61 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MASK 0x2000000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB 62 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MSB 62 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK 0x4000000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK 0x8000000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000038 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x000000000000ffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x0000000000000038 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0x00000000ffff0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000000000000038 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff00000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x0000000000000040 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x000000000000ffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x0000000000000040 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0x00000000ffff0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x0000000000000040 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff00000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x0000000000000048 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0x00000000ffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000000000000048 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff00000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000000000000048 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x0000000000000050 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0x00000000ffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x0000000000000050 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff00000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x0000000000000050 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x0000000000000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0x00000000ffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_OFFSET 0x0000000000000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MSB 39 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MASK 0x000000ff00000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000000000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_LSB 40 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MASK 0x0001ff0000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000000000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_LSB 49 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MSB 49 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MASK 0x0002000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000000000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_LSB 50 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MSB 61 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MASK 0x3ffc000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_OFFSET 0x0000000000000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_LSB 62 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MSB 62 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MASK 0x4000000000000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000000000000068 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MASK 0x0000000100000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000000000000068 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_LSB 33 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MASK 0xfffffffe00000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_OFFSET 0x0000000000000070 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_MASK 0x00000000ffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_OFFSET 0x0000000000000070 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/rx_msdu_desc_info.h b/hw/kiwi/v2/rx_msdu_desc_info.h new file mode 100644 index 000000000000..8d10087201b6 --- /dev/null +++ b/hw/kiwi/v2/rx_msdu_desc_info.h @@ -0,0 +1,154 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MSDU_DESC_INFO_H_ +#define _RX_MSDU_DESC_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 1 + +struct rx_msdu_desc_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t first_msdu_in_mpdu_flag : 1, + last_msdu_in_mpdu_flag : 1, + msdu_continuation : 1, + msdu_length : 14, + msdu_drop : 1, + sa_is_valid : 1, + da_is_valid : 1, + da_is_mcbc : 1, + l3_header_padding_msb : 1, + tcp_udp_chksum_fail : 1, + ip_chksum_fail : 1, + fr_ds : 1, + to_ds : 1, + intra_bss : 1, + dest_chip_id : 2, + decap_format : 2, + reserved_0a : 1; +#else + uint32_t reserved_0a : 1, + decap_format : 2, + dest_chip_id : 2, + intra_bss : 1, + to_ds : 1, + fr_ds : 1, + ip_chksum_fail : 1, + tcp_udp_chksum_fail : 1, + l3_header_padding_msb : 1, + da_is_mcbc : 1, + da_is_valid : 1, + sa_is_valid : 1, + msdu_drop : 1, + msdu_length : 14, + msdu_continuation : 1, + last_msdu_in_mpdu_flag : 1, + first_msdu_in_mpdu_flag : 1; +#endif +}; + +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3 +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MSB 16 +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_DESC_INFO_MSDU_DROP_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_MSDU_DROP_LSB 17 +#define RX_MSDU_DESC_INFO_MSDU_DROP_MSB 17 +#define RX_MSDU_DESC_INFO_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_SA_IS_VALID_LSB 18 +#define RX_MSDU_DESC_INFO_SA_IS_VALID_MSB 18 +#define RX_MSDU_DESC_INFO_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DA_IS_VALID_LSB 19 +#define RX_MSDU_DESC_INFO_DA_IS_VALID_MSB 19 +#define RX_MSDU_DESC_INFO_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_LSB 20 +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MSB 20 +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_DESC_INFO_FR_DS_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_FR_DS_LSB 24 +#define RX_MSDU_DESC_INFO_FR_DS_MSB 24 +#define RX_MSDU_DESC_INFO_FR_DS_MASK 0x01000000 + +#define RX_MSDU_DESC_INFO_TO_DS_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_TO_DS_LSB 25 +#define RX_MSDU_DESC_INFO_TO_DS_MSB 25 +#define RX_MSDU_DESC_INFO_TO_DS_MASK 0x02000000 + +#define RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_INTRA_BSS_LSB 26 +#define RX_MSDU_DESC_INFO_INTRA_BSS_MSB 26 +#define RX_MSDU_DESC_INFO_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_LSB 29 +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MSB 30 +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_DESC_INFO_RESERVED_0A_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_RESERVED_0A_LSB 31 +#define RX_MSDU_DESC_INFO_RESERVED_0A_MSB 31 +#define RX_MSDU_DESC_INFO_RESERVED_0A_MASK 0x80000000 + +#endif diff --git a/hw/kiwi/v2/rx_msdu_details.h b/hw/kiwi/v2/rx_msdu_details.h new file mode 100644 index 000000000000..372ad6eeb3c3 --- /dev/null +++ b/hw/kiwi/v2/rx_msdu_details.h @@ -0,0 +1,179 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MSDU_DETAILS_H_ +#define _RX_MSDU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_msdu_desc_info.h" +#include "rx_msdu_ext_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4 + +struct rx_msdu_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buffer_addr_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; +#else + struct buffer_addr_info buffer_addr_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; +#endif +}; + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000 + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#endif diff --git a/hw/kiwi/v2/rx_msdu_end.h b/hw/kiwi/v2/rx_msdu_end.h new file mode 100644 index 000000000000..d290d0100693 --- /dev/null +++ b/hw/kiwi/v2/rx_msdu_end.h @@ -0,0 +1,1103 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MSDU_END_H_ +#define _RX_MSDU_END_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MSDU_END 32 + +#define NUM_OF_QWORDS_RX_MSDU_END 16 + +struct rx_msdu_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t ip_hdr_chksum : 16, + reported_mpdu_length : 14, + reserved_1a : 2; + uint32_t reserved_2a : 8, + cce_super_rule : 6, + cce_classify_not_done_truncate : 1, + cce_classify_not_done_cce_dis : 1, + cumulative_l3_checksum : 16; + uint32_t rule_indication_31_0 : 32; + uint32_t ipv6_options_crc : 32; + uint32_t da_offset : 6, + sa_offset : 6, + da_offset_valid : 1, + sa_offset_valid : 1, + reserved_5a : 2, + l3_type : 16; + uint32_t rule_indication_63_32 : 32; + uint32_t tcp_seq_number : 32; + uint32_t tcp_ack_number : 32; + uint32_t tcp_flag : 9, + lro_eligible : 1, + reserved_9a : 6, + window_size : 16; + uint32_t sa_sw_peer_id : 16, + sa_idx_timeout : 1, + da_idx_timeout : 1, + to_ds : 1, + tid : 4, + sa_is_valid : 1, + da_is_valid : 1, + da_is_mcbc : 1, + l3_header_padding : 2, + first_msdu : 1, + last_msdu : 1, + fr_ds : 1, + ip_chksum_fail_copy : 1; + uint32_t sa_idx : 16, + da_idx_or_sw_peer_id : 16; + uint32_t msdu_drop : 1, + reo_destination_indication : 5, + flow_idx : 20, + use_ppe : 1, + __reserved_g_0003 : 2, + vlan_ctag_stripped : 1, + vlan_stag_stripped : 1, + fragment_flag : 1; + uint32_t fse_metadata : 32; + uint32_t cce_metadata : 16, + tcp_udp_chksum : 16; + uint32_t aggregation_count : 8, + flow_aggregation_continuation : 1, + fisa_timeout : 1, + tcp_udp_chksum_fail_copy : 1, + msdu_limit_error : 1, + flow_idx_timeout : 1, + flow_idx_invalid : 1, + cce_match : 1, + amsdu_parser_error : 1, + cumulative_ip_length : 16; + uint32_t key_id_octet : 8, + reserved_16a : 24; + uint32_t reserved_17a : 6, + service_code : 9, + priority_valid : 1, + intra_bss : 1, + dest_chip_id : 2, + multicast_echo : 1, + wds_learning_event : 1, + wds_roaming_event : 1, + wds_keep_alive_event : 1, + reserved_17b : 9; + uint32_t msdu_length : 14, + stbc : 1, + ipsec_esp : 1, + l3_offset : 7, + ipsec_ah : 1, + l4_offset : 8; + uint32_t msdu_number : 8, + decap_format : 2, + ipv4_proto : 1, + ipv6_proto : 1, + tcp_proto : 1, + udp_proto : 1, + ip_frag : 1, + tcp_only_ack : 1, + da_is_bcast_mcast : 1, + toeplitz_hash_sel : 2, + ip_fixed_header_valid : 1, + ip_extn_header_valid : 1, + tcp_udp_header_valid : 1, + mesh_control_present : 1, + ldpc : 1, + ip4_protocol_ip6_next_header : 8; + uint32_t vlan_ctag_ci : 16, + vlan_stag_ci : 16; + uint32_t peer_meta_data : 32; + uint32_t user_rssi : 8, + pkt_type : 4, + sgi : 2, + rate_mcs : 4, + receive_bandwidth : 3, + reception_type : 3, + mimo_ss_bitmap : 7, + msdu_done_copy : 1; + uint32_t flow_id_toeplitz : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t toeplitz_hash_2_or_4 : 32; + uint32_t reserved_28a : 16, + sa_15_0 : 16; + uint32_t sa_47_16 : 32; + uint32_t first_mpdu : 1, + reserved_30a : 1, + mcast_bcast : 1, + ast_index_not_found : 1, + ast_index_timeout : 1, + power_mgmt : 1, + non_qos : 1, + null_data : 1, + mgmt_type : 1, + ctrl_type : 1, + more_data : 1, + eosp : 1, + a_msdu_error : 1, + reserved_30b : 1, + order : 1, + wifi_parser_error : 1, + overflow_err : 1, + msdu_length_err : 1, + tcp_udp_chksum_fail : 1, + ip_chksum_fail : 1, + sa_idx_invalid : 1, + da_idx_invalid : 1, + amsdu_addr_mismatch : 1, + rx_in_tx_decrypt_byp : 1, + encrypt_required : 1, + directed : 1, + buffer_fragment : 1, + mpdu_length_err : 1, + tkip_mic_err : 1, + decrypt_err : 1, + unencrypted_frame_err : 1, + fcs_err : 1; + uint32_t reserved_31a : 10, + decrypt_status_code : 3, + rx_bitmap_not_updated : 1, + reserved_31b : 17, + msdu_done : 1; +#else + uint32_t phy_ppdu_id : 16, + reserved_0 : 7, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t reserved_1a : 2, + reported_mpdu_length : 14, + ip_hdr_chksum : 16; + uint32_t cumulative_l3_checksum : 16, + cce_classify_not_done_cce_dis : 1, + cce_classify_not_done_truncate : 1, + cce_super_rule : 6, + reserved_2a : 8; + uint32_t rule_indication_31_0 : 32; + uint32_t ipv6_options_crc : 32; + uint32_t l3_type : 16, + reserved_5a : 2, + sa_offset_valid : 1, + da_offset_valid : 1, + sa_offset : 6, + da_offset : 6; + uint32_t rule_indication_63_32 : 32; + uint32_t tcp_seq_number : 32; + uint32_t tcp_ack_number : 32; + uint32_t window_size : 16, + reserved_9a : 6, + lro_eligible : 1, + tcp_flag : 9; + uint32_t ip_chksum_fail_copy : 1, + fr_ds : 1, + last_msdu : 1, + first_msdu : 1, + l3_header_padding : 2, + da_is_mcbc : 1, + da_is_valid : 1, + sa_is_valid : 1, + tid : 4, + to_ds : 1, + da_idx_timeout : 1, + sa_idx_timeout : 1, + sa_sw_peer_id : 16; + uint32_t da_idx_or_sw_peer_id : 16, + sa_idx : 16; + uint32_t fragment_flag : 1, + vlan_stag_stripped : 1, + vlan_ctag_stripped : 1, + __reserved_g_0003 : 2, + use_ppe : 1, + flow_idx : 20, + reo_destination_indication : 5, + msdu_drop : 1; + uint32_t fse_metadata : 32; + uint32_t tcp_udp_chksum : 16, + cce_metadata : 16; + uint32_t cumulative_ip_length : 16, + amsdu_parser_error : 1, + cce_match : 1, + flow_idx_invalid : 1, + flow_idx_timeout : 1, + msdu_limit_error : 1, + tcp_udp_chksum_fail_copy : 1, + fisa_timeout : 1, + flow_aggregation_continuation : 1, + aggregation_count : 8; + uint32_t reserved_16a : 24, + key_id_octet : 8; + uint32_t reserved_17b : 9, + wds_keep_alive_event : 1, + wds_roaming_event : 1, + wds_learning_event : 1, + multicast_echo : 1, + dest_chip_id : 2, + intra_bss : 1, + priority_valid : 1, + service_code : 9, + reserved_17a : 6; + uint32_t l4_offset : 8, + ipsec_ah : 1, + l3_offset : 7, + ipsec_esp : 1, + stbc : 1, + msdu_length : 14; + uint32_t ip4_protocol_ip6_next_header : 8, + ldpc : 1, + mesh_control_present : 1, + tcp_udp_header_valid : 1, + ip_extn_header_valid : 1, + ip_fixed_header_valid : 1, + toeplitz_hash_sel : 2, + da_is_bcast_mcast : 1, + tcp_only_ack : 1, + ip_frag : 1, + udp_proto : 1, + tcp_proto : 1, + ipv6_proto : 1, + ipv4_proto : 1, + decap_format : 2, + msdu_number : 8; + uint32_t vlan_stag_ci : 16, + vlan_ctag_ci : 16; + uint32_t peer_meta_data : 32; + uint32_t msdu_done_copy : 1, + mimo_ss_bitmap : 7, + reception_type : 3, + receive_bandwidth : 3, + rate_mcs : 4, + sgi : 2, + pkt_type : 4, + user_rssi : 8; + uint32_t flow_id_toeplitz : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t toeplitz_hash_2_or_4 : 32; + uint32_t sa_15_0 : 16, + reserved_28a : 16; + uint32_t sa_47_16 : 32; + uint32_t fcs_err : 1, + unencrypted_frame_err : 1, + decrypt_err : 1, + tkip_mic_err : 1, + mpdu_length_err : 1, + buffer_fragment : 1, + directed : 1, + encrypt_required : 1, + rx_in_tx_decrypt_byp : 1, + amsdu_addr_mismatch : 1, + da_idx_invalid : 1, + sa_idx_invalid : 1, + ip_chksum_fail : 1, + tcp_udp_chksum_fail : 1, + msdu_length_err : 1, + overflow_err : 1, + wifi_parser_error : 1, + order : 1, + reserved_30b : 1, + a_msdu_error : 1, + eosp : 1, + more_data : 1, + ctrl_type : 1, + mgmt_type : 1, + null_data : 1, + non_qos : 1, + power_mgmt : 1, + ast_index_timeout : 1, + ast_index_not_found : 1, + mcast_bcast : 1, + reserved_30a : 1, + first_mpdu : 1; + uint32_t msdu_done : 1, + reserved_31b : 17, + rx_bitmap_not_updated : 1, + decrypt_status_code : 3, + reserved_31a : 10; +#endif +}; + +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 + +#define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 +#define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc + +#define RX_MSDU_END_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_MSDU_END_RESERVED_0_LSB 9 +#define RX_MSDU_END_RESERVED_0_MSB 15 +#define RX_MSDU_END_RESERVED_0_MASK 0x000000000000fe00 + +#define RX_MSDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_MSDU_END_PHY_PPDU_ID_LSB 16 +#define RX_MSDU_END_PHY_PPDU_ID_MSB 31 +#define RX_MSDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 + +#define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET 0x0000000000000000 +#define RX_MSDU_END_IP_HDR_CHKSUM_LSB 32 +#define RX_MSDU_END_IP_HDR_CHKSUM_MSB 47 +#define RX_MSDU_END_IP_HDR_CHKSUM_MASK 0x0000ffff00000000 + +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET 0x0000000000000000 +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB 48 +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB 61 +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK 0x3fff000000000000 + +#define RX_MSDU_END_RESERVED_1A_OFFSET 0x0000000000000000 +#define RX_MSDU_END_RESERVED_1A_LSB 62 +#define RX_MSDU_END_RESERVED_1A_MSB 63 +#define RX_MSDU_END_RESERVED_1A_MASK 0xc000000000000000 + +#define RX_MSDU_END_RESERVED_2A_OFFSET 0x0000000000000008 +#define RX_MSDU_END_RESERVED_2A_LSB 0 +#define RX_MSDU_END_RESERVED_2A_MSB 7 +#define RX_MSDU_END_RESERVED_2A_MASK 0x00000000000000ff + +#define RX_MSDU_END_CCE_SUPER_RULE_OFFSET 0x0000000000000008 +#define RX_MSDU_END_CCE_SUPER_RULE_LSB 8 +#define RX_MSDU_END_CCE_SUPER_RULE_MSB 13 +#define RX_MSDU_END_CCE_SUPER_RULE_MASK 0x0000000000003f00 + +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x0000000000000008 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB 14 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x0000000000004000 + +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x0000000000000008 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB 15 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x0000000000008000 + +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET 0x0000000000000008 +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB 16 +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB 31 +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK 0x00000000ffff0000 + +#define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET 0x0000000000000008 +#define RX_MSDU_END_RULE_INDICATION_31_0_LSB 32 +#define RX_MSDU_END_RULE_INDICATION_31_0_MSB 63 +#define RX_MSDU_END_RULE_INDICATION_31_0_MASK 0xffffffff00000000 + +#define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET 0x0000000000000010 +#define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB 0 +#define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB 31 +#define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK 0x00000000ffffffff + +#define RX_MSDU_END_DA_OFFSET_OFFSET 0x0000000000000010 +#define RX_MSDU_END_DA_OFFSET_LSB 32 +#define RX_MSDU_END_DA_OFFSET_MSB 37 +#define RX_MSDU_END_DA_OFFSET_MASK 0x0000003f00000000 + +#define RX_MSDU_END_SA_OFFSET_OFFSET 0x0000000000000010 +#define RX_MSDU_END_SA_OFFSET_LSB 38 +#define RX_MSDU_END_SA_OFFSET_MSB 43 +#define RX_MSDU_END_SA_OFFSET_MASK 0x00000fc000000000 + +#define RX_MSDU_END_DA_OFFSET_VALID_OFFSET 0x0000000000000010 +#define RX_MSDU_END_DA_OFFSET_VALID_LSB 44 +#define RX_MSDU_END_DA_OFFSET_VALID_MSB 44 +#define RX_MSDU_END_DA_OFFSET_VALID_MASK 0x0000100000000000 + +#define RX_MSDU_END_SA_OFFSET_VALID_OFFSET 0x0000000000000010 +#define RX_MSDU_END_SA_OFFSET_VALID_LSB 45 +#define RX_MSDU_END_SA_OFFSET_VALID_MSB 45 +#define RX_MSDU_END_SA_OFFSET_VALID_MASK 0x0000200000000000 + +#define RX_MSDU_END_RESERVED_5A_OFFSET 0x0000000000000010 +#define RX_MSDU_END_RESERVED_5A_LSB 46 +#define RX_MSDU_END_RESERVED_5A_MSB 47 +#define RX_MSDU_END_RESERVED_5A_MASK 0x0000c00000000000 + +#define RX_MSDU_END_L3_TYPE_OFFSET 0x0000000000000010 +#define RX_MSDU_END_L3_TYPE_LSB 48 +#define RX_MSDU_END_L3_TYPE_MSB 63 +#define RX_MSDU_END_L3_TYPE_MASK 0xffff000000000000 + +#define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET 0x0000000000000018 +#define RX_MSDU_END_RULE_INDICATION_63_32_LSB 0 +#define RX_MSDU_END_RULE_INDICATION_63_32_MSB 31 +#define RX_MSDU_END_RULE_INDICATION_63_32_MASK 0x00000000ffffffff + +#define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET 0x0000000000000018 +#define RX_MSDU_END_TCP_SEQ_NUMBER_LSB 32 +#define RX_MSDU_END_TCP_SEQ_NUMBER_MSB 63 +#define RX_MSDU_END_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 + +#define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET 0x0000000000000020 +#define RX_MSDU_END_TCP_ACK_NUMBER_LSB 0 +#define RX_MSDU_END_TCP_ACK_NUMBER_MSB 31 +#define RX_MSDU_END_TCP_ACK_NUMBER_MASK 0x00000000ffffffff + +#define RX_MSDU_END_TCP_FLAG_OFFSET 0x0000000000000020 +#define RX_MSDU_END_TCP_FLAG_LSB 32 +#define RX_MSDU_END_TCP_FLAG_MSB 40 +#define RX_MSDU_END_TCP_FLAG_MASK 0x000001ff00000000 + +#define RX_MSDU_END_LRO_ELIGIBLE_OFFSET 0x0000000000000020 +#define RX_MSDU_END_LRO_ELIGIBLE_LSB 41 +#define RX_MSDU_END_LRO_ELIGIBLE_MSB 41 +#define RX_MSDU_END_LRO_ELIGIBLE_MASK 0x0000020000000000 + +#define RX_MSDU_END_RESERVED_9A_OFFSET 0x0000000000000020 +#define RX_MSDU_END_RESERVED_9A_LSB 42 +#define RX_MSDU_END_RESERVED_9A_MSB 47 +#define RX_MSDU_END_RESERVED_9A_MASK 0x0000fc0000000000 + +#define RX_MSDU_END_WINDOW_SIZE_OFFSET 0x0000000000000020 +#define RX_MSDU_END_WINDOW_SIZE_LSB 48 +#define RX_MSDU_END_WINDOW_SIZE_MSB 63 +#define RX_MSDU_END_WINDOW_SIZE_MASK 0xffff000000000000 + +#define RX_MSDU_END_SA_SW_PEER_ID_OFFSET 0x0000000000000028 +#define RX_MSDU_END_SA_SW_PEER_ID_LSB 0 +#define RX_MSDU_END_SA_SW_PEER_ID_MSB 15 +#define RX_MSDU_END_SA_SW_PEER_ID_MASK 0x000000000000ffff + +#define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET 0x0000000000000028 +#define RX_MSDU_END_SA_IDX_TIMEOUT_LSB 16 +#define RX_MSDU_END_SA_IDX_TIMEOUT_MSB 16 +#define RX_MSDU_END_SA_IDX_TIMEOUT_MASK 0x0000000000010000 + +#define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET 0x0000000000000028 +#define RX_MSDU_END_DA_IDX_TIMEOUT_LSB 17 +#define RX_MSDU_END_DA_IDX_TIMEOUT_MSB 17 +#define RX_MSDU_END_DA_IDX_TIMEOUT_MASK 0x0000000000020000 + +#define RX_MSDU_END_TO_DS_OFFSET 0x0000000000000028 +#define RX_MSDU_END_TO_DS_LSB 18 +#define RX_MSDU_END_TO_DS_MSB 18 +#define RX_MSDU_END_TO_DS_MASK 0x0000000000040000 + +#define RX_MSDU_END_TID_OFFSET 0x0000000000000028 +#define RX_MSDU_END_TID_LSB 19 +#define RX_MSDU_END_TID_MSB 22 +#define RX_MSDU_END_TID_MASK 0x0000000000780000 + +#define RX_MSDU_END_SA_IS_VALID_OFFSET 0x0000000000000028 +#define RX_MSDU_END_SA_IS_VALID_LSB 23 +#define RX_MSDU_END_SA_IS_VALID_MSB 23 +#define RX_MSDU_END_SA_IS_VALID_MASK 0x0000000000800000 + +#define RX_MSDU_END_DA_IS_VALID_OFFSET 0x0000000000000028 +#define RX_MSDU_END_DA_IS_VALID_LSB 24 +#define RX_MSDU_END_DA_IS_VALID_MSB 24 +#define RX_MSDU_END_DA_IS_VALID_MASK 0x0000000001000000 + +#define RX_MSDU_END_DA_IS_MCBC_OFFSET 0x0000000000000028 +#define RX_MSDU_END_DA_IS_MCBC_LSB 25 +#define RX_MSDU_END_DA_IS_MCBC_MSB 25 +#define RX_MSDU_END_DA_IS_MCBC_MASK 0x0000000002000000 + +#define RX_MSDU_END_L3_HEADER_PADDING_OFFSET 0x0000000000000028 +#define RX_MSDU_END_L3_HEADER_PADDING_LSB 26 +#define RX_MSDU_END_L3_HEADER_PADDING_MSB 27 +#define RX_MSDU_END_L3_HEADER_PADDING_MASK 0x000000000c000000 + +#define RX_MSDU_END_FIRST_MSDU_OFFSET 0x0000000000000028 +#define RX_MSDU_END_FIRST_MSDU_LSB 28 +#define RX_MSDU_END_FIRST_MSDU_MSB 28 +#define RX_MSDU_END_FIRST_MSDU_MASK 0x0000000010000000 + +#define RX_MSDU_END_LAST_MSDU_OFFSET 0x0000000000000028 +#define RX_MSDU_END_LAST_MSDU_LSB 29 +#define RX_MSDU_END_LAST_MSDU_MSB 29 +#define RX_MSDU_END_LAST_MSDU_MASK 0x0000000020000000 + +#define RX_MSDU_END_FR_DS_OFFSET 0x0000000000000028 +#define RX_MSDU_END_FR_DS_LSB 30 +#define RX_MSDU_END_FR_DS_MSB 30 +#define RX_MSDU_END_FR_DS_MASK 0x0000000040000000 + +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000028 +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB 31 +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB 31 +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK 0x0000000080000000 + +#define RX_MSDU_END_SA_IDX_OFFSET 0x0000000000000028 +#define RX_MSDU_END_SA_IDX_LSB 32 +#define RX_MSDU_END_SA_IDX_MSB 47 +#define RX_MSDU_END_SA_IDX_MASK 0x0000ffff00000000 + +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000000000000028 +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB 48 +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB 63 +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK 0xffff000000000000 + +#define RX_MSDU_END_MSDU_DROP_OFFSET 0x0000000000000030 +#define RX_MSDU_END_MSDU_DROP_LSB 0 +#define RX_MSDU_END_MSDU_DROP_MSB 0 +#define RX_MSDU_END_MSDU_DROP_MASK 0x0000000000000001 + +#define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000030 +#define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB 1 +#define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB 5 +#define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK 0x000000000000003e + +#define RX_MSDU_END_FLOW_IDX_OFFSET 0x0000000000000030 +#define RX_MSDU_END_FLOW_IDX_LSB 6 +#define RX_MSDU_END_FLOW_IDX_MSB 25 +#define RX_MSDU_END_FLOW_IDX_MASK 0x0000000003ffffc0 + +#define RX_MSDU_END_USE_PPE_OFFSET 0x0000000000000030 +#define RX_MSDU_END_USE_PPE_LSB 26 +#define RX_MSDU_END_USE_PPE_MSB 26 +#define RX_MSDU_END_USE_PPE_MASK 0x0000000004000000 + +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_OFFSET 0x0000000000000030 +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_LSB 29 +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MSB 29 +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MASK 0x0000000020000000 + +#define RX_MSDU_END_VLAN_STAG_STRIPPED_OFFSET 0x0000000000000030 +#define RX_MSDU_END_VLAN_STAG_STRIPPED_LSB 30 +#define RX_MSDU_END_VLAN_STAG_STRIPPED_MSB 30 +#define RX_MSDU_END_VLAN_STAG_STRIPPED_MASK 0x0000000040000000 + +#define RX_MSDU_END_FRAGMENT_FLAG_OFFSET 0x0000000000000030 +#define RX_MSDU_END_FRAGMENT_FLAG_LSB 31 +#define RX_MSDU_END_FRAGMENT_FLAG_MSB 31 +#define RX_MSDU_END_FRAGMENT_FLAG_MASK 0x0000000080000000 + +#define RX_MSDU_END_FSE_METADATA_OFFSET 0x0000000000000030 +#define RX_MSDU_END_FSE_METADATA_LSB 32 +#define RX_MSDU_END_FSE_METADATA_MSB 63 +#define RX_MSDU_END_FSE_METADATA_MASK 0xffffffff00000000 + +#define RX_MSDU_END_CCE_METADATA_OFFSET 0x0000000000000038 +#define RX_MSDU_END_CCE_METADATA_LSB 0 +#define RX_MSDU_END_CCE_METADATA_MSB 15 +#define RX_MSDU_END_CCE_METADATA_MASK 0x000000000000ffff + +#define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET 0x0000000000000038 +#define RX_MSDU_END_TCP_UDP_CHKSUM_LSB 16 +#define RX_MSDU_END_TCP_UDP_CHKSUM_MSB 31 +#define RX_MSDU_END_TCP_UDP_CHKSUM_MASK 0x00000000ffff0000 + +#define RX_MSDU_END_AGGREGATION_COUNT_OFFSET 0x0000000000000038 +#define RX_MSDU_END_AGGREGATION_COUNT_LSB 32 +#define RX_MSDU_END_AGGREGATION_COUNT_MSB 39 +#define RX_MSDU_END_AGGREGATION_COUNT_MASK 0x000000ff00000000 + +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000000000000038 +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB 40 +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB 40 +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK 0x0000010000000000 + +#define RX_MSDU_END_FISA_TIMEOUT_OFFSET 0x0000000000000038 +#define RX_MSDU_END_FISA_TIMEOUT_LSB 41 +#define RX_MSDU_END_FISA_TIMEOUT_MSB 41 +#define RX_MSDU_END_FISA_TIMEOUT_MASK 0x0000020000000000 + +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000038 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB 42 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB 42 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK 0x0000040000000000 + +#define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000038 +#define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB 43 +#define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB 43 +#define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK 0x0000080000000000 + +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000038 +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB 44 +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB 44 +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK 0x0000100000000000 + +#define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET 0x0000000000000038 +#define RX_MSDU_END_FLOW_IDX_INVALID_LSB 45 +#define RX_MSDU_END_FLOW_IDX_INVALID_MSB 45 +#define RX_MSDU_END_FLOW_IDX_INVALID_MASK 0x0000200000000000 + +#define RX_MSDU_END_CCE_MATCH_OFFSET 0x0000000000000038 +#define RX_MSDU_END_CCE_MATCH_LSB 46 +#define RX_MSDU_END_CCE_MATCH_MSB 46 +#define RX_MSDU_END_CCE_MATCH_MASK 0x0000400000000000 + +#define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000038 +#define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB 47 +#define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB 47 +#define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK 0x0000800000000000 + +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET 0x0000000000000038 +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB 48 +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB 63 +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK 0xffff000000000000 + +#define RX_MSDU_END_KEY_ID_OCTET_OFFSET 0x0000000000000040 +#define RX_MSDU_END_KEY_ID_OCTET_LSB 0 +#define RX_MSDU_END_KEY_ID_OCTET_MSB 7 +#define RX_MSDU_END_KEY_ID_OCTET_MASK 0x00000000000000ff + +#define RX_MSDU_END_RESERVED_16A_OFFSET 0x0000000000000040 +#define RX_MSDU_END_RESERVED_16A_LSB 8 +#define RX_MSDU_END_RESERVED_16A_MSB 31 +#define RX_MSDU_END_RESERVED_16A_MASK 0x00000000ffffff00 + +#define RX_MSDU_END_RESERVED_17A_OFFSET 0x0000000000000040 +#define RX_MSDU_END_RESERVED_17A_LSB 32 +#define RX_MSDU_END_RESERVED_17A_MSB 37 +#define RX_MSDU_END_RESERVED_17A_MASK 0x0000003f00000000 + +#define RX_MSDU_END_SERVICE_CODE_OFFSET 0x0000000000000040 +#define RX_MSDU_END_SERVICE_CODE_LSB 38 +#define RX_MSDU_END_SERVICE_CODE_MSB 46 +#define RX_MSDU_END_SERVICE_CODE_MASK 0x00007fc000000000 + +#define RX_MSDU_END_PRIORITY_VALID_OFFSET 0x0000000000000040 +#define RX_MSDU_END_PRIORITY_VALID_LSB 47 +#define RX_MSDU_END_PRIORITY_VALID_MSB 47 +#define RX_MSDU_END_PRIORITY_VALID_MASK 0x0000800000000000 + +#define RX_MSDU_END_INTRA_BSS_OFFSET 0x0000000000000040 +#define RX_MSDU_END_INTRA_BSS_LSB 48 +#define RX_MSDU_END_INTRA_BSS_MSB 48 +#define RX_MSDU_END_INTRA_BSS_MASK 0x0001000000000000 + +#define RX_MSDU_END_DEST_CHIP_ID_OFFSET 0x0000000000000040 +#define RX_MSDU_END_DEST_CHIP_ID_LSB 49 +#define RX_MSDU_END_DEST_CHIP_ID_MSB 50 +#define RX_MSDU_END_DEST_CHIP_ID_MASK 0x0006000000000000 + +#define RX_MSDU_END_MULTICAST_ECHO_OFFSET 0x0000000000000040 +#define RX_MSDU_END_MULTICAST_ECHO_LSB 51 +#define RX_MSDU_END_MULTICAST_ECHO_MSB 51 +#define RX_MSDU_END_MULTICAST_ECHO_MASK 0x0008000000000000 + +#define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET 0x0000000000000040 +#define RX_MSDU_END_WDS_LEARNING_EVENT_LSB 52 +#define RX_MSDU_END_WDS_LEARNING_EVENT_MSB 52 +#define RX_MSDU_END_WDS_LEARNING_EVENT_MASK 0x0010000000000000 + +#define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET 0x0000000000000040 +#define RX_MSDU_END_WDS_ROAMING_EVENT_LSB 53 +#define RX_MSDU_END_WDS_ROAMING_EVENT_MSB 53 +#define RX_MSDU_END_WDS_ROAMING_EVENT_MASK 0x0020000000000000 + +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET 0x0000000000000040 +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB 54 +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB 54 +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK 0x0040000000000000 + +#define RX_MSDU_END_RESERVED_17B_OFFSET 0x0000000000000040 +#define RX_MSDU_END_RESERVED_17B_LSB 55 +#define RX_MSDU_END_RESERVED_17B_MSB 63 +#define RX_MSDU_END_RESERVED_17B_MASK 0xff80000000000000 + +#define RX_MSDU_END_MSDU_LENGTH_OFFSET 0x0000000000000048 +#define RX_MSDU_END_MSDU_LENGTH_LSB 0 +#define RX_MSDU_END_MSDU_LENGTH_MSB 13 +#define RX_MSDU_END_MSDU_LENGTH_MASK 0x0000000000003fff + +#define RX_MSDU_END_STBC_OFFSET 0x0000000000000048 +#define RX_MSDU_END_STBC_LSB 14 +#define RX_MSDU_END_STBC_MSB 14 +#define RX_MSDU_END_STBC_MASK 0x0000000000004000 + +#define RX_MSDU_END_IPSEC_ESP_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IPSEC_ESP_LSB 15 +#define RX_MSDU_END_IPSEC_ESP_MSB 15 +#define RX_MSDU_END_IPSEC_ESP_MASK 0x0000000000008000 + +#define RX_MSDU_END_L3_OFFSET_OFFSET 0x0000000000000048 +#define RX_MSDU_END_L3_OFFSET_LSB 16 +#define RX_MSDU_END_L3_OFFSET_MSB 22 +#define RX_MSDU_END_L3_OFFSET_MASK 0x00000000007f0000 + +#define RX_MSDU_END_IPSEC_AH_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IPSEC_AH_LSB 23 +#define RX_MSDU_END_IPSEC_AH_MSB 23 +#define RX_MSDU_END_IPSEC_AH_MASK 0x0000000000800000 + +#define RX_MSDU_END_L4_OFFSET_OFFSET 0x0000000000000048 +#define RX_MSDU_END_L4_OFFSET_LSB 24 +#define RX_MSDU_END_L4_OFFSET_MSB 31 +#define RX_MSDU_END_L4_OFFSET_MASK 0x00000000ff000000 + +#define RX_MSDU_END_MSDU_NUMBER_OFFSET 0x0000000000000048 +#define RX_MSDU_END_MSDU_NUMBER_LSB 32 +#define RX_MSDU_END_MSDU_NUMBER_MSB 39 +#define RX_MSDU_END_MSDU_NUMBER_MASK 0x000000ff00000000 + +#define RX_MSDU_END_DECAP_FORMAT_OFFSET 0x0000000000000048 +#define RX_MSDU_END_DECAP_FORMAT_LSB 40 +#define RX_MSDU_END_DECAP_FORMAT_MSB 41 +#define RX_MSDU_END_DECAP_FORMAT_MASK 0x0000030000000000 + +#define RX_MSDU_END_IPV4_PROTO_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IPV4_PROTO_LSB 42 +#define RX_MSDU_END_IPV4_PROTO_MSB 42 +#define RX_MSDU_END_IPV4_PROTO_MASK 0x0000040000000000 + +#define RX_MSDU_END_IPV6_PROTO_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IPV6_PROTO_LSB 43 +#define RX_MSDU_END_IPV6_PROTO_MSB 43 +#define RX_MSDU_END_IPV6_PROTO_MASK 0x0000080000000000 + +#define RX_MSDU_END_TCP_PROTO_OFFSET 0x0000000000000048 +#define RX_MSDU_END_TCP_PROTO_LSB 44 +#define RX_MSDU_END_TCP_PROTO_MSB 44 +#define RX_MSDU_END_TCP_PROTO_MASK 0x0000100000000000 + +#define RX_MSDU_END_UDP_PROTO_OFFSET 0x0000000000000048 +#define RX_MSDU_END_UDP_PROTO_LSB 45 +#define RX_MSDU_END_UDP_PROTO_MSB 45 +#define RX_MSDU_END_UDP_PROTO_MASK 0x0000200000000000 + +#define RX_MSDU_END_IP_FRAG_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IP_FRAG_LSB 46 +#define RX_MSDU_END_IP_FRAG_MSB 46 +#define RX_MSDU_END_IP_FRAG_MASK 0x0000400000000000 + +#define RX_MSDU_END_TCP_ONLY_ACK_OFFSET 0x0000000000000048 +#define RX_MSDU_END_TCP_ONLY_ACK_LSB 47 +#define RX_MSDU_END_TCP_ONLY_ACK_MSB 47 +#define RX_MSDU_END_TCP_ONLY_ACK_MASK 0x0000800000000000 + +#define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000048 +#define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB 48 +#define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB 48 +#define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK 0x0001000000000000 + +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000048 +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB 49 +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB 50 +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK 0x0006000000000000 + +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB 51 +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB 51 +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK 0x0008000000000000 + +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB 52 +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB 52 +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK 0x0010000000000000 + +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000048 +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB 53 +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB 53 +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK 0x0020000000000000 + +#define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000048 +#define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB 54 +#define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB 54 +#define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK 0x0040000000000000 + +#define RX_MSDU_END_LDPC_OFFSET 0x0000000000000048 +#define RX_MSDU_END_LDPC_LSB 55 +#define RX_MSDU_END_LDPC_MSB 55 +#define RX_MSDU_END_LDPC_MASK 0x0080000000000000 + +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 56 +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 63 +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff00000000000000 + +#define RX_MSDU_END_VLAN_CTAG_CI_OFFSET 0x0000000000000050 +#define RX_MSDU_END_VLAN_CTAG_CI_LSB 0 +#define RX_MSDU_END_VLAN_CTAG_CI_MSB 15 +#define RX_MSDU_END_VLAN_CTAG_CI_MASK 0x000000000000ffff + +#define RX_MSDU_END_VLAN_STAG_CI_OFFSET 0x0000000000000050 +#define RX_MSDU_END_VLAN_STAG_CI_LSB 16 +#define RX_MSDU_END_VLAN_STAG_CI_MSB 31 +#define RX_MSDU_END_VLAN_STAG_CI_MASK 0x00000000ffff0000 + +#define RX_MSDU_END_PEER_META_DATA_OFFSET 0x0000000000000050 +#define RX_MSDU_END_PEER_META_DATA_LSB 32 +#define RX_MSDU_END_PEER_META_DATA_MSB 63 +#define RX_MSDU_END_PEER_META_DATA_MASK 0xffffffff00000000 + +#define RX_MSDU_END_USER_RSSI_OFFSET 0x0000000000000058 +#define RX_MSDU_END_USER_RSSI_LSB 0 +#define RX_MSDU_END_USER_RSSI_MSB 7 +#define RX_MSDU_END_USER_RSSI_MASK 0x00000000000000ff + +#define RX_MSDU_END_PKT_TYPE_OFFSET 0x0000000000000058 +#define RX_MSDU_END_PKT_TYPE_LSB 8 +#define RX_MSDU_END_PKT_TYPE_MSB 11 +#define RX_MSDU_END_PKT_TYPE_MASK 0x0000000000000f00 + +#define RX_MSDU_END_SGI_OFFSET 0x0000000000000058 +#define RX_MSDU_END_SGI_LSB 12 +#define RX_MSDU_END_SGI_MSB 13 +#define RX_MSDU_END_SGI_MASK 0x0000000000003000 + +#define RX_MSDU_END_RATE_MCS_OFFSET 0x0000000000000058 +#define RX_MSDU_END_RATE_MCS_LSB 14 +#define RX_MSDU_END_RATE_MCS_MSB 17 +#define RX_MSDU_END_RATE_MCS_MASK 0x000000000003c000 + +#define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000058 +#define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB 18 +#define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB 20 +#define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK 0x00000000001c0000 + +#define RX_MSDU_END_RECEPTION_TYPE_OFFSET 0x0000000000000058 +#define RX_MSDU_END_RECEPTION_TYPE_LSB 21 +#define RX_MSDU_END_RECEPTION_TYPE_MSB 23 +#define RX_MSDU_END_RECEPTION_TYPE_MASK 0x0000000000e00000 + +#define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET 0x0000000000000058 +#define RX_MSDU_END_MIMO_SS_BITMAP_LSB 24 +#define RX_MSDU_END_MIMO_SS_BITMAP_MSB 30 +#define RX_MSDU_END_MIMO_SS_BITMAP_MASK 0x000000007f000000 + +#define RX_MSDU_END_MSDU_DONE_COPY_OFFSET 0x0000000000000058 +#define RX_MSDU_END_MSDU_DONE_COPY_LSB 31 +#define RX_MSDU_END_MSDU_DONE_COPY_MSB 31 +#define RX_MSDU_END_MSDU_DONE_COPY_MASK 0x0000000080000000 + +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000058 +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB 32 +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB 63 +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK 0xffffffff00000000 + +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000060 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB 0 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB 31 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK 0x00000000ffffffff + +#define RX_MSDU_END_SW_PHY_META_DATA_OFFSET 0x0000000000000060 +#define RX_MSDU_END_SW_PHY_META_DATA_LSB 32 +#define RX_MSDU_END_SW_PHY_META_DATA_MSB 63 +#define RX_MSDU_END_SW_PHY_META_DATA_MASK 0xffffffff00000000 + +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000068 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff + +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000068 +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB 32 +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB 63 +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000 + +#define RX_MSDU_END_RESERVED_28A_OFFSET 0x0000000000000070 +#define RX_MSDU_END_RESERVED_28A_LSB 0 +#define RX_MSDU_END_RESERVED_28A_MSB 15 +#define RX_MSDU_END_RESERVED_28A_MASK 0x000000000000ffff + +#define RX_MSDU_END_SA_15_0_OFFSET 0x0000000000000070 +#define RX_MSDU_END_SA_15_0_LSB 16 +#define RX_MSDU_END_SA_15_0_MSB 31 +#define RX_MSDU_END_SA_15_0_MASK 0x00000000ffff0000 + +#define RX_MSDU_END_SA_47_16_OFFSET 0x0000000000000070 +#define RX_MSDU_END_SA_47_16_LSB 32 +#define RX_MSDU_END_SA_47_16_MSB 63 +#define RX_MSDU_END_SA_47_16_MASK 0xffffffff00000000 + +#define RX_MSDU_END_FIRST_MPDU_OFFSET 0x0000000000000078 +#define RX_MSDU_END_FIRST_MPDU_LSB 0 +#define RX_MSDU_END_FIRST_MPDU_MSB 0 +#define RX_MSDU_END_FIRST_MPDU_MASK 0x0000000000000001 + +#define RX_MSDU_END_RESERVED_30A_OFFSET 0x0000000000000078 +#define RX_MSDU_END_RESERVED_30A_LSB 1 +#define RX_MSDU_END_RESERVED_30A_MSB 1 +#define RX_MSDU_END_RESERVED_30A_MASK 0x0000000000000002 + +#define RX_MSDU_END_MCAST_BCAST_OFFSET 0x0000000000000078 +#define RX_MSDU_END_MCAST_BCAST_LSB 2 +#define RX_MSDU_END_MCAST_BCAST_MSB 2 +#define RX_MSDU_END_MCAST_BCAST_MASK 0x0000000000000004 + +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000078 +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB 3 +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB 3 +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK 0x0000000000000008 + +#define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000078 +#define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB 4 +#define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB 4 +#define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK 0x0000000000000010 + +#define RX_MSDU_END_POWER_MGMT_OFFSET 0x0000000000000078 +#define RX_MSDU_END_POWER_MGMT_LSB 5 +#define RX_MSDU_END_POWER_MGMT_MSB 5 +#define RX_MSDU_END_POWER_MGMT_MASK 0x0000000000000020 + +#define RX_MSDU_END_NON_QOS_OFFSET 0x0000000000000078 +#define RX_MSDU_END_NON_QOS_LSB 6 +#define RX_MSDU_END_NON_QOS_MSB 6 +#define RX_MSDU_END_NON_QOS_MASK 0x0000000000000040 + +#define RX_MSDU_END_NULL_DATA_OFFSET 0x0000000000000078 +#define RX_MSDU_END_NULL_DATA_LSB 7 +#define RX_MSDU_END_NULL_DATA_MSB 7 +#define RX_MSDU_END_NULL_DATA_MASK 0x0000000000000080 + +#define RX_MSDU_END_MGMT_TYPE_OFFSET 0x0000000000000078 +#define RX_MSDU_END_MGMT_TYPE_LSB 8 +#define RX_MSDU_END_MGMT_TYPE_MSB 8 +#define RX_MSDU_END_MGMT_TYPE_MASK 0x0000000000000100 + +#define RX_MSDU_END_CTRL_TYPE_OFFSET 0x0000000000000078 +#define RX_MSDU_END_CTRL_TYPE_LSB 9 +#define RX_MSDU_END_CTRL_TYPE_MSB 9 +#define RX_MSDU_END_CTRL_TYPE_MASK 0x0000000000000200 + +#define RX_MSDU_END_MORE_DATA_OFFSET 0x0000000000000078 +#define RX_MSDU_END_MORE_DATA_LSB 10 +#define RX_MSDU_END_MORE_DATA_MSB 10 +#define RX_MSDU_END_MORE_DATA_MASK 0x0000000000000400 + +#define RX_MSDU_END_EOSP_OFFSET 0x0000000000000078 +#define RX_MSDU_END_EOSP_LSB 11 +#define RX_MSDU_END_EOSP_MSB 11 +#define RX_MSDU_END_EOSP_MASK 0x0000000000000800 + +#define RX_MSDU_END_A_MSDU_ERROR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_A_MSDU_ERROR_LSB 12 +#define RX_MSDU_END_A_MSDU_ERROR_MSB 12 +#define RX_MSDU_END_A_MSDU_ERROR_MASK 0x0000000000001000 + +#define RX_MSDU_END_RESERVED_30B_OFFSET 0x0000000000000078 +#define RX_MSDU_END_RESERVED_30B_LSB 13 +#define RX_MSDU_END_RESERVED_30B_MSB 13 +#define RX_MSDU_END_RESERVED_30B_MASK 0x0000000000002000 + +#define RX_MSDU_END_ORDER_OFFSET 0x0000000000000078 +#define RX_MSDU_END_ORDER_LSB 14 +#define RX_MSDU_END_ORDER_MSB 14 +#define RX_MSDU_END_ORDER_MASK 0x0000000000004000 + +#define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_WIFI_PARSER_ERROR_LSB 15 +#define RX_MSDU_END_WIFI_PARSER_ERROR_MSB 15 +#define RX_MSDU_END_WIFI_PARSER_ERROR_MASK 0x0000000000008000 + +#define RX_MSDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_OVERFLOW_ERR_LSB 16 +#define RX_MSDU_END_OVERFLOW_ERR_MSB 16 +#define RX_MSDU_END_OVERFLOW_ERR_MASK 0x0000000000010000 + +#define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_MSDU_LENGTH_ERR_LSB 17 +#define RX_MSDU_END_MSDU_LENGTH_ERR_MSB 17 +#define RX_MSDU_END_MSDU_LENGTH_ERR_MASK 0x0000000000020000 + +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000078 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB 18 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB 18 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK 0x0000000000040000 + +#define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET 0x0000000000000078 +#define RX_MSDU_END_IP_CHKSUM_FAIL_LSB 19 +#define RX_MSDU_END_IP_CHKSUM_FAIL_MSB 19 +#define RX_MSDU_END_IP_CHKSUM_FAIL_MASK 0x0000000000080000 + +#define RX_MSDU_END_SA_IDX_INVALID_OFFSET 0x0000000000000078 +#define RX_MSDU_END_SA_IDX_INVALID_LSB 20 +#define RX_MSDU_END_SA_IDX_INVALID_MSB 20 +#define RX_MSDU_END_SA_IDX_INVALID_MASK 0x0000000000100000 + +#define RX_MSDU_END_DA_IDX_INVALID_OFFSET 0x0000000000000078 +#define RX_MSDU_END_DA_IDX_INVALID_LSB 21 +#define RX_MSDU_END_DA_IDX_INVALID_MSB 21 +#define RX_MSDU_END_DA_IDX_INVALID_MASK 0x0000000000200000 + +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_OFFSET 0x0000000000000078 +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_LSB 22 +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MSB 22 +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MASK 0x0000000000400000 + +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000078 +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB 23 +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB 23 +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000000000800000 + +#define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET 0x0000000000000078 +#define RX_MSDU_END_ENCRYPT_REQUIRED_LSB 24 +#define RX_MSDU_END_ENCRYPT_REQUIRED_MSB 24 +#define RX_MSDU_END_ENCRYPT_REQUIRED_MASK 0x0000000001000000 + +#define RX_MSDU_END_DIRECTED_OFFSET 0x0000000000000078 +#define RX_MSDU_END_DIRECTED_LSB 25 +#define RX_MSDU_END_DIRECTED_MSB 25 +#define RX_MSDU_END_DIRECTED_MASK 0x0000000002000000 + +#define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET 0x0000000000000078 +#define RX_MSDU_END_BUFFER_FRAGMENT_LSB 26 +#define RX_MSDU_END_BUFFER_FRAGMENT_MSB 26 +#define RX_MSDU_END_BUFFER_FRAGMENT_MASK 0x0000000004000000 + +#define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_MPDU_LENGTH_ERR_LSB 27 +#define RX_MSDU_END_MPDU_LENGTH_ERR_MSB 27 +#define RX_MSDU_END_MPDU_LENGTH_ERR_MASK 0x0000000008000000 + +#define RX_MSDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_TKIP_MIC_ERR_LSB 28 +#define RX_MSDU_END_TKIP_MIC_ERR_MSB 28 +#define RX_MSDU_END_TKIP_MIC_ERR_MASK 0x0000000010000000 + +#define RX_MSDU_END_DECRYPT_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_DECRYPT_ERR_LSB 29 +#define RX_MSDU_END_DECRYPT_ERR_MSB 29 +#define RX_MSDU_END_DECRYPT_ERR_MASK 0x0000000020000000 + +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB 30 +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB 30 +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0000000040000000 + +#define RX_MSDU_END_FCS_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_FCS_ERR_LSB 31 +#define RX_MSDU_END_FCS_ERR_MSB 31 +#define RX_MSDU_END_FCS_ERR_MASK 0x0000000080000000 + +#define RX_MSDU_END_RESERVED_31A_OFFSET 0x0000000000000078 +#define RX_MSDU_END_RESERVED_31A_LSB 32 +#define RX_MSDU_END_RESERVED_31A_MSB 41 +#define RX_MSDU_END_RESERVED_31A_MASK 0x000003ff00000000 + +#define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000078 +#define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB 42 +#define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB 44 +#define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK 0x00001c0000000000 + +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000078 +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB 45 +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB 45 +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x0000200000000000 + +#define RX_MSDU_END_RESERVED_31B_OFFSET 0x0000000000000078 +#define RX_MSDU_END_RESERVED_31B_LSB 46 +#define RX_MSDU_END_RESERVED_31B_MSB 62 +#define RX_MSDU_END_RESERVED_31B_MASK 0x7fffc00000000000 + +#define RX_MSDU_END_MSDU_DONE_OFFSET 0x0000000000000078 +#define RX_MSDU_END_MSDU_DONE_LSB 63 +#define RX_MSDU_END_MSDU_DONE_MSB 63 +#define RX_MSDU_END_MSDU_DONE_MASK 0x8000000000000000 + +#endif diff --git a/hw/kiwi/v2/rx_msdu_ext_desc_info.h b/hw/kiwi/v2/rx_msdu_ext_desc_info.h new file mode 100644 index 000000000000..62ae132e6cf7 --- /dev/null +++ b/hw/kiwi/v2/rx_msdu_ext_desc_info.h @@ -0,0 +1,77 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MSDU_EXT_DESC_INFO_H_ +#define _RX_MSDU_EXT_DESC_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MSDU_EXT_DESC_INFO 1 + +struct rx_msdu_ext_desc_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_destination_indication : 5, + service_code : 9, + priority_valid : 1, + data_offset : 12, + src_link_id : 3, + reserved_0a : 2; +#else + uint32_t reserved_0a : 2, + src_link_id : 3, + data_offset : 12, + priority_valid : 1, + service_code : 9, + reo_destination_indication : 5; +#endif +}; + +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_LSB 5 +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MSB 13 +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_LSB 14 +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MSB 14 +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_LSB 15 +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MSB 26 +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_LSB 27 +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MSB 29 +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_LSB 30 +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MSB 31 +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MASK 0xc0000000 + +#endif diff --git a/hw/kiwi/v2/rx_msdu_link.h b/hw/kiwi/v2/rx_msdu_link.h new file mode 100644 index 000000000000..a2a1056c2096 --- /dev/null +++ b/hw/kiwi/v2/rx_msdu_link.h @@ -0,0 +1,948 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MSDU_LINK_H_ +#define _RX_MSDU_LINK_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" +#include "buffer_addr_info.h" +#include "rx_msdu_details.h" +#define NUM_OF_DWORDS_RX_MSDU_LINK 32 + +struct rx_msdu_link { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_descriptor_header descriptor_header; + struct buffer_addr_info next_msdu_link_desc_addr_info; + uint32_t receive_queue_number : 16, + first_rx_msdu_link_struct : 1, + reserved_3a : 15; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + struct rx_msdu_details msdu_0; + struct rx_msdu_details msdu_1; + struct rx_msdu_details msdu_2; + struct rx_msdu_details msdu_3; + struct rx_msdu_details msdu_4; + struct rx_msdu_details msdu_5; +#else + struct uniform_descriptor_header descriptor_header; + struct buffer_addr_info next_msdu_link_desc_addr_info; + uint32_t reserved_3a : 15, + first_rx_msdu_link_struct : 1, + receive_queue_number : 16; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + struct rx_msdu_details msdu_0; + struct rx_msdu_details msdu_1; + struct rx_msdu_details msdu_2; + struct rx_msdu_details msdu_3; + struct rx_msdu_details msdu_4; + struct rx_msdu_details msdu_5; +#endif +}; + +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_LSB 0 +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_MSB 15 +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_OFFSET 0x0000000c +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_LSB 16 +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_MSB 16 +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_MASK 0x00010000 + +#define RX_MSDU_LINK_RESERVED_3A_OFFSET 0x0000000c +#define RX_MSDU_LINK_RESERVED_3A_LSB 17 +#define RX_MSDU_LINK_RESERVED_3A_MSB 31 +#define RX_MSDU_LINK_RESERVED_3A_MASK 0xfffe0000 + +#define RX_MSDU_LINK_PN_31_0_OFFSET 0x00000010 +#define RX_MSDU_LINK_PN_31_0_LSB 0 +#define RX_MSDU_LINK_PN_31_0_MSB 31 +#define RX_MSDU_LINK_PN_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_PN_63_32_OFFSET 0x00000014 +#define RX_MSDU_LINK_PN_63_32_LSB 0 +#define RX_MSDU_LINK_PN_63_32_MSB 31 +#define RX_MSDU_LINK_PN_63_32_MASK 0xffffffff + +#define RX_MSDU_LINK_PN_95_64_OFFSET 0x00000018 +#define RX_MSDU_LINK_PN_95_64_LSB 0 +#define RX_MSDU_LINK_PN_95_64_MSB 31 +#define RX_MSDU_LINK_PN_95_64_MASK 0xffffffff + +#define RX_MSDU_LINK_PN_127_96_OFFSET 0x0000001c +#define RX_MSDU_LINK_PN_127_96_LSB 0 +#define RX_MSDU_LINK_PN_127_96_MSB 31 +#define RX_MSDU_LINK_PN_127_96_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#endif diff --git a/hw/kiwi/v2/rx_msdu_start.h b/hw/kiwi/v2/rx_msdu_start.h new file mode 100644 index 000000000000..ecdc999ee7b5 --- /dev/null +++ b/hw/kiwi/v2/rx_msdu_start.h @@ -0,0 +1,317 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MSDU_START_H_ +#define _RX_MSDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MSDU_START 10 + +#define NUM_OF_QWORDS_RX_MSDU_START 5 + +struct rx_msdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t msdu_length : 14, + stbc : 1, + ipsec_esp : 1, + l3_offset : 7, + ipsec_ah : 1, + l4_offset : 8; + uint32_t msdu_number : 8, + decap_format : 2, + ipv4_proto : 1, + ipv6_proto : 1, + tcp_proto : 1, + udp_proto : 1, + ip_frag : 1, + tcp_only_ack : 1, + da_is_bcast_mcast : 1, + toeplitz_hash_sel : 2, + ip_fixed_header_valid : 1, + ip_extn_header_valid : 1, + tcp_udp_header_valid : 1, + mesh_control_present : 1, + ldpc : 1, + ip4_protocol_ip6_next_header : 8; + uint32_t toeplitz_hash_2_or_4 : 32; + uint32_t flow_id_toeplitz : 32; + uint32_t user_rssi : 8, + pkt_type : 4, + sgi : 2, + rate_mcs : 4, + receive_bandwidth : 3, + reception_type : 3, + mimo_ss_bitmap : 8; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t sw_phy_meta_data : 32; + uint32_t vlan_ctag_ci : 16, + vlan_stag_ci : 16; +#else + uint32_t phy_ppdu_id : 16, + reserved_0 : 7, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t l4_offset : 8, + ipsec_ah : 1, + l3_offset : 7, + ipsec_esp : 1, + stbc : 1, + msdu_length : 14; + uint32_t ip4_protocol_ip6_next_header : 8, + ldpc : 1, + mesh_control_present : 1, + tcp_udp_header_valid : 1, + ip_extn_header_valid : 1, + ip_fixed_header_valid : 1, + toeplitz_hash_sel : 2, + da_is_bcast_mcast : 1, + tcp_only_ack : 1, + ip_frag : 1, + udp_proto : 1, + tcp_proto : 1, + ipv6_proto : 1, + ipv4_proto : 1, + decap_format : 2, + msdu_number : 8; + uint32_t toeplitz_hash_2_or_4 : 32; + uint32_t flow_id_toeplitz : 32; + uint32_t mimo_ss_bitmap : 8, + reception_type : 3, + receive_bandwidth : 3, + rate_mcs : 4, + sgi : 2, + pkt_type : 4, + user_rssi : 8; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t sw_phy_meta_data : 32; + uint32_t vlan_stag_ci : 16, + vlan_ctag_ci : 16; +#endif +}; + +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 + +#define RX_MSDU_START_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 +#define RX_MSDU_START_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MSDU_START_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MSDU_START_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc + +#define RX_MSDU_START_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_MSDU_START_RESERVED_0_LSB 9 +#define RX_MSDU_START_RESERVED_0_MSB 15 +#define RX_MSDU_START_RESERVED_0_MASK 0x000000000000fe00 + +#define RX_MSDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_MSDU_START_PHY_PPDU_ID_LSB 16 +#define RX_MSDU_START_PHY_PPDU_ID_MSB 31 +#define RX_MSDU_START_PHY_PPDU_ID_MASK 0x00000000ffff0000 + +#define RX_MSDU_START_MSDU_LENGTH_OFFSET 0x0000000000000000 +#define RX_MSDU_START_MSDU_LENGTH_LSB 32 +#define RX_MSDU_START_MSDU_LENGTH_MSB 45 +#define RX_MSDU_START_MSDU_LENGTH_MASK 0x00003fff00000000 + +#define RX_MSDU_START_STBC_OFFSET 0x0000000000000000 +#define RX_MSDU_START_STBC_LSB 46 +#define RX_MSDU_START_STBC_MSB 46 +#define RX_MSDU_START_STBC_MASK 0x0000400000000000 + +#define RX_MSDU_START_IPSEC_ESP_OFFSET 0x0000000000000000 +#define RX_MSDU_START_IPSEC_ESP_LSB 47 +#define RX_MSDU_START_IPSEC_ESP_MSB 47 +#define RX_MSDU_START_IPSEC_ESP_MASK 0x0000800000000000 + +#define RX_MSDU_START_L3_OFFSET_OFFSET 0x0000000000000000 +#define RX_MSDU_START_L3_OFFSET_LSB 48 +#define RX_MSDU_START_L3_OFFSET_MSB 54 +#define RX_MSDU_START_L3_OFFSET_MASK 0x007f000000000000 + +#define RX_MSDU_START_IPSEC_AH_OFFSET 0x0000000000000000 +#define RX_MSDU_START_IPSEC_AH_LSB 55 +#define RX_MSDU_START_IPSEC_AH_MSB 55 +#define RX_MSDU_START_IPSEC_AH_MASK 0x0080000000000000 + +#define RX_MSDU_START_L4_OFFSET_OFFSET 0x0000000000000000 +#define RX_MSDU_START_L4_OFFSET_LSB 56 +#define RX_MSDU_START_L4_OFFSET_MSB 63 +#define RX_MSDU_START_L4_OFFSET_MASK 0xff00000000000000 + +#define RX_MSDU_START_MSDU_NUMBER_OFFSET 0x0000000000000008 +#define RX_MSDU_START_MSDU_NUMBER_LSB 0 +#define RX_MSDU_START_MSDU_NUMBER_MSB 7 +#define RX_MSDU_START_MSDU_NUMBER_MASK 0x00000000000000ff + +#define RX_MSDU_START_DECAP_FORMAT_OFFSET 0x0000000000000008 +#define RX_MSDU_START_DECAP_FORMAT_LSB 8 +#define RX_MSDU_START_DECAP_FORMAT_MSB 9 +#define RX_MSDU_START_DECAP_FORMAT_MASK 0x0000000000000300 + +#define RX_MSDU_START_IPV4_PROTO_OFFSET 0x0000000000000008 +#define RX_MSDU_START_IPV4_PROTO_LSB 10 +#define RX_MSDU_START_IPV4_PROTO_MSB 10 +#define RX_MSDU_START_IPV4_PROTO_MASK 0x0000000000000400 + +#define RX_MSDU_START_IPV6_PROTO_OFFSET 0x0000000000000008 +#define RX_MSDU_START_IPV6_PROTO_LSB 11 +#define RX_MSDU_START_IPV6_PROTO_MSB 11 +#define RX_MSDU_START_IPV6_PROTO_MASK 0x0000000000000800 + +#define RX_MSDU_START_TCP_PROTO_OFFSET 0x0000000000000008 +#define RX_MSDU_START_TCP_PROTO_LSB 12 +#define RX_MSDU_START_TCP_PROTO_MSB 12 +#define RX_MSDU_START_TCP_PROTO_MASK 0x0000000000001000 + +#define RX_MSDU_START_UDP_PROTO_OFFSET 0x0000000000000008 +#define RX_MSDU_START_UDP_PROTO_LSB 13 +#define RX_MSDU_START_UDP_PROTO_MSB 13 +#define RX_MSDU_START_UDP_PROTO_MASK 0x0000000000002000 + +#define RX_MSDU_START_IP_FRAG_OFFSET 0x0000000000000008 +#define RX_MSDU_START_IP_FRAG_LSB 14 +#define RX_MSDU_START_IP_FRAG_MSB 14 +#define RX_MSDU_START_IP_FRAG_MASK 0x0000000000004000 + +#define RX_MSDU_START_TCP_ONLY_ACK_OFFSET 0x0000000000000008 +#define RX_MSDU_START_TCP_ONLY_ACK_LSB 15 +#define RX_MSDU_START_TCP_ONLY_ACK_MSB 15 +#define RX_MSDU_START_TCP_ONLY_ACK_MASK 0x0000000000008000 + +#define RX_MSDU_START_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000008 +#define RX_MSDU_START_DA_IS_BCAST_MCAST_LSB 16 +#define RX_MSDU_START_DA_IS_BCAST_MCAST_MSB 16 +#define RX_MSDU_START_DA_IS_BCAST_MCAST_MASK 0x0000000000010000 + +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000008 +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_LSB 17 +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MSB 18 +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MASK 0x0000000000060000 + +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000008 +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_LSB 19 +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MSB 19 +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MASK 0x0000000000080000 + +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000008 +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_LSB 20 +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MSB 20 +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MASK 0x0000000000100000 + +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000008 +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_LSB 21 +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MSB 21 +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MASK 0x0000000000200000 + +#define RX_MSDU_START_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000008 +#define RX_MSDU_START_MESH_CONTROL_PRESENT_LSB 22 +#define RX_MSDU_START_MESH_CONTROL_PRESENT_MSB 22 +#define RX_MSDU_START_MESH_CONTROL_PRESENT_MASK 0x0000000000400000 + +#define RX_MSDU_START_LDPC_OFFSET 0x0000000000000008 +#define RX_MSDU_START_LDPC_LSB 23 +#define RX_MSDU_START_LDPC_MSB 23 +#define RX_MSDU_START_LDPC_MASK 0x0000000000800000 + +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000008 +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24 +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 31 +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0x00000000ff000000 + +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000008 +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_LSB 32 +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MSB 63 +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000 + +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000010 +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_LSB 0 +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MSB 31 +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MASK 0x00000000ffffffff + +#define RX_MSDU_START_USER_RSSI_OFFSET 0x0000000000000010 +#define RX_MSDU_START_USER_RSSI_LSB 32 +#define RX_MSDU_START_USER_RSSI_MSB 39 +#define RX_MSDU_START_USER_RSSI_MASK 0x000000ff00000000 + +#define RX_MSDU_START_PKT_TYPE_OFFSET 0x0000000000000010 +#define RX_MSDU_START_PKT_TYPE_LSB 40 +#define RX_MSDU_START_PKT_TYPE_MSB 43 +#define RX_MSDU_START_PKT_TYPE_MASK 0x00000f0000000000 + +#define RX_MSDU_START_SGI_OFFSET 0x0000000000000010 +#define RX_MSDU_START_SGI_LSB 44 +#define RX_MSDU_START_SGI_MSB 45 +#define RX_MSDU_START_SGI_MASK 0x0000300000000000 + +#define RX_MSDU_START_RATE_MCS_OFFSET 0x0000000000000010 +#define RX_MSDU_START_RATE_MCS_LSB 46 +#define RX_MSDU_START_RATE_MCS_MSB 49 +#define RX_MSDU_START_RATE_MCS_MASK 0x0003c00000000000 + +#define RX_MSDU_START_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000010 +#define RX_MSDU_START_RECEIVE_BANDWIDTH_LSB 50 +#define RX_MSDU_START_RECEIVE_BANDWIDTH_MSB 52 +#define RX_MSDU_START_RECEIVE_BANDWIDTH_MASK 0x001c000000000000 + +#define RX_MSDU_START_RECEPTION_TYPE_OFFSET 0x0000000000000010 +#define RX_MSDU_START_RECEPTION_TYPE_LSB 53 +#define RX_MSDU_START_RECEPTION_TYPE_MSB 55 +#define RX_MSDU_START_RECEPTION_TYPE_MASK 0x00e0000000000000 + +#define RX_MSDU_START_MIMO_SS_BITMAP_OFFSET 0x0000000000000010 +#define RX_MSDU_START_MIMO_SS_BITMAP_LSB 56 +#define RX_MSDU_START_MIMO_SS_BITMAP_MSB 63 +#define RX_MSDU_START_MIMO_SS_BITMAP_MASK 0xff00000000000000 + +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000018 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff + +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000018 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 + +#define RX_MSDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000020 +#define RX_MSDU_START_SW_PHY_META_DATA_LSB 0 +#define RX_MSDU_START_SW_PHY_META_DATA_MSB 31 +#define RX_MSDU_START_SW_PHY_META_DATA_MASK 0x00000000ffffffff + +#define RX_MSDU_START_VLAN_CTAG_CI_OFFSET 0x0000000000000020 +#define RX_MSDU_START_VLAN_CTAG_CI_LSB 32 +#define RX_MSDU_START_VLAN_CTAG_CI_MSB 47 +#define RX_MSDU_START_VLAN_CTAG_CI_MASK 0x0000ffff00000000 + +#define RX_MSDU_START_VLAN_STAG_CI_OFFSET 0x0000000000000020 +#define RX_MSDU_START_VLAN_STAG_CI_LSB 48 +#define RX_MSDU_START_VLAN_STAG_CI_MSB 63 +#define RX_MSDU_START_VLAN_STAG_CI_MASK 0xffff000000000000 + +#endif diff --git a/hw/kiwi/v2/rx_ppdu_end_user_stats.h b/hw/kiwi/v2/rx_ppdu_end_user_stats.h new file mode 100644 index 000000000000..f7d776796d55 --- /dev/null +++ b/hw/kiwi/v2/rx_ppdu_end_user_stats.h @@ -0,0 +1,599 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_PPDU_END_USER_STATS_H_ +#define _RX_PPDU_END_USER_STATS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_rxpcu_classification_overview.h" +#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 24 + +#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS 12 + +struct rx_ppdu_end_user_stats { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t sta_full_aid : 13, + mcs : 4, + nss : 3, + expected_response_ack_or_ba : 1, + reserved_1a : 11; + uint32_t sw_peer_id : 16, + mpdu_cnt_fcs_err : 11, + sw2rxdma0_buf_source_used : 1, + fw2rxdma_pmac0_buf_source_used : 1, + sw2rxdma1_buf_source_used : 1, + sw2rxdma_exception_buf_source_used : 1, + fw2rxdma_pmac1_buf_source_used : 1; + uint32_t mpdu_cnt_fcs_ok : 11, + frame_control_info_valid : 1, + qos_control_info_valid : 1, + ht_control_info_valid : 1, + data_sequence_control_info_valid : 1, + ht_control_info_null_valid : 1, + rxdma2fw_pmac1_ring_used : 1, + rxdma2reo_ring_used : 1, + rxdma2fw_pmac0_ring_used : 1, + rxdma2sw_ring_used : 1, + rxdma_release_ring_used : 1, + ht_control_field_pkt_type : 4, + rxdma2reo_remote0_ring_used : 1, + rxdma2reo_remote1_ring_used : 1, + reserved_3b : 5; + uint32_t ast_index : 16, + frame_control_field : 16; + uint32_t first_data_seq_ctrl : 16, + qos_control_field : 16; + uint32_t ht_control_field : 32; + uint32_t fcs_ok_bitmap_31_0 : 32; + uint32_t fcs_ok_bitmap_63_32 : 32; + uint32_t udp_msdu_count : 16, + tcp_msdu_count : 16; + uint32_t other_msdu_count : 16, + tcp_ack_msdu_count : 16; + uint32_t sw_response_reference_ptr : 32; + uint32_t received_qos_data_tid_bitmap : 16, + received_qos_data_tid_eosp_bitmap : 16; + uint32_t qosctrl_15_8_tid0 : 8, + qosctrl_15_8_tid1 : 8, + qosctrl_15_8_tid2 : 8, + qosctrl_15_8_tid3 : 8; + uint32_t qosctrl_15_8_tid4 : 8, + qosctrl_15_8_tid5 : 8, + qosctrl_15_8_tid6 : 8, + qosctrl_15_8_tid7 : 8; + uint32_t qosctrl_15_8_tid8 : 8, + qosctrl_15_8_tid9 : 8, + qosctrl_15_8_tid10 : 8, + qosctrl_15_8_tid11 : 8; + uint32_t qosctrl_15_8_tid12 : 8, + qosctrl_15_8_tid13 : 8, + qosctrl_15_8_tid14 : 8, + qosctrl_15_8_tid15 : 8; + uint32_t mpdu_ok_byte_count : 25, + ampdu_delim_ok_count_6_0 : 7; + uint32_t ampdu_delim_err_count : 25, + ampdu_delim_ok_count_13_7 : 7; + uint32_t mpdu_err_byte_count : 25, + ampdu_delim_ok_count_20_14 : 7; + uint32_t non_consecutive_delimiter_err : 16, + retried_msdu_count : 16; + uint32_t ht_control_null_field : 32; + uint32_t sw_response_reference_ptr_ext : 32; + uint32_t corrupted_due_to_fifo_delay : 1, + frame_control_info_null_valid : 1, + frame_control_field_null : 16, + retried_mpdu_count : 11, + reserved_23a : 3; +#else + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t reserved_1a : 11, + expected_response_ack_or_ba : 1, + nss : 3, + mcs : 4, + sta_full_aid : 13; + uint32_t fw2rxdma_pmac1_buf_source_used : 1, + sw2rxdma_exception_buf_source_used : 1, + sw2rxdma1_buf_source_used : 1, + fw2rxdma_pmac0_buf_source_used : 1, + sw2rxdma0_buf_source_used : 1, + mpdu_cnt_fcs_err : 11, + sw_peer_id : 16; + uint32_t reserved_3b : 5, + rxdma2reo_remote1_ring_used : 1, + rxdma2reo_remote0_ring_used : 1, + ht_control_field_pkt_type : 4, + rxdma_release_ring_used : 1, + rxdma2sw_ring_used : 1, + rxdma2fw_pmac0_ring_used : 1, + rxdma2reo_ring_used : 1, + rxdma2fw_pmac1_ring_used : 1, + ht_control_info_null_valid : 1, + data_sequence_control_info_valid : 1, + ht_control_info_valid : 1, + qos_control_info_valid : 1, + frame_control_info_valid : 1, + mpdu_cnt_fcs_ok : 11; + uint32_t frame_control_field : 16, + ast_index : 16; + uint32_t qos_control_field : 16, + first_data_seq_ctrl : 16; + uint32_t ht_control_field : 32; + uint32_t fcs_ok_bitmap_31_0 : 32; + uint32_t fcs_ok_bitmap_63_32 : 32; + uint32_t tcp_msdu_count : 16, + udp_msdu_count : 16; + uint32_t tcp_ack_msdu_count : 16, + other_msdu_count : 16; + uint32_t sw_response_reference_ptr : 32; + uint32_t received_qos_data_tid_eosp_bitmap : 16, + received_qos_data_tid_bitmap : 16; + uint32_t qosctrl_15_8_tid3 : 8, + qosctrl_15_8_tid2 : 8, + qosctrl_15_8_tid1 : 8, + qosctrl_15_8_tid0 : 8; + uint32_t qosctrl_15_8_tid7 : 8, + qosctrl_15_8_tid6 : 8, + qosctrl_15_8_tid5 : 8, + qosctrl_15_8_tid4 : 8; + uint32_t qosctrl_15_8_tid11 : 8, + qosctrl_15_8_tid10 : 8, + qosctrl_15_8_tid9 : 8, + qosctrl_15_8_tid8 : 8; + uint32_t qosctrl_15_8_tid15 : 8, + qosctrl_15_8_tid14 : 8, + qosctrl_15_8_tid13 : 8, + qosctrl_15_8_tid12 : 8; + uint32_t ampdu_delim_ok_count_6_0 : 7, + mpdu_ok_byte_count : 25; + uint32_t ampdu_delim_ok_count_13_7 : 7, + ampdu_delim_err_count : 25; + uint32_t ampdu_delim_ok_count_20_14 : 7, + mpdu_err_byte_count : 25; + uint32_t retried_msdu_count : 16, + non_consecutive_delimiter_err : 16; + uint32_t ht_control_null_field : 32; + uint32_t sw_response_reference_ptr_ext : 32; + uint32_t reserved_23a : 3, + retried_mpdu_count : 11, + frame_control_field_null : 16, + frame_control_info_null_valid : 1, + corrupted_due_to_fifo_delay : 1; +#endif +}; + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000fe00 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 + +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_LSB 32 +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MSB 44 +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MASK 0x00001fff00000000 + +#define RX_PPDU_END_USER_STATS_MCS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_MCS_LSB 45 +#define RX_PPDU_END_USER_STATS_MCS_MSB 48 +#define RX_PPDU_END_USER_STATS_MCS_MASK 0x0001e00000000000 + +#define RX_PPDU_END_USER_STATS_NSS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_NSS_LSB 49 +#define RX_PPDU_END_USER_STATS_NSS_MSB 51 +#define RX_PPDU_END_USER_STATS_NSS_MASK 0x000e000000000000 + +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_LSB 52 +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MSB 52 +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MASK 0x0010000000000000 + +#define RX_PPDU_END_USER_STATS_RESERVED_1A_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RESERVED_1A_LSB 53 +#define RX_PPDU_END_USER_STATS_RESERVED_1A_MSB 63 +#define RX_PPDU_END_USER_STATS_RESERVED_1A_MASK 0xffe0000000000000 + +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_LSB 0 +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MSB 15 +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MASK 0x000000000000ffff + +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_LSB 16 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MSB 26 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MASK 0x0000000007ff0000 + +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_LSB 27 +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MSB 27 +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MASK 0x0000000008000000 + +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_LSB 28 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MSB 28 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MASK 0x0000000010000000 + +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_LSB 29 +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MSB 29 +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MASK 0x0000000020000000 + +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_LSB 30 +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MSB 30 +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MASK 0x0000000040000000 + +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_LSB 31 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MSB 31 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MASK 0x0000000080000000 + +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_LSB 32 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MSB 42 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MASK 0x000007ff00000000 + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_LSB 43 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MSB 43 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MASK 0x0000080000000000 + +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_LSB 44 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MSB 44 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MASK 0x0000100000000000 + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_LSB 45 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MSB 45 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MASK 0x0000200000000000 + +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 46 +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MSB 46 +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x0000400000000000 + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_LSB 47 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MSB 47 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MASK 0x0000800000000000 + +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_LSB 48 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MSB 48 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MASK 0x0001000000000000 + +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_LSB 49 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MSB 49 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MASK 0x0002000000000000 + +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_LSB 50 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MSB 50 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MASK 0x0004000000000000 + +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_LSB 51 +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MSB 51 +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MASK 0x0008000000000000 + +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_LSB 52 +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MSB 52 +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MASK 0x0010000000000000 + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_LSB 53 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MSB 56 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x01e0000000000000 + +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_LSB 57 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MSB 57 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MASK 0x0200000000000000 + +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_LSB 58 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MSB 58 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MASK 0x0400000000000000 + +#define RX_PPDU_END_USER_STATS_RESERVED_3B_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RESERVED_3B_LSB 59 +#define RX_PPDU_END_USER_STATS_RESERVED_3B_MSB 63 +#define RX_PPDU_END_USER_STATS_RESERVED_3B_MASK 0xf800000000000000 + +#define RX_PPDU_END_USER_STATS_AST_INDEX_OFFSET 0x0000000000000010 +#define RX_PPDU_END_USER_STATS_AST_INDEX_LSB 0 +#define RX_PPDU_END_USER_STATS_AST_INDEX_MSB 15 +#define RX_PPDU_END_USER_STATS_AST_INDEX_MASK 0x000000000000ffff + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000010 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_LSB 16 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MSB 31 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MASK 0x00000000ffff0000 + +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_OFFSET 0x0000000000000010 +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_LSB 32 +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MSB 47 +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff00000000 + +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_OFFSET 0x0000000000000010 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_LSB 48 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MSB 63 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MASK 0xffff000000000000 + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_OFFSET 0x0000000000000018 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_LSB 0 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MSB 31 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MASK 0x00000000ffffffff + +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_OFFSET 0x0000000000000018 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_LSB 32 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MSB 63 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MASK 0xffffffff00000000 + +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_OFFSET 0x0000000000000020 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_LSB 0 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MSB 31 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MASK 0x00000000ffffffff + +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_OFFSET 0x0000000000000020 +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_LSB 32 +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MSB 47 +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MASK 0x0000ffff00000000 + +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_OFFSET 0x0000000000000020 +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_LSB 48 +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MSB 63 +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MASK 0xffff000000000000 + +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_OFFSET 0x0000000000000028 +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MSB 15 +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MASK 0x000000000000ffff + +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_OFFSET 0x0000000000000028 +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MASK 0x00000000ffff0000 + +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000000000000028 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_LSB 32 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MSB 63 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff00000000 + +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x0000000000000030 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MSB 15 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x000000000000ffff + +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x0000000000000030 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MSB 31 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0x00000000ffff0000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_OFFSET 0x0000000000000030 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_LSB 32 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MSB 39 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MASK 0x000000ff00000000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_OFFSET 0x0000000000000030 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_LSB 40 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MSB 47 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MASK 0x0000ff0000000000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_OFFSET 0x0000000000000030 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_LSB 48 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MSB 55 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MASK 0x00ff000000000000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_OFFSET 0x0000000000000030 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_LSB 56 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MSB 63 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MASK 0xff00000000000000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_LSB 0 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MSB 7 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MASK 0x00000000000000ff + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_LSB 8 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MSB 15 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MASK 0x000000000000ff00 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_LSB 16 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MSB 23 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MASK 0x0000000000ff0000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_LSB 24 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MSB 31 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MASK 0x00000000ff000000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_LSB 32 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MSB 39 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MASK 0x000000ff00000000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_LSB 40 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MSB 47 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MASK 0x0000ff0000000000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_LSB 48 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MSB 55 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MASK 0x00ff000000000000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_LSB 56 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MSB 63 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MASK 0xff00000000000000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_OFFSET 0x0000000000000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_LSB 0 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MSB 7 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MASK 0x00000000000000ff + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_OFFSET 0x0000000000000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_LSB 8 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MSB 15 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MASK 0x000000000000ff00 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_OFFSET 0x0000000000000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_LSB 16 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MSB 23 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MASK 0x0000000000ff0000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_OFFSET 0x0000000000000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_LSB 24 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MSB 31 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MASK 0x00000000ff000000 + +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_OFFSET 0x0000000000000040 +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_LSB 32 +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MSB 56 +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff00000000 + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x0000000000000040 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_LSB 57 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MSB 63 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe00000000000000 + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_OFFSET 0x0000000000000048 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MSB 24 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MASK 0x0000000001ffffff + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x0000000000000048 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_LSB 25 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MSB 31 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MASK 0x00000000fe000000 + +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000000000000048 +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_LSB 32 +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MSB 56 +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff00000000 + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000000000000048 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_LSB 57 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MSB 63 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe00000000000000 + +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x0000000000000050 +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0 +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MSB 15 +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x000000000000ffff + +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_OFFSET 0x0000000000000050 +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MASK 0x00000000ffff0000 + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_OFFSET 0x0000000000000050 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_LSB 32 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MSB 63 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MASK 0xffffffff00000000 + +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x0000000000000058 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MSB 31 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0x00000000ffffffff + +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000058 +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000058 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_LSB 33 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MSB 33 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MASK 0x0000000200000000 + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_OFFSET 0x0000000000000058 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_LSB 34 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MSB 49 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MASK 0x0003fffc00000000 + +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_OFFSET 0x0000000000000058 +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_LSB 50 +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MSB 60 +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MASK 0x1ffc000000000000 + +#define RX_PPDU_END_USER_STATS_RESERVED_23A_OFFSET 0x0000000000000058 +#define RX_PPDU_END_USER_STATS_RESERVED_23A_LSB 61 +#define RX_PPDU_END_USER_STATS_RESERVED_23A_MSB 63 +#define RX_PPDU_END_USER_STATS_RESERVED_23A_MASK 0xe000000000000000 + +#endif diff --git a/hw/kiwi/v2/rx_ppdu_end_user_stats_ext.h b/hw/kiwi/v2/rx_ppdu_end_user_stats_ext.h new file mode 100644 index 000000000000..8642f7069004 --- /dev/null +++ b/hw/kiwi/v2/rx_ppdu_end_user_stats_ext.h @@ -0,0 +1,151 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_PPDU_END_USER_STATS_EXT_H_ +#define _RX_PPDU_END_USER_STATS_EXT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_rxpcu_classification_overview.h" +#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 8 + +#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS_EXT 4 + +struct rx_ppdu_end_user_stats_ext { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t fcs_ok_bitmap_95_64 : 32; + uint32_t fcs_ok_bitmap_127_96 : 32; + uint32_t fcs_ok_bitmap_159_128 : 32; + uint32_t fcs_ok_bitmap_191_160 : 32; + uint32_t fcs_ok_bitmap_223_192 : 32; + uint32_t fcs_ok_bitmap_255_224 : 32; + uint32_t corrupted_due_to_fifo_delay : 1, + reserved_7a : 31; +#else + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t fcs_ok_bitmap_95_64 : 32; + uint32_t fcs_ok_bitmap_127_96 : 32; + uint32_t fcs_ok_bitmap_159_128 : 32; + uint32_t fcs_ok_bitmap_191_160 : 32; + uint32_t fcs_ok_bitmap_223_192 : 32; + uint32_t fcs_ok_bitmap_255_224 : 32; + uint32_t reserved_7a : 31, + corrupted_due_to_fifo_delay : 1; +#endif +}; + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000fe00 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_LSB 32 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MSB 63 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MASK 0xffffffff00000000 + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MASK 0x00000000ffffffff + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_LSB 32 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MSB 63 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MASK 0xffffffff00000000 + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_OFFSET 0x0000000000000010 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MASK 0x00000000ffffffff + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_OFFSET 0x0000000000000010 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_LSB 32 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MSB 63 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MASK 0xffffffff00000000 + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_OFFSET 0x0000000000000018 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MASK 0x00000000ffffffff + +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000018 +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 + +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_OFFSET 0x0000000000000018 +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_LSB 33 +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MSB 63 +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MASK 0xfffffffe00000000 + +#endif diff --git a/hw/kiwi/v2/rx_ppdu_start.h b/hw/kiwi/v2/rx_ppdu_start.h new file mode 100644 index 000000000000..eed0e8b832de --- /dev/null +++ b/hw/kiwi/v2/rx_ppdu_start.h @@ -0,0 +1,93 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_PPDU_START_H_ +#define _RX_PPDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_PPDU_START 6 + +#define NUM_OF_QWORDS_RX_PPDU_START 3 + +struct rx_ppdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_ppdu_id : 16, + preamble_time_to_rxframe : 8, + reserved_0a : 8; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t rxframe_assert_timestamp : 32; + uint32_t tlv64_padding : 32; +#else + uint32_t reserved_0a : 8, + preamble_time_to_rxframe : 8, + phy_ppdu_id : 16; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t rxframe_assert_timestamp : 32; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RX_PPDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_PPDU_START_PHY_PPDU_ID_LSB 0 +#define RX_PPDU_START_PHY_PPDU_ID_MSB 15 +#define RX_PPDU_START_PHY_PPDU_ID_MASK 0x000000000000ffff + +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000000 +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB 16 +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB 23 +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK 0x0000000000ff0000 + +#define RX_PPDU_START_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_PPDU_START_RESERVED_0A_LSB 24 +#define RX_PPDU_START_RESERVED_0A_MSB 31 +#define RX_PPDU_START_RESERVED_0A_MASK 0x00000000ff000000 + +#define RX_PPDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000000 +#define RX_PPDU_START_SW_PHY_META_DATA_LSB 32 +#define RX_PPDU_START_SW_PHY_META_DATA_MSB 63 +#define RX_PPDU_START_SW_PHY_META_DATA_MASK 0xffffffff00000000 + +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000008 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff + +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 + +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET 0x0000000000000010 +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB 0 +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB 31 +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK 0x00000000ffffffff + +#define RX_PPDU_START_TLV64_PADDING_OFFSET 0x0000000000000010 +#define RX_PPDU_START_TLV64_PADDING_LSB 32 +#define RX_PPDU_START_TLV64_PADDING_MSB 63 +#define RX_PPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/rx_ppdu_start_user_info.h b/hw/kiwi/v2/rx_ppdu_start_user_info.h new file mode 100644 index 000000000000..04ab55ff2d91 --- /dev/null +++ b/hw/kiwi/v2/rx_ppdu_start_user_info.h @@ -0,0 +1,210 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_PPDU_START_USER_INFO_H_ +#define _RX_PPDU_START_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "receive_user_info.h" +#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 8 + +#define NUM_OF_QWORDS_RX_PPDU_START_USER_INFO 4 + +struct rx_ppdu_start_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct receive_user_info receive_user_info_details; +#else + struct receive_user_info receive_user_info_details; +#endif +}; + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x000000000000ffff + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x0000000000ff0000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x0000000010000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0x00000000e0000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 32 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 35 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f00000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 36 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 37 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x0000003000000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_LSB 39 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MSB 39 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 40 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 47 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff0000000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 48 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 50 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x0007000000000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 51 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 55 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f8000000000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 56 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 63 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff00000000000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x0000000000000001 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 7 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x00000000000000fe + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x0000000000000700 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x0000000000003800 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x0000000000004000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x0000000000008000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x00000000000f0000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x0000000000f00000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x000000000f000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0x00000000f0000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 32 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 37 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f00000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 38 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 39 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c000000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 40 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 45 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f0000000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 46 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 47 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c00000000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 48 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 53 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f000000000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 54 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 55 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c0000000000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 56 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 61 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f00000000000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 62 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 63 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0xc000000000000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET 0x0000000000000010 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK 0x00000000ffffffff + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET 0x0000000000000010 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB 32 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB 63 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK 0xffffffff00000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET 0x0000000000000018 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK 0x00000000ffffffff + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET 0x0000000000000018 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB 32 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB 63 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/rx_reo_queue.h b/hw/kiwi/v2/rx_reo_queue.h new file mode 100644 index 000000000000..05a04f5daa81 --- /dev/null +++ b/hw/kiwi/v2/rx_reo_queue.h @@ -0,0 +1,515 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_REO_QUEUE_H_ +#define _RX_REO_QUEUE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" +#define NUM_OF_DWORDS_RX_REO_QUEUE 32 + +struct rx_reo_queue { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_descriptor_header descriptor_header; + uint32_t receive_queue_number : 16, + reserved_1b : 16; + uint32_t vld : 1, + associated_link_descriptor_counter : 2, + disable_duplicate_detection : 1, + soft_reorder_enable : 1, + ac : 2, + bar : 1, + rty : 1, + chk_2k_mode : 1, + oor_mode : 1, + ba_window_size : 10, + pn_check_needed : 1, + pn_shall_be_even : 1, + pn_shall_be_uneven : 1, + pn_handling_enable : 1, + pn_size : 2, + ignore_ampdu_flag : 1, + reserved_2b : 4; + uint32_t svld : 1, + ssn : 12, + current_index : 10, + seq_2k_error_detected_flag : 1, + pn_error_detected_flag : 1, + reserved_3a : 6, + pn_valid : 1; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t last_rx_enqueue_timestamp : 32; + uint32_t last_rx_dequeue_timestamp : 32; + uint32_t ptr_to_next_aging_queue_31_0 : 32; + uint32_t ptr_to_next_aging_queue_39_32 : 8, + reserved_11a : 24; + uint32_t ptr_to_previous_aging_queue_31_0 : 32; + uint32_t ptr_to_previous_aging_queue_39_32 : 8, + statistics_counter_index : 6, + reserved_13a : 18; + uint32_t rx_bitmap_31_0 : 32; + uint32_t rx_bitmap_63_32 : 32; + uint32_t rx_bitmap_95_64 : 32; + uint32_t rx_bitmap_127_96 : 32; + uint32_t rx_bitmap_159_128 : 32; + uint32_t rx_bitmap_191_160 : 32; + uint32_t rx_bitmap_223_192 : 32; + uint32_t rx_bitmap_255_224 : 32; + uint32_t rx_bitmap_287_256 : 32; + uint32_t current_mpdu_count : 7, + current_msdu_count : 25; + uint32_t last_sn_reg_index : 4, + timeout_count : 6, + forward_due_to_bar_count : 6, + duplicate_count : 16; + uint32_t frames_in_order_count : 24, + bar_received_count : 8; + uint32_t mpdu_frames_processed_count : 32; + uint32_t msdu_frames_processed_count : 32; + uint32_t total_processed_byte_count : 32; + uint32_t late_receive_mpdu_count : 12, + window_jump_2k : 4, + hole_count : 16; + uint32_t aging_drop_mpdu_count : 16, + aging_drop_interval : 8, + reserved_30 : 8; + uint32_t reserved_31 : 32; +#else + struct uniform_descriptor_header descriptor_header; + uint32_t reserved_1b : 16, + receive_queue_number : 16; + uint32_t reserved_2b : 4, + ignore_ampdu_flag : 1, + pn_size : 2, + pn_handling_enable : 1, + pn_shall_be_uneven : 1, + pn_shall_be_even : 1, + pn_check_needed : 1, + ba_window_size : 10, + oor_mode : 1, + chk_2k_mode : 1, + rty : 1, + bar : 1, + ac : 2, + soft_reorder_enable : 1, + disable_duplicate_detection : 1, + associated_link_descriptor_counter : 2, + vld : 1; + uint32_t pn_valid : 1, + reserved_3a : 6, + pn_error_detected_flag : 1, + seq_2k_error_detected_flag : 1, + current_index : 10, + ssn : 12, + svld : 1; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t last_rx_enqueue_timestamp : 32; + uint32_t last_rx_dequeue_timestamp : 32; + uint32_t ptr_to_next_aging_queue_31_0 : 32; + uint32_t reserved_11a : 24, + ptr_to_next_aging_queue_39_32 : 8; + uint32_t ptr_to_previous_aging_queue_31_0 : 32; + uint32_t reserved_13a : 18, + statistics_counter_index : 6, + ptr_to_previous_aging_queue_39_32 : 8; + uint32_t rx_bitmap_31_0 : 32; + uint32_t rx_bitmap_63_32 : 32; + uint32_t rx_bitmap_95_64 : 32; + uint32_t rx_bitmap_127_96 : 32; + uint32_t rx_bitmap_159_128 : 32; + uint32_t rx_bitmap_191_160 : 32; + uint32_t rx_bitmap_223_192 : 32; + uint32_t rx_bitmap_255_224 : 32; + uint32_t rx_bitmap_287_256 : 32; + uint32_t current_msdu_count : 25, + current_mpdu_count : 7; + uint32_t duplicate_count : 16, + forward_due_to_bar_count : 6, + timeout_count : 6, + last_sn_reg_index : 4; + uint32_t bar_received_count : 8, + frames_in_order_count : 24; + uint32_t mpdu_frames_processed_count : 32; + uint32_t msdu_frames_processed_count : 32; + uint32_t total_processed_byte_count : 32; + uint32_t hole_count : 16, + window_jump_2k : 4, + late_receive_mpdu_count : 12; + uint32_t reserved_30 : 8, + aging_drop_interval : 8, + aging_drop_mpdu_count : 16; + uint32_t reserved_31 : 32; +#endif +}; + +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 + +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 0 +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 15 +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + +#define RX_REO_QUEUE_RESERVED_1B_OFFSET 0x00000004 +#define RX_REO_QUEUE_RESERVED_1B_LSB 16 +#define RX_REO_QUEUE_RESERVED_1B_MSB 31 +#define RX_REO_QUEUE_RESERVED_1B_MASK 0xffff0000 + +#define RX_REO_QUEUE_VLD_OFFSET 0x00000008 +#define RX_REO_QUEUE_VLD_LSB 0 +#define RX_REO_QUEUE_VLD_MSB 0 +#define RX_REO_QUEUE_VLD_MASK 0x00000001 + +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1 +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 2 +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006 + +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 3 +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 3 +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008 + +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x00000008 +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 4 +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 4 +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x00000010 + +#define RX_REO_QUEUE_AC_OFFSET 0x00000008 +#define RX_REO_QUEUE_AC_LSB 5 +#define RX_REO_QUEUE_AC_MSB 6 +#define RX_REO_QUEUE_AC_MASK 0x00000060 + +#define RX_REO_QUEUE_BAR_OFFSET 0x00000008 +#define RX_REO_QUEUE_BAR_LSB 7 +#define RX_REO_QUEUE_BAR_MSB 7 +#define RX_REO_QUEUE_BAR_MASK 0x00000080 + +#define RX_REO_QUEUE_RTY_OFFSET 0x00000008 +#define RX_REO_QUEUE_RTY_LSB 8 +#define RX_REO_QUEUE_RTY_MSB 8 +#define RX_REO_QUEUE_RTY_MASK 0x00000100 + +#define RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x00000008 +#define RX_REO_QUEUE_CHK_2K_MODE_LSB 9 +#define RX_REO_QUEUE_CHK_2K_MODE_MSB 9 +#define RX_REO_QUEUE_CHK_2K_MODE_MASK 0x00000200 + +#define RX_REO_QUEUE_OOR_MODE_OFFSET 0x00000008 +#define RX_REO_QUEUE_OOR_MODE_LSB 10 +#define RX_REO_QUEUE_OOR_MODE_MSB 10 +#define RX_REO_QUEUE_OOR_MODE_MASK 0x00000400 + +#define RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x00000008 +#define RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 11 +#define RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 20 +#define RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x001ff800 + +#define RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 21 +#define RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 21 +#define RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x00200000 + +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 22 +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 22 +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x00400000 + +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 23 +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 23 +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x00800000 + +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 24 +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 24 +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x01000000 + +#define RX_REO_QUEUE_PN_SIZE_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_SIZE_LSB 25 +#define RX_REO_QUEUE_PN_SIZE_MSB 26 +#define RX_REO_QUEUE_PN_SIZE_MASK 0x06000000 + +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 27 +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 27 +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x08000000 + +#define RX_REO_QUEUE_RESERVED_2B_OFFSET 0x00000008 +#define RX_REO_QUEUE_RESERVED_2B_LSB 28 +#define RX_REO_QUEUE_RESERVED_2B_MSB 31 +#define RX_REO_QUEUE_RESERVED_2B_MASK 0xf0000000 + +#define RX_REO_QUEUE_SVLD_OFFSET 0x0000000c +#define RX_REO_QUEUE_SVLD_LSB 0 +#define RX_REO_QUEUE_SVLD_MSB 0 +#define RX_REO_QUEUE_SVLD_MASK 0x00000001 + +#define RX_REO_QUEUE_SSN_OFFSET 0x0000000c +#define RX_REO_QUEUE_SSN_LSB 1 +#define RX_REO_QUEUE_SSN_MSB 12 +#define RX_REO_QUEUE_SSN_MASK 0x00001ffe + +#define RX_REO_QUEUE_CURRENT_INDEX_OFFSET 0x0000000c +#define RX_REO_QUEUE_CURRENT_INDEX_LSB 13 +#define RX_REO_QUEUE_CURRENT_INDEX_MSB 22 +#define RX_REO_QUEUE_CURRENT_INDEX_MASK 0x007fe000 + +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 23 +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 23 +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00800000 + +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 24 +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 24 +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x01000000 + +#define RX_REO_QUEUE_RESERVED_3A_OFFSET 0x0000000c +#define RX_REO_QUEUE_RESERVED_3A_LSB 25 +#define RX_REO_QUEUE_RESERVED_3A_MSB 30 +#define RX_REO_QUEUE_RESERVED_3A_MASK 0x7e000000 + +#define RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000c +#define RX_REO_QUEUE_PN_VALID_LSB 31 +#define RX_REO_QUEUE_PN_VALID_MSB 31 +#define RX_REO_QUEUE_PN_VALID_MASK 0x80000000 + +#define RX_REO_QUEUE_PN_31_0_OFFSET 0x00000010 +#define RX_REO_QUEUE_PN_31_0_LSB 0 +#define RX_REO_QUEUE_PN_31_0_MSB 31 +#define RX_REO_QUEUE_PN_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_PN_63_32_OFFSET 0x00000014 +#define RX_REO_QUEUE_PN_63_32_LSB 0 +#define RX_REO_QUEUE_PN_63_32_MSB 31 +#define RX_REO_QUEUE_PN_63_32_MASK 0xffffffff + +#define RX_REO_QUEUE_PN_95_64_OFFSET 0x00000018 +#define RX_REO_QUEUE_PN_95_64_LSB 0 +#define RX_REO_QUEUE_PN_95_64_MSB 31 +#define RX_REO_QUEUE_PN_95_64_MASK 0xffffffff + +#define RX_REO_QUEUE_PN_127_96_OFFSET 0x0000001c +#define RX_REO_QUEUE_PN_127_96_LSB 0 +#define RX_REO_QUEUE_PN_127_96_MSB 31 +#define RX_REO_QUEUE_PN_127_96_MASK 0xffffffff + +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MSB 31 +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff + +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31 +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff + +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MSB 31 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MSB 7 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_RESERVED_11A_OFFSET 0x0000002c +#define RX_REO_QUEUE_RESERVED_11A_LSB 8 +#define RX_REO_QUEUE_RESERVED_11A_MSB 31 +#define RX_REO_QUEUE_RESERVED_11A_MASK 0xffffff00 + +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MSB 31 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MSB 7 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_OFFSET 0x00000034 +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_LSB 8 +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MSB 13 +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MASK 0x00003f00 + +#define RX_REO_QUEUE_RESERVED_13A_OFFSET 0x00000034 +#define RX_REO_QUEUE_RESERVED_13A_LSB 14 +#define RX_REO_QUEUE_RESERVED_13A_MSB 31 +#define RX_REO_QUEUE_RESERVED_13A_MASK 0xffffc000 + +#define RX_REO_QUEUE_RX_BITMAP_31_0_OFFSET 0x00000038 +#define RX_REO_QUEUE_RX_BITMAP_31_0_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_31_0_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_63_32_OFFSET 0x0000003c +#define RX_REO_QUEUE_RX_BITMAP_63_32_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_63_32_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_63_32_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_95_64_OFFSET 0x00000040 +#define RX_REO_QUEUE_RX_BITMAP_95_64_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_95_64_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_95_64_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_127_96_OFFSET 0x00000044 +#define RX_REO_QUEUE_RX_BITMAP_127_96_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_127_96_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_127_96_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_159_128_OFFSET 0x00000048 +#define RX_REO_QUEUE_RX_BITMAP_159_128_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_159_128_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_159_128_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_191_160_OFFSET 0x0000004c +#define RX_REO_QUEUE_RX_BITMAP_191_160_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_191_160_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_191_160_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_223_192_OFFSET 0x00000050 +#define RX_REO_QUEUE_RX_BITMAP_223_192_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_223_192_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_223_192_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_255_224_OFFSET 0x00000054 +#define RX_REO_QUEUE_RX_BITMAP_255_224_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_255_224_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_255_224_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_287_256_OFFSET 0x00000058 +#define RX_REO_QUEUE_RX_BITMAP_287_256_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_287_256_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_287_256_MASK 0xffffffff + +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MSB 6 +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MASK 0x0000007f + +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_LSB 7 +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MSB 31 +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MASK 0xffffff80 + +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_OFFSET 0x00000060 +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_LSB 0 +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_MSB 3 +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_MASK 0x0000000f + +#define RX_REO_QUEUE_TIMEOUT_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_TIMEOUT_COUNT_LSB 4 +#define RX_REO_QUEUE_TIMEOUT_COUNT_MSB 9 +#define RX_REO_QUEUE_TIMEOUT_COUNT_MASK 0x000003f0 + +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_LSB 10 +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MSB 15 +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 + +#define RX_REO_QUEUE_DUPLICATE_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_DUPLICATE_COUNT_LSB 16 +#define RX_REO_QUEUE_DUPLICATE_COUNT_MSB 31 +#define RX_REO_QUEUE_DUPLICATE_COUNT_MASK 0xffff0000 + +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000064 +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_LSB 0 +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MSB 23 +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff + +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_OFFSET 0x00000064 +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_LSB 24 +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MSB 31 +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MASK 0xff000000 + +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068 +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MSB 31 +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000006c +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MSB 31 +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000070 +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MSB 31 +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff + +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000074 +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MSB 11 +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff + +#define RX_REO_QUEUE_WINDOW_JUMP_2K_OFFSET 0x00000074 +#define RX_REO_QUEUE_WINDOW_JUMP_2K_LSB 12 +#define RX_REO_QUEUE_WINDOW_JUMP_2K_MSB 15 +#define RX_REO_QUEUE_WINDOW_JUMP_2K_MASK 0x0000f000 + +#define RX_REO_QUEUE_HOLE_COUNT_OFFSET 0x00000074 +#define RX_REO_QUEUE_HOLE_COUNT_LSB 16 +#define RX_REO_QUEUE_HOLE_COUNT_MSB 31 +#define RX_REO_QUEUE_HOLE_COUNT_MASK 0xffff0000 + +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_OFFSET 0x00000078 +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MSB 15 +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MASK 0x0000ffff + +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_OFFSET 0x00000078 +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_LSB 16 +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_MSB 23 +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_MASK 0x00ff0000 + +#define RX_REO_QUEUE_RESERVED_30_OFFSET 0x00000078 +#define RX_REO_QUEUE_RESERVED_30_LSB 24 +#define RX_REO_QUEUE_RESERVED_30_MSB 31 +#define RX_REO_QUEUE_RESERVED_30_MASK 0xff000000 + +#define RX_REO_QUEUE_RESERVED_31_OFFSET 0x0000007c +#define RX_REO_QUEUE_RESERVED_31_LSB 0 +#define RX_REO_QUEUE_RESERVED_31_MSB 31 +#define RX_REO_QUEUE_RESERVED_31_MASK 0xffffffff + +#endif diff --git a/hw/kiwi/v2/rx_reo_queue_ext.h b/hw/kiwi/v2/rx_reo_queue_ext.h new file mode 100644 index 000000000000..de867cab8327 --- /dev/null +++ b/hw/kiwi/v2/rx_reo_queue_ext.h @@ -0,0 +1,391 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_REO_QUEUE_EXT_H_ +#define _RX_REO_QUEUE_EXT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_link_ptr.h" +#include "uniform_descriptor_header.h" +#define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32 + +struct rx_reo_queue_ext { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_descriptor_header descriptor_header; + uint32_t reserved_1a : 32; + struct rx_mpdu_link_ptr mpdu_link_pointer_0; + struct rx_mpdu_link_ptr mpdu_link_pointer_1; + struct rx_mpdu_link_ptr mpdu_link_pointer_2; + struct rx_mpdu_link_ptr mpdu_link_pointer_3; + struct rx_mpdu_link_ptr mpdu_link_pointer_4; + struct rx_mpdu_link_ptr mpdu_link_pointer_5; + struct rx_mpdu_link_ptr mpdu_link_pointer_6; + struct rx_mpdu_link_ptr mpdu_link_pointer_7; + struct rx_mpdu_link_ptr mpdu_link_pointer_8; + struct rx_mpdu_link_ptr mpdu_link_pointer_9; + struct rx_mpdu_link_ptr mpdu_link_pointer_10; + struct rx_mpdu_link_ptr mpdu_link_pointer_11; + struct rx_mpdu_link_ptr mpdu_link_pointer_12; + struct rx_mpdu_link_ptr mpdu_link_pointer_13; + struct rx_mpdu_link_ptr mpdu_link_pointer_14; +#else + struct uniform_descriptor_header descriptor_header; + uint32_t reserved_1a : 32; + struct rx_mpdu_link_ptr mpdu_link_pointer_0; + struct rx_mpdu_link_ptr mpdu_link_pointer_1; + struct rx_mpdu_link_ptr mpdu_link_pointer_2; + struct rx_mpdu_link_ptr mpdu_link_pointer_3; + struct rx_mpdu_link_ptr mpdu_link_pointer_4; + struct rx_mpdu_link_ptr mpdu_link_pointer_5; + struct rx_mpdu_link_ptr mpdu_link_pointer_6; + struct rx_mpdu_link_ptr mpdu_link_pointer_7; + struct rx_mpdu_link_ptr mpdu_link_pointer_8; + struct rx_mpdu_link_ptr mpdu_link_pointer_9; + struct rx_mpdu_link_ptr mpdu_link_pointer_10; + struct rx_mpdu_link_ptr mpdu_link_pointer_11; + struct rx_mpdu_link_ptr mpdu_link_pointer_12; + struct rx_mpdu_link_ptr mpdu_link_pointer_13; + struct rx_mpdu_link_ptr mpdu_link_pointer_14; +#endif +}; + +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 + +#define RX_REO_QUEUE_EXT_RESERVED_1A_OFFSET 0x00000004 +#define RX_REO_QUEUE_EXT_RESERVED_1A_LSB 0 +#define RX_REO_QUEUE_EXT_RESERVED_1A_MSB 31 +#define RX_REO_QUEUE_EXT_RESERVED_1A_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#endif diff --git a/hw/kiwi/v2/rx_rxpcu_classification_overview.h b/hw/kiwi/v2/rx_rxpcu_classification_overview.h new file mode 100644 index 000000000000..49567c756ef8 --- /dev/null +++ b/hw/kiwi/v2/rx_rxpcu_classification_overview.h @@ -0,0 +1,112 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ +#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1 + +struct rx_rxpcu_classification_overview { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t filter_pass_mpdus : 1, + filter_pass_mpdus_fcs_ok : 1, + monitor_direct_mpdus : 1, + monitor_direct_mpdus_fcs_ok : 1, + monitor_other_mpdus : 1, + monitor_other_mpdus_fcs_ok : 1, + phyrx_abort_received : 1, + filter_pass_monitor_ovrd_mpdus : 1, + filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, + reserved_0 : 7, + phy_ppdu_id : 16; +#else + uint32_t phy_ppdu_id : 16, + reserved_0 : 7, + filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, + filter_pass_monitor_ovrd_mpdus : 1, + phyrx_abort_received : 1, + monitor_other_mpdus_fcs_ok : 1, + monitor_other_mpdus : 1, + monitor_direct_mpdus_fcs_ok : 1, + monitor_direct_mpdus : 1, + filter_pass_mpdus_fcs_ok : 1, + filter_pass_mpdus : 1; +#endif +}; + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_LSB 0 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MSB 0 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MASK 0x00000001 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MSB 1 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MSB 2 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MASK 0x00000004 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MSB 4 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MASK 0x00000010 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MSB 6 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MASK 0x00000040 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x00000080 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_LSB 9 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MSB 15 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MASK 0x0000fe00 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_LSB 16 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MSB 31 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MASK 0xffff0000 + +#endif diff --git a/hw/kiwi/v2/rx_timing_offset_info.h b/hw/kiwi/v2/rx_timing_offset_info.h new file mode 100644 index 000000000000..849eb8420fa8 --- /dev/null +++ b/hw/kiwi/v2/rx_timing_offset_info.h @@ -0,0 +1,49 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_TIMING_OFFSET_INFO_H_ +#define _RX_TIMING_OFFSET_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_TIMING_OFFSET_INFO 1 + +struct rx_timing_offset_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t residual_phase_offset : 12, + reserved : 20; +#else + uint32_t reserved : 20, + residual_phase_offset : 12; +#endif +}; + +#define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000000 +#define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_LSB 0 +#define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_MSB 11 +#define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + +#define RX_TIMING_OFFSET_INFO_RESERVED_OFFSET 0x00000000 +#define RX_TIMING_OFFSET_INFO_RESERVED_LSB 12 +#define RX_TIMING_OFFSET_INFO_RESERVED_MSB 31 +#define RX_TIMING_OFFSET_INFO_RESERVED_MASK 0xfffff000 + +#endif diff --git a/hw/kiwi/v2/rxpcu_ppdu_end_info.h b/hw/kiwi/v2/rxpcu_ppdu_end_info.h new file mode 100644 index 000000000000..ff017bc2f0f0 --- /dev/null +++ b/hw/kiwi/v2/rxpcu_ppdu_end_info.h @@ -0,0 +1,788 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RXPCU_PPDU_END_INFO_H_ +#define _RXPCU_PPDU_END_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phyrx_abort_request_info.h" +#include "macrx_abort_request_info.h" +#include "rxpcu_ppdu_end_layout_info.h" +#define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 28 + +#define NUM_OF_QWORDS_RXPCU_PPDU_END_INFO 14 + +struct rxpcu_ppdu_end_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t wb_timestamp_lower_32 : 32; + uint32_t wb_timestamp_upper_32 : 32; + uint32_t rx_antenna : 24, + tx_ht_vht_ack : 1, + unsupported_mu_nc : 1, + otp_txbf_disable : 1, + previous_tlv_corrupted : 1, + phyrx_abort_request_info_valid : 1, + macrx_abort_request_info_valid : 1, + reserved : 2; + uint32_t coex_bt_tx_from_start_of_rx : 1, + coex_bt_tx_after_start_of_rx : 1, + coex_wan_tx_from_start_of_rx : 1, + coex_wan_tx_after_start_of_rx : 1, + coex_wlan_tx_from_start_of_rx : 1, + coex_wlan_tx_after_start_of_rx : 1, + mpdu_delimiter_errors_seen : 1, + __reserved_g_0012 : 2, + dialog_token : 8, + follow_up_dialog_token : 8, + bb_captured_channel : 1, + bb_captured_reason : 3, + bb_captured_timeout : 1, + reserved_3 : 2; + uint32_t before_mpdu_count_passing_fcs : 10, + before_mpdu_count_failing_fcs : 10, + after_mpdu_count_passing_fcs : 10, + reserved_4 : 2; + uint32_t after_mpdu_count_failing_fcs : 10, + reserved_5 : 22; + uint32_t phy_timestamp_tx_lower_32 : 32; + uint32_t phy_timestamp_tx_upper_32 : 32; + uint32_t bb_length : 16, + bb_data : 1, + reserved_8 : 3, + first_bt_broadcast_status_details : 12; + uint32_t rx_ppdu_duration : 24, + reserved_9 : 8; + uint32_t ast_index : 16, + ast_index_valid : 1, + reserved_10 : 3, + second_bt_broadcast_status_details : 12; + struct phyrx_abort_request_info phyrx_abort_request_info_details; + struct macrx_abort_request_info macrx_abort_request_info_details; + uint16_t pre_bt_broadcast_status_details : 12, + reserved_12a : 4; + uint32_t non_qos_sn_info_valid : 1, + reserved_13a : 5, + non_qos_sn_highest : 12, + non_qos_sn_highest_retry_setting : 1, + non_qos_sn_lowest : 12, + non_qos_sn_lowest_retry_setting : 1; + uint32_t qos_sn_1_info_valid : 1, + reserved_14a : 1, + qos_sn_1_tid : 4, + qos_sn_1_highest : 12, + qos_sn_1_highest_retry_setting : 1, + qos_sn_1_lowest : 12, + qos_sn_1_lowest_retry_setting : 1; + uint32_t qos_sn_2_info_valid : 1, + reserved_15a : 1, + qos_sn_2_tid : 4, + qos_sn_2_highest : 12, + qos_sn_2_highest_retry_setting : 1, + qos_sn_2_lowest : 12, + qos_sn_2_lowest_retry_setting : 1; + struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; + uint32_t corrupted_due_to_fifo_delay : 1, + qos_sn_1_more_frag_state : 1, + qos_sn_1_frag_num_state : 4, + qos_sn_2_more_frag_state : 1, + qos_sn_2_frag_num_state : 4, + reserved_26a : 21; + uint32_t rx_ppdu_end_marker : 32; +#else + uint32_t wb_timestamp_lower_32 : 32; + uint32_t wb_timestamp_upper_32 : 32; + uint32_t reserved : 2, + macrx_abort_request_info_valid : 1, + phyrx_abort_request_info_valid : 1, + previous_tlv_corrupted : 1, + otp_txbf_disable : 1, + unsupported_mu_nc : 1, + tx_ht_vht_ack : 1, + rx_antenna : 24; + uint32_t reserved_3 : 2, + bb_captured_timeout : 1, + bb_captured_reason : 3, + bb_captured_channel : 1, + follow_up_dialog_token : 8, + dialog_token : 8, + __reserved_g_0012 : 2, + mpdu_delimiter_errors_seen : 1, + coex_wlan_tx_after_start_of_rx : 1, + coex_wlan_tx_from_start_of_rx : 1, + coex_wan_tx_after_start_of_rx : 1, + coex_wan_tx_from_start_of_rx : 1, + coex_bt_tx_after_start_of_rx : 1, + coex_bt_tx_from_start_of_rx : 1; + uint32_t reserved_4 : 2, + after_mpdu_count_passing_fcs : 10, + before_mpdu_count_failing_fcs : 10, + before_mpdu_count_passing_fcs : 10; + uint32_t reserved_5 : 22, + after_mpdu_count_failing_fcs : 10; + uint32_t phy_timestamp_tx_lower_32 : 32; + uint32_t phy_timestamp_tx_upper_32 : 32; + uint32_t first_bt_broadcast_status_details : 12, + reserved_8 : 3, + bb_data : 1, + bb_length : 16; + uint32_t reserved_9 : 8, + rx_ppdu_duration : 24; + uint32_t second_bt_broadcast_status_details : 12, + reserved_10 : 3, + ast_index_valid : 1, + ast_index : 16; + struct phyrx_abort_request_info phyrx_abort_request_info_details; + uint32_t reserved_12a : 4, + pre_bt_broadcast_status_details : 12; + struct macrx_abort_request_info macrx_abort_request_info_details; + uint32_t non_qos_sn_lowest_retry_setting : 1, + non_qos_sn_lowest : 12, + non_qos_sn_highest_retry_setting : 1, + non_qos_sn_highest : 12, + reserved_13a : 5, + non_qos_sn_info_valid : 1; + uint32_t qos_sn_1_lowest_retry_setting : 1, + qos_sn_1_lowest : 12, + qos_sn_1_highest_retry_setting : 1, + qos_sn_1_highest : 12, + qos_sn_1_tid : 4, + reserved_14a : 1, + qos_sn_1_info_valid : 1; + uint32_t qos_sn_2_lowest_retry_setting : 1, + qos_sn_2_lowest : 12, + qos_sn_2_highest_retry_setting : 1, + qos_sn_2_highest : 12, + qos_sn_2_tid : 4, + reserved_15a : 1, + qos_sn_2_info_valid : 1; + struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; + uint32_t reserved_26a : 21, + qos_sn_2_frag_num_state : 4, + qos_sn_2_more_frag_state : 1, + qos_sn_1_frag_num_state : 4, + qos_sn_1_more_frag_state : 1, + corrupted_due_to_fifo_delay : 1; + uint32_t rx_ppdu_end_marker : 32; +#endif +}; + +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MSB 31 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff + +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_LSB 32 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MSB 63 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 + +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_LSB 0 +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MSB 23 +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MASK 0x0000000000ffffff + +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_LSB 24 +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MSB 24 +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MASK 0x0000000001000000 + +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_LSB 25 +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MSB 25 +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MASK 0x0000000002000000 + +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_LSB 26 +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MSB 26 +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MASK 0x0000000004000000 + +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_LSB 27 +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MSB 27 +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MASK 0x0000000008000000 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MSB 28 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000010000000 + +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MSB 29 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000020000000 + +#define RXPCU_PPDU_END_INFO_RESERVED_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_RESERVED_LSB 30 +#define RXPCU_PPDU_END_INFO_RESERVED_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_MASK 0x00000000c0000000 + +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_LSB 32 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MSB 32 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MASK 0x0000000100000000 + +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_LSB 33 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MSB 33 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x0000000200000000 + +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_LSB 34 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MSB 34 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x0000000400000000 + +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_LSB 35 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MSB 35 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x0000000800000000 + +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_LSB 36 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MSB 36 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x0000001000000000 + +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 37 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MSB 37 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x0000002000000000 + +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_LSB 38 +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MSB 38 +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x0000004000000000 + +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_LSB 41 +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MSB 48 +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MASK 0x0001fe0000000000 + +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_LSB 49 +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MSB 56 +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe000000000000 + +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_LSB 57 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MSB 57 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MASK 0x0200000000000000 + +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_LSB 58 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MSB 60 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MASK 0x1c00000000000000 + +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_LSB 61 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MSB 61 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MASK 0x2000000000000000 + +#define RXPCU_PPDU_END_INFO_RESERVED_3_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_RESERVED_3_LSB 62 +#define RXPCU_PPDU_END_INFO_RESERVED_3_MSB 63 +#define RXPCU_PPDU_END_INFO_RESERVED_3_MASK 0xc000000000000000 + +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MSB 9 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x00000000000003ff + +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MSB 19 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x00000000000ffc00 + +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MSB 29 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x000000003ff00000 + +#define RXPCU_PPDU_END_INFO_RESERVED_4_OFFSET 0x0000000000000010 +#define RXPCU_PPDU_END_INFO_RESERVED_4_LSB 30 +#define RXPCU_PPDU_END_INFO_RESERVED_4_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_4_MASK 0x00000000c0000000 + +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_LSB 32 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MSB 41 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff00000000 + +#define RXPCU_PPDU_END_INFO_RESERVED_5_OFFSET 0x0000000000000010 +#define RXPCU_PPDU_END_INFO_RESERVED_5_LSB 42 +#define RXPCU_PPDU_END_INFO_RESERVED_5_MSB 63 +#define RXPCU_PPDU_END_INFO_RESERVED_5_MASK 0xfffffc0000000000 + +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x0000000000000018 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MSB 31 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MASK 0x00000000ffffffff + +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000000000000018 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_LSB 32 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MSB 63 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff00000000 + +#define RXPCU_PPDU_END_INFO_BB_LENGTH_OFFSET 0x0000000000000020 +#define RXPCU_PPDU_END_INFO_BB_LENGTH_LSB 0 +#define RXPCU_PPDU_END_INFO_BB_LENGTH_MSB 15 +#define RXPCU_PPDU_END_INFO_BB_LENGTH_MASK 0x000000000000ffff + +#define RXPCU_PPDU_END_INFO_BB_DATA_OFFSET 0x0000000000000020 +#define RXPCU_PPDU_END_INFO_BB_DATA_LSB 16 +#define RXPCU_PPDU_END_INFO_BB_DATA_MSB 16 +#define RXPCU_PPDU_END_INFO_BB_DATA_MASK 0x0000000000010000 + +#define RXPCU_PPDU_END_INFO_RESERVED_8_OFFSET 0x0000000000000020 +#define RXPCU_PPDU_END_INFO_RESERVED_8_LSB 17 +#define RXPCU_PPDU_END_INFO_RESERVED_8_MSB 19 +#define RXPCU_PPDU_END_INFO_RESERVED_8_MASK 0x00000000000e0000 + +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000020 +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 31 +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 + +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 0x0000000000000020 +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 32 +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MSB 55 +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 0x00ffffff00000000 + +#define RXPCU_PPDU_END_INFO_RESERVED_9_OFFSET 0x0000000000000020 +#define RXPCU_PPDU_END_INFO_RESERVED_9_LSB 56 +#define RXPCU_PPDU_END_INFO_RESERVED_9_MSB 63 +#define RXPCU_PPDU_END_INFO_RESERVED_9_MASK 0xff00000000000000 + +#define RXPCU_PPDU_END_INFO_AST_INDEX_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_AST_INDEX_LSB 0 +#define RXPCU_PPDU_END_INFO_AST_INDEX_MSB 15 +#define RXPCU_PPDU_END_INFO_AST_INDEX_MASK 0x000000000000ffff + +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_LSB 16 +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MSB 16 +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MASK 0x0000000000010000 + +#define RXPCU_PPDU_END_INFO_RESERVED_10_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_RESERVED_10_LSB 17 +#define RXPCU_PPDU_END_INFO_RESERVED_10_MSB 19 +#define RXPCU_PPDU_END_INFO_RESERVED_10_MASK 0x00000000000e0000 + +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 31 +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 32 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MSB 39 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff00000000 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 40 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MSB 40 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x0000010000000000 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 41 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MSB 41 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x0000020000000000 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 42 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 47 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000fc0000000000 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 48 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MSB 63 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff000000000000 + +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MSB 7 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000ff + +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 15 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x000000000000ff00 + +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 16 +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 27 +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x000000000fff0000 + +#define RXPCU_PPDU_END_INFO_RESERVED_12A_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_RESERVED_12A_LSB 28 +#define RXPCU_PPDU_END_INFO_RESERVED_12A_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_12A_MASK 0x00000000f0000000 + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_LSB 32 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MSB 32 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MASK 0x0000000100000000 + +#define RXPCU_PPDU_END_INFO_RESERVED_13A_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_RESERVED_13A_LSB 33 +#define RXPCU_PPDU_END_INFO_RESERVED_13A_MSB 37 +#define RXPCU_PPDU_END_INFO_RESERVED_13A_MASK 0x0000003e00000000 + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_LSB 38 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MSB 49 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MASK 0x0003ffc000000000 + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_LSB 50 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MSB 50 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_LSB 51 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MSB 62 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MASK 0x7ff8000000000000 + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_LSB 63 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MSB 63 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_LSB 0 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MSB 0 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MASK 0x0000000000000001 + +#define RXPCU_PPDU_END_INFO_RESERVED_14A_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_RESERVED_14A_LSB 1 +#define RXPCU_PPDU_END_INFO_RESERVED_14A_MSB 1 +#define RXPCU_PPDU_END_INFO_RESERVED_14A_MASK 0x0000000000000002 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_LSB 2 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MSB 5 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MASK 0x000000000000003c + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_LSB 6 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MSB 17 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MASK 0x000000000003ffc0 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_LSB 18 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MSB 18 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MASK 0x0000000000040000 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_LSB 19 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MSB 30 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MASK 0x000000007ff80000 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_LSB 31 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MSB 31 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MASK 0x0000000080000000 + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_LSB 32 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MSB 32 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MASK 0x0000000100000000 + +#define RXPCU_PPDU_END_INFO_RESERVED_15A_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_RESERVED_15A_LSB 33 +#define RXPCU_PPDU_END_INFO_RESERVED_15A_MSB 33 +#define RXPCU_PPDU_END_INFO_RESERVED_15A_MASK 0x0000000200000000 + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_LSB 34 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MSB 37 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MASK 0x0000003c00000000 + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_LSB 38 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MSB 49 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MASK 0x0003ffc000000000 + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_LSB 50 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MSB 50 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_LSB 51 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MSB 62 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MASK 0x7ff8000000000000 + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_LSB 63 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MSB 63 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MSB 1 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MASK 0x0000000000000003 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_LSB 2 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MASK 0x00000000000000fc + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_LSB 8 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MSB 13 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MASK 0x0000000000003f00 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_LSB 14 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MSB 19 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MASK 0x00000000000fc000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_LSB 20 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MSB 25 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MASK 0x0000000003f00000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_LSB 26 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MASK 0x00000000fc000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_LSB 32 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MSB 37 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MASK 0x0000003f00000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_LSB 38 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MSB 43 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc000000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_LSB 44 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MSB 49 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f00000000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_LSB 50 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MSB 55 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MASK 0x00fc000000000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_LSB 56 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MSB 62 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MASK 0x7f00000000000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_LSB 63 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MSB 63 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MASK 0x8000000000000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MSB 6 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MASK 0x000000000000007f + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_LSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MSB 13 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MASK 0x0000000000003f80 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_LSB 14 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MSB 20 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MASK 0x00000000001fc000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_LSB 21 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MSB 27 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MASK 0x000000000fe00000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_LSB 28 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MASK 0x00000000f0000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_LSB 32 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MSB 38 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f00000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_LSB 39 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MSB 45 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f8000000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_LSB 46 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MSB 52 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc00000000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_LSB 53 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MSB 59 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe0000000000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_LSB 60 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MSB 63 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MASK 0xf000000000000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MSB 6 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MASK 0x000000000000007f + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_LSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MSB 13 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MASK 0x0000000000003f80 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_LSB 14 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MSB 20 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MASK 0x00000000001fc000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x000000000fe00000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x0000000010000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_LSB 29 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MASK 0x00000000e0000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_LSB 32 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MSB 38 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MASK 0x0000007f00000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_LSB 39 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MSB 46 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f8000000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 47 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 47 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x0000800000000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 48 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 55 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff000000000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 56 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 56 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x0100000000000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_LSB 57 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MSB 63 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MASK 0xfe00000000000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MASK 0x00000000000000ff + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_LSB 8 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MSB 15 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MASK 0x000000000000ff00 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_LSB 16 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MSB 23 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MASK 0x0000000000ff0000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_LSB 24 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MASK 0x00000000ff000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_LSB 40 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MSB 47 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MASK 0x0000ff0000000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_LSB 48 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MSB 55 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff000000000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_LSB 56 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MSB 63 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MASK 0xff00000000000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_OFFSET 0x0000000000000060 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MASK 0x00000000ffffffff + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_OFFSET 0x0000000000000060 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_LSB 32 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MSB 63 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MASK 0xffffffff00000000 + +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0 +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0 +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000000000001 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_LSB 1 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MSB 1 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MASK 0x0000000000000002 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_LSB 2 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MSB 5 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MASK 0x000000000000003c + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_LSB 6 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MSB 6 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MASK 0x0000000000000040 + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_LSB 7 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MSB 10 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MASK 0x0000000000000780 + +#define RXPCU_PPDU_END_INFO_RESERVED_26A_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_RESERVED_26A_LSB 11 +#define RXPCU_PPDU_END_INFO_RESERVED_26A_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_26A_MASK 0x00000000fffff800 + +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_LSB 32 +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MSB 63 +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/rxpcu_ppdu_end_layout_info.h b/hw/kiwi/v2/rxpcu_ppdu_end_layout_info.h new file mode 100644 index 000000000000..f393a75a84c3 --- /dev/null +++ b/hw/kiwi/v2/rxpcu_ppdu_end_layout_info.h @@ -0,0 +1,338 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RXPCU_PPDU_END_LAYOUT_INFO_H_ +#define _RXPCU_PPDU_END_LAYOUT_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RXPCU_PPDU_END_LAYOUT_INFO 10 + +struct rxpcu_ppdu_end_layout_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rssi_legacy_offset : 2, + l_sig_a_offset : 6, + l_sig_b_offset : 6, + ht_sig_offset : 6, + vht_sig_a_offset : 6, + repeat_l_sig_a_offset : 6; + uint32_t he_sig_a_su_offset : 6, + he_sig_a_mu_dl_offset : 6, + he_sig_a_mu_ul_offset : 6, + generic_u_sig_offset : 6, + rssi_ht_offset : 7, + reserved_1a : 1; + uint32_t vht_sig_b_su20_offset : 7, + vht_sig_b_su40_offset : 7, + vht_sig_b_su80_offset : 7, + vht_sig_b_su160_offset : 7, + reserved_2a : 4; + uint32_t vht_sig_b_mu20_offset : 7, + vht_sig_b_mu40_offset : 7, + vht_sig_b_mu80_offset : 7, + vht_sig_b_mu160_offset : 7, + reserved_3a : 4; + uint32_t he_sig_b1_mu_offset : 7, + he_sig_b2_mu_offset : 7, + he_sig_b2_ofdma_offset : 7, + first_generic_eht_sig_offset : 7, + multiple_generic_eht_sig_included : 1, + reserved_4a : 3; + uint32_t common_user_info_offset : 7, + first_debug_info_offset : 8, + multiple_debug_info_included : 1, + first_other_receive_info_offset : 8, + multiple_other_receive_info_included : 1, + reserved_5a : 7; + uint32_t data_done_offset : 8, + generated_cbf_details_offset : 8, + pkt_end_part1_offset : 8, + location_offset : 8; + uint32_t __reserved_g_0011 : 8, + pkt_end_offset : 8, + abort_request_ack_offset : 8, + reserved_7a : 8; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; +#else + uint32_t repeat_l_sig_a_offset : 6, + vht_sig_a_offset : 6, + ht_sig_offset : 6, + l_sig_b_offset : 6, + l_sig_a_offset : 6, + rssi_legacy_offset : 2; + uint32_t reserved_1a : 1, + rssi_ht_offset : 7, + generic_u_sig_offset : 6, + he_sig_a_mu_ul_offset : 6, + he_sig_a_mu_dl_offset : 6, + he_sig_a_su_offset : 6; + uint32_t reserved_2a : 4, + vht_sig_b_su160_offset : 7, + vht_sig_b_su80_offset : 7, + vht_sig_b_su40_offset : 7, + vht_sig_b_su20_offset : 7; + uint32_t reserved_3a : 4, + vht_sig_b_mu160_offset : 7, + vht_sig_b_mu80_offset : 7, + vht_sig_b_mu40_offset : 7, + vht_sig_b_mu20_offset : 7; + uint32_t reserved_4a : 3, + multiple_generic_eht_sig_included : 1, + first_generic_eht_sig_offset : 7, + he_sig_b2_ofdma_offset : 7, + he_sig_b2_mu_offset : 7, + he_sig_b1_mu_offset : 7; + uint32_t reserved_5a : 7, + multiple_other_receive_info_included : 1, + first_other_receive_info_offset : 8, + multiple_debug_info_included : 1, + first_debug_info_offset : 8, + common_user_info_offset : 7; + uint32_t location_offset : 8, + pkt_end_part1_offset : 8, + generated_cbf_details_offset : 8, + data_done_offset : 8; + uint32_t reserved_7a : 8, + abort_request_ack_offset : 8, + pkt_end_offset : 8, + __reserved_g_0011 : 8; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; +#endif +}; + +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MSB 1 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MASK 0x00000003 + +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_LSB 2 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MASK 0x000000fc + +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_LSB 8 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MASK 0x00003f00 + +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MSB 19 +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MASK 0x000fc000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_LSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MSB 25 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MASK 0x03f00000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_LSB 26 +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MASK 0xfc000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MSB 5 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MASK 0x0000003f + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_LSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MSB 11 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc0 + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_LSB 12 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MSB 17 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_LSB 18 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MASK 0x00fc0000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MSB 30 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MASK 0x7f000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_LSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MASK 0x80000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MASK 0x00003f80 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MASK 0x001fc000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_LSB 21 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MSB 27 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MASK 0x0fe00000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_LSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MASK 0xf0000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f80 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_LSB 21 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MSB 27 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe00000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_LSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MASK 0xf0000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MASK 0x00003f80 + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MASK 0x001fc000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x0fe00000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x10000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_LSB 29 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MASK 0xe0000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f80 + +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x00008000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 16 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff0000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x01000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_LSB 25 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MASK 0xfe000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MASK 0x000000ff + +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_LSB 8 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MASK 0x0000ff00 + +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_LSB 16 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MASK 0x00ff0000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MASK 0xff000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_OFFSET 0x0000001c +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_LSB 8 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MASK 0x0000ff00 + +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000001c +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_LSB 16 +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff0000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_OFFSET 0x0000001c +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MASK 0xff000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_OFFSET 0x00000020 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MASK 0xffffffff + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_OFFSET 0x00000024 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MASK 0xffffffff + +#endif diff --git a/hw/kiwi/v2/rxpt_classify_info.h b/hw/kiwi/v2/rxpt_classify_info.h new file mode 100644 index 000000000000..a095bb7cb0da --- /dev/null +++ b/hw/kiwi/v2/rxpt_classify_info.h @@ -0,0 +1,133 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RXPT_CLASSIFY_INFO_H_ +#define _RXPT_CLASSIFY_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1 + +struct rxpt_classify_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_destination_indication : 5, + lmac_peer_id_msb : 2, + use_flow_id_toeplitz_clfy : 1, + pkt_selection_fp_ucast_data : 1, + pkt_selection_fp_mcast_data : 1, + pkt_selection_fp_1000 : 1, + rxdma0_source_ring_selection : 3, + rxdma0_destination_ring_selection : 3, + mcast_echo_drop_enable : 1, + wds_learning_detect_en : 1, + intrabss_check_en : 1, + use_ppe : 1, + ppe_routing_enable : 1, + reserved_0b : 10; +#else + uint32_t reserved_0b : 10, + ppe_routing_enable : 1, + use_ppe : 1, + intrabss_check_en : 1, + wds_learning_detect_en : 1, + mcast_echo_drop_enable : 1, + rxdma0_destination_ring_selection : 3, + rxdma0_source_ring_selection : 3, + pkt_selection_fp_1000 : 1, + pkt_selection_fp_mcast_data : 1, + pkt_selection_fp_ucast_data : 1, + use_flow_id_toeplitz_clfy : 1, + lmac_peer_id_msb : 2, + reo_destination_indication : 5; +#endif +}; + +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_LSB 0 +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MSB 4 +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_LSB 5 +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MSB 6 +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MASK 0x00000060 + +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MSB 8 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MSB 9 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_LSB 10 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MSB 10 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MASK 0x00000400 + +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MSB 13 +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 + +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 + +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_LSB 17 +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MSB 17 +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 + +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_LSB 18 +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MSB 18 +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MASK 0x00040000 + +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_LSB 19 +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MSB 19 +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MASK 0x00080000 + +#define RXPT_CLASSIFY_INFO_USE_PPE_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_USE_PPE_LSB 20 +#define RXPT_CLASSIFY_INFO_USE_PPE_MSB 20 +#define RXPT_CLASSIFY_INFO_USE_PPE_MASK 0x00100000 + +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_LSB 21 +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MSB 21 +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MASK 0x00200000 + +#define RXPT_CLASSIFY_INFO_RESERVED_0B_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_RESERVED_0B_LSB 22 +#define RXPT_CLASSIFY_INFO_RESERVED_0B_MSB 31 +#define RXPT_CLASSIFY_INFO_RESERVED_0B_MASK 0xffc00000 + +#endif diff --git a/hw/kiwi/v2/seq_hwio.h b/hw/kiwi/v2/seq_hwio.h new file mode 100644 index 000000000000..9cfdb9284c60 --- /dev/null +++ b/hw/kiwi/v2/seq_hwio.h @@ -0,0 +1,56 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef __SEQ_H__ +#define __SEQ_H__ + +#include "HALhwio.h" + +#define SEQ_INH(base, regtype, reg) \ + SEQ_##regtype##_INH(base, reg) + +#define SEQ_INMH(base, regtype, reg, mask) \ + SEQ_##regtype##_INMH(base, reg, mask) + +#define SEQ_INFH(base, regtype, reg, fld) \ + (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld)) + +#define SEQ_OUTH(base, regtype, reg, val) \ + SEQ_##regtype##_OUTH(base, reg, val) + +#define SEQ_OUTMH(base, regtype, reg, mask, val) \ + SEQ_##regtype##_OUTMH(base, reg, mask, val) + +#define SEQ_OUTFH(base, regtype, reg, fld, val) \ + SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld)) + +typedef enum { + SEC, + MS, + US, + NS +} SEQ_TimeUnit; + +extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit); + +extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt); + +#endif diff --git a/hw/kiwi/v2/tcl_data_cmd.h b/hw/kiwi/v2/tcl_data_cmd.h new file mode 100644 index 000000000000..e40cfbb3fd09 --- /dev/null +++ b/hw/kiwi/v2/tcl_data_cmd.h @@ -0,0 +1,296 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TCL_DATA_CMD_H_ +#define _TCL_DATA_CMD_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_TCL_DATA_CMD 8 + +struct tcl_data_cmd { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buf_addr_info; + uint32_t tcl_cmd_type : 1, + buf_or_ext_desc_type : 1, + bank_id : 6, + tx_notify_frame : 3, + header_length_read_sel : 1, + buffer_timestamp : 19, + buffer_timestamp_valid : 1; + uint32_t reserved_3a : 16, + tcl_cmd_number : 16; + uint32_t data_length : 16, + ipv4_checksum_en : 1, + udp_over_ipv4_checksum_en : 1, + udp_over_ipv6_checksum_en : 1, + tcp_over_ipv4_checksum_en : 1, + tcp_over_ipv6_checksum_en : 1, + to_fw : 1, + reserved_4a : 1, + packet_offset : 9; + uint32_t hlos_tid_overwrite : 1, + flow_override_enable : 1, + who_classify_info_sel : 2, + hlos_tid : 4, + flow_override : 1, + pmac_id : 2, + msdu_color : 2, + reserved_5a : 11, + vdev_id : 8; + uint32_t search_index : 20, + cache_set_num : 4, + index_lookup_override : 1, + reserved_6a : 7; + uint32_t reserved_7a : 20, + ring_id : 8, + looping_count : 4; +#else + struct buffer_addr_info buf_addr_info; + uint32_t buffer_timestamp_valid : 1, + buffer_timestamp : 19, + header_length_read_sel : 1, + tx_notify_frame : 3, + bank_id : 6, + buf_or_ext_desc_type : 1, + tcl_cmd_type : 1; + uint32_t tcl_cmd_number : 16, + reserved_3a : 16; + uint32_t packet_offset : 9, + reserved_4a : 1, + to_fw : 1, + tcp_over_ipv6_checksum_en : 1, + tcp_over_ipv4_checksum_en : 1, + udp_over_ipv6_checksum_en : 1, + udp_over_ipv4_checksum_en : 1, + ipv4_checksum_en : 1, + data_length : 16; + uint32_t vdev_id : 8, + reserved_5a : 11, + msdu_color : 2, + pmac_id : 2, + flow_override : 1, + hlos_tid : 4, + who_classify_info_sel : 2, + flow_override_enable : 1, + hlos_tid_overwrite : 1; + uint32_t reserved_6a : 7, + index_lookup_override : 1, + cache_set_num : 4, + search_index : 20; + uint32_t looping_count : 4, + ring_id : 8, + reserved_7a : 20; +#endif +}; + +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define TCL_DATA_CMD_TCL_CMD_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_TCL_CMD_TYPE_LSB 0 +#define TCL_DATA_CMD_TCL_CMD_TYPE_MSB 0 +#define TCL_DATA_CMD_TCL_CMD_TYPE_MASK 0x00000001 + +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 1 +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MSB 1 +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 0x00000002 + +#define TCL_DATA_CMD_BANK_ID_OFFSET 0x00000008 +#define TCL_DATA_CMD_BANK_ID_LSB 2 +#define TCL_DATA_CMD_BANK_ID_MSB 7 +#define TCL_DATA_CMD_BANK_ID_MASK 0x000000fc + +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_OFFSET 0x00000008 +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_LSB 8 +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MSB 10 +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MASK 0x00000700 + +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_OFFSET 0x00000008 +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_LSB 11 +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MSB 11 +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MASK 0x00000800 + +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_OFFSET 0x00000008 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_LSB 12 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MSB 30 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MASK 0x7ffff000 + +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000008 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_LSB 31 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MSB 31 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MASK 0x80000000 + +#define TCL_DATA_CMD_RESERVED_3A_OFFSET 0x0000000c +#define TCL_DATA_CMD_RESERVED_3A_LSB 0 +#define TCL_DATA_CMD_RESERVED_3A_MSB 15 +#define TCL_DATA_CMD_RESERVED_3A_MASK 0x0000ffff + +#define TCL_DATA_CMD_TCL_CMD_NUMBER_OFFSET 0x0000000c +#define TCL_DATA_CMD_TCL_CMD_NUMBER_LSB 16 +#define TCL_DATA_CMD_TCL_CMD_NUMBER_MSB 31 +#define TCL_DATA_CMD_TCL_CMD_NUMBER_MASK 0xffff0000 + +#define TCL_DATA_CMD_DATA_LENGTH_OFFSET 0x00000010 +#define TCL_DATA_CMD_DATA_LENGTH_LSB 0 +#define TCL_DATA_CMD_DATA_LENGTH_MSB 15 +#define TCL_DATA_CMD_DATA_LENGTH_MASK 0x0000ffff + +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_LSB 16 +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MSB 16 +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MASK 0x00010000 + +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_LSB 17 +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MSB 17 +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00020000 + +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_LSB 18 +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MSB 18 +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00040000 + +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_LSB 19 +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MSB 19 +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00080000 + +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_LSB 20 +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MSB 20 +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00100000 + +#define TCL_DATA_CMD_TO_FW_OFFSET 0x00000010 +#define TCL_DATA_CMD_TO_FW_LSB 21 +#define TCL_DATA_CMD_TO_FW_MSB 21 +#define TCL_DATA_CMD_TO_FW_MASK 0x00200000 + +#define TCL_DATA_CMD_RESERVED_4A_OFFSET 0x00000010 +#define TCL_DATA_CMD_RESERVED_4A_LSB 22 +#define TCL_DATA_CMD_RESERVED_4A_MSB 22 +#define TCL_DATA_CMD_RESERVED_4A_MASK 0x00400000 + +#define TCL_DATA_CMD_PACKET_OFFSET_OFFSET 0x00000010 +#define TCL_DATA_CMD_PACKET_OFFSET_LSB 23 +#define TCL_DATA_CMD_PACKET_OFFSET_MSB 31 +#define TCL_DATA_CMD_PACKET_OFFSET_MASK 0xff800000 + +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_OFFSET 0x00000014 +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_LSB 0 +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MSB 0 +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MASK 0x00000001 + +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_OFFSET 0x00000014 +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_LSB 1 +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MSB 1 +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MASK 0x00000002 + +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_OFFSET 0x00000014 +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_LSB 2 +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MSB 3 +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MASK 0x0000000c + +#define TCL_DATA_CMD_HLOS_TID_OFFSET 0x00000014 +#define TCL_DATA_CMD_HLOS_TID_LSB 4 +#define TCL_DATA_CMD_HLOS_TID_MSB 7 +#define TCL_DATA_CMD_HLOS_TID_MASK 0x000000f0 + +#define TCL_DATA_CMD_FLOW_OVERRIDE_OFFSET 0x00000014 +#define TCL_DATA_CMD_FLOW_OVERRIDE_LSB 8 +#define TCL_DATA_CMD_FLOW_OVERRIDE_MSB 8 +#define TCL_DATA_CMD_FLOW_OVERRIDE_MASK 0x00000100 + +#define TCL_DATA_CMD_PMAC_ID_OFFSET 0x00000014 +#define TCL_DATA_CMD_PMAC_ID_LSB 9 +#define TCL_DATA_CMD_PMAC_ID_MSB 10 +#define TCL_DATA_CMD_PMAC_ID_MASK 0x00000600 + +#define TCL_DATA_CMD_MSDU_COLOR_OFFSET 0x00000014 +#define TCL_DATA_CMD_MSDU_COLOR_LSB 11 +#define TCL_DATA_CMD_MSDU_COLOR_MSB 12 +#define TCL_DATA_CMD_MSDU_COLOR_MASK 0x00001800 + +#define TCL_DATA_CMD_RESERVED_5A_OFFSET 0x00000014 +#define TCL_DATA_CMD_RESERVED_5A_LSB 13 +#define TCL_DATA_CMD_RESERVED_5A_MSB 23 +#define TCL_DATA_CMD_RESERVED_5A_MASK 0x00ffe000 + +#define TCL_DATA_CMD_VDEV_ID_OFFSET 0x00000014 +#define TCL_DATA_CMD_VDEV_ID_LSB 24 +#define TCL_DATA_CMD_VDEV_ID_MSB 31 +#define TCL_DATA_CMD_VDEV_ID_MASK 0xff000000 + +#define TCL_DATA_CMD_SEARCH_INDEX_OFFSET 0x00000018 +#define TCL_DATA_CMD_SEARCH_INDEX_LSB 0 +#define TCL_DATA_CMD_SEARCH_INDEX_MSB 19 +#define TCL_DATA_CMD_SEARCH_INDEX_MASK 0x000fffff + +#define TCL_DATA_CMD_CACHE_SET_NUM_OFFSET 0x00000018 +#define TCL_DATA_CMD_CACHE_SET_NUM_LSB 20 +#define TCL_DATA_CMD_CACHE_SET_NUM_MSB 23 +#define TCL_DATA_CMD_CACHE_SET_NUM_MASK 0x00f00000 + +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_OFFSET 0x00000018 +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_LSB 24 +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MSB 24 +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MASK 0x01000000 + +#define TCL_DATA_CMD_RESERVED_6A_OFFSET 0x00000018 +#define TCL_DATA_CMD_RESERVED_6A_LSB 25 +#define TCL_DATA_CMD_RESERVED_6A_MSB 31 +#define TCL_DATA_CMD_RESERVED_6A_MASK 0xfe000000 + +#define TCL_DATA_CMD_RESERVED_7A_OFFSET 0x0000001c +#define TCL_DATA_CMD_RESERVED_7A_LSB 0 +#define TCL_DATA_CMD_RESERVED_7A_MSB 19 +#define TCL_DATA_CMD_RESERVED_7A_MASK 0x000fffff + +#define TCL_DATA_CMD_RING_ID_OFFSET 0x0000001c +#define TCL_DATA_CMD_RING_ID_LSB 20 +#define TCL_DATA_CMD_RING_ID_MSB 27 +#define TCL_DATA_CMD_RING_ID_MASK 0x0ff00000 + +#define TCL_DATA_CMD_LOOPING_COUNT_OFFSET 0x0000001c +#define TCL_DATA_CMD_LOOPING_COUNT_LSB 28 +#define TCL_DATA_CMD_LOOPING_COUNT_MSB 31 +#define TCL_DATA_CMD_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/kiwi/v2/tcl_gse_cmd.h b/hw/kiwi/v2/tcl_gse_cmd.h new file mode 100644 index 000000000000..d109f74cfdd7 --- /dev/null +++ b/hw/kiwi/v2/tcl_gse_cmd.h @@ -0,0 +1,161 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TCL_GSE_CMD_H_ +#define _TCL_GSE_CMD_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TCL_GSE_CMD 8 + +struct tcl_gse_cmd { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t control_buffer_addr_31_0 : 32; + uint32_t control_buffer_addr_39_32 : 8, + gse_ctrl : 4, + gse_sel : 1, + status_destination_ring_id : 1, + swap : 1, + index_search_en : 1, + cache_set_num : 4, + reserved_1a : 12; + uint32_t tcl_cmd_type : 1, + reserved_2a : 31; + uint32_t cmd_meta_data_31_0 : 32; + uint32_t cmd_meta_data_63_32 : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 20, + ring_id : 8, + looping_count : 4; +#else + uint32_t control_buffer_addr_31_0 : 32; + uint32_t reserved_1a : 12, + cache_set_num : 4, + index_search_en : 1, + swap : 1, + status_destination_ring_id : 1, + gse_sel : 1, + gse_ctrl : 4, + control_buffer_addr_39_32 : 8; + uint32_t reserved_2a : 31, + tcl_cmd_type : 1; + uint32_t cmd_meta_data_31_0 : 32; + uint32_t cmd_meta_data_63_32 : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t looping_count : 4, + ring_id : 8, + reserved_7a : 20; +#endif +}; + +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_LSB 0 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MSB 31 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_LSB 0 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MSB 7 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define TCL_GSE_CMD_GSE_CTRL_OFFSET 0x00000004 +#define TCL_GSE_CMD_GSE_CTRL_LSB 8 +#define TCL_GSE_CMD_GSE_CTRL_MSB 11 +#define TCL_GSE_CMD_GSE_CTRL_MASK 0x00000f00 + +#define TCL_GSE_CMD_GSE_SEL_OFFSET 0x00000004 +#define TCL_GSE_CMD_GSE_SEL_LSB 12 +#define TCL_GSE_CMD_GSE_SEL_MSB 12 +#define TCL_GSE_CMD_GSE_SEL_MASK 0x00001000 + +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004 +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_LSB 13 +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MSB 13 +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MASK 0x00002000 + +#define TCL_GSE_CMD_SWAP_OFFSET 0x00000004 +#define TCL_GSE_CMD_SWAP_LSB 14 +#define TCL_GSE_CMD_SWAP_MSB 14 +#define TCL_GSE_CMD_SWAP_MASK 0x00004000 + +#define TCL_GSE_CMD_INDEX_SEARCH_EN_OFFSET 0x00000004 +#define TCL_GSE_CMD_INDEX_SEARCH_EN_LSB 15 +#define TCL_GSE_CMD_INDEX_SEARCH_EN_MSB 15 +#define TCL_GSE_CMD_INDEX_SEARCH_EN_MASK 0x00008000 + +#define TCL_GSE_CMD_CACHE_SET_NUM_OFFSET 0x00000004 +#define TCL_GSE_CMD_CACHE_SET_NUM_LSB 16 +#define TCL_GSE_CMD_CACHE_SET_NUM_MSB 19 +#define TCL_GSE_CMD_CACHE_SET_NUM_MASK 0x000f0000 + +#define TCL_GSE_CMD_RESERVED_1A_OFFSET 0x00000004 +#define TCL_GSE_CMD_RESERVED_1A_LSB 20 +#define TCL_GSE_CMD_RESERVED_1A_MSB 31 +#define TCL_GSE_CMD_RESERVED_1A_MASK 0xfff00000 + +#define TCL_GSE_CMD_TCL_CMD_TYPE_OFFSET 0x00000008 +#define TCL_GSE_CMD_TCL_CMD_TYPE_LSB 0 +#define TCL_GSE_CMD_TCL_CMD_TYPE_MSB 0 +#define TCL_GSE_CMD_TCL_CMD_TYPE_MASK 0x00000001 + +#define TCL_GSE_CMD_RESERVED_2A_OFFSET 0x00000008 +#define TCL_GSE_CMD_RESERVED_2A_LSB 1 +#define TCL_GSE_CMD_RESERVED_2A_MSB 31 +#define TCL_GSE_CMD_RESERVED_2A_MASK 0xfffffffe + +#define TCL_GSE_CMD_CMD_META_DATA_31_0_OFFSET 0x0000000c +#define TCL_GSE_CMD_CMD_META_DATA_31_0_LSB 0 +#define TCL_GSE_CMD_CMD_META_DATA_31_0_MSB 31 +#define TCL_GSE_CMD_CMD_META_DATA_31_0_MASK 0xffffffff + +#define TCL_GSE_CMD_CMD_META_DATA_63_32_OFFSET 0x00000010 +#define TCL_GSE_CMD_CMD_META_DATA_63_32_LSB 0 +#define TCL_GSE_CMD_CMD_META_DATA_63_32_MSB 31 +#define TCL_GSE_CMD_CMD_META_DATA_63_32_MASK 0xffffffff + +#define TCL_GSE_CMD_RESERVED_5A_OFFSET 0x00000014 +#define TCL_GSE_CMD_RESERVED_5A_LSB 0 +#define TCL_GSE_CMD_RESERVED_5A_MSB 31 +#define TCL_GSE_CMD_RESERVED_5A_MASK 0xffffffff + +#define TCL_GSE_CMD_RESERVED_6A_OFFSET 0x00000018 +#define TCL_GSE_CMD_RESERVED_6A_LSB 0 +#define TCL_GSE_CMD_RESERVED_6A_MSB 31 +#define TCL_GSE_CMD_RESERVED_6A_MASK 0xffffffff + +#define TCL_GSE_CMD_RESERVED_7A_OFFSET 0x0000001c +#define TCL_GSE_CMD_RESERVED_7A_LSB 0 +#define TCL_GSE_CMD_RESERVED_7A_MSB 19 +#define TCL_GSE_CMD_RESERVED_7A_MASK 0x000fffff + +#define TCL_GSE_CMD_RING_ID_OFFSET 0x0000001c +#define TCL_GSE_CMD_RING_ID_LSB 20 +#define TCL_GSE_CMD_RING_ID_MSB 27 +#define TCL_GSE_CMD_RING_ID_MASK 0x0ff00000 + +#define TCL_GSE_CMD_LOOPING_COUNT_OFFSET 0x0000001c +#define TCL_GSE_CMD_LOOPING_COUNT_LSB 28 +#define TCL_GSE_CMD_LOOPING_COUNT_MSB 31 +#define TCL_GSE_CMD_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/kiwi/v2/tcl_status_ring.h b/hw/kiwi/v2/tcl_status_ring.h new file mode 100644 index 000000000000..fe47a1dc94ee --- /dev/null +++ b/hw/kiwi/v2/tcl_status_ring.h @@ -0,0 +1,147 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TCL_STATUS_RING_H_ +#define _TCL_STATUS_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TCL_STATUS_RING 8 + +struct tcl_status_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t gse_ctrl : 4, + ase_fse_sel : 1, + cache_op_res : 2, + index_search_en : 1, + msdu_cnt_n : 24; + uint32_t msdu_byte_cnt_n : 32; + uint32_t msdu_timestmp_n : 32; + uint32_t cmd_meta_data_31_0 : 32; + uint32_t cmd_meta_data_63_32 : 32; + uint32_t hash_indx_val : 20, + cache_set_num : 4, + reserved_5a : 8; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 20, + ring_id : 8, + looping_count : 4; +#else + uint32_t msdu_cnt_n : 24, + index_search_en : 1, + cache_op_res : 2, + ase_fse_sel : 1, + gse_ctrl : 4; + uint32_t msdu_byte_cnt_n : 32; + uint32_t msdu_timestmp_n : 32; + uint32_t cmd_meta_data_31_0 : 32; + uint32_t cmd_meta_data_63_32 : 32; + uint32_t reserved_5a : 8, + cache_set_num : 4, + hash_indx_val : 20; + uint32_t reserved_6a : 32; + uint32_t looping_count : 4, + ring_id : 8, + reserved_7a : 20; +#endif +}; + +#define TCL_STATUS_RING_GSE_CTRL_OFFSET 0x00000000 +#define TCL_STATUS_RING_GSE_CTRL_LSB 0 +#define TCL_STATUS_RING_GSE_CTRL_MSB 3 +#define TCL_STATUS_RING_GSE_CTRL_MASK 0x0000000f + +#define TCL_STATUS_RING_ASE_FSE_SEL_OFFSET 0x00000000 +#define TCL_STATUS_RING_ASE_FSE_SEL_LSB 4 +#define TCL_STATUS_RING_ASE_FSE_SEL_MSB 4 +#define TCL_STATUS_RING_ASE_FSE_SEL_MASK 0x00000010 + +#define TCL_STATUS_RING_CACHE_OP_RES_OFFSET 0x00000000 +#define TCL_STATUS_RING_CACHE_OP_RES_LSB 5 +#define TCL_STATUS_RING_CACHE_OP_RES_MSB 6 +#define TCL_STATUS_RING_CACHE_OP_RES_MASK 0x00000060 + +#define TCL_STATUS_RING_INDEX_SEARCH_EN_OFFSET 0x00000000 +#define TCL_STATUS_RING_INDEX_SEARCH_EN_LSB 7 +#define TCL_STATUS_RING_INDEX_SEARCH_EN_MSB 7 +#define TCL_STATUS_RING_INDEX_SEARCH_EN_MASK 0x00000080 + +#define TCL_STATUS_RING_MSDU_CNT_N_OFFSET 0x00000000 +#define TCL_STATUS_RING_MSDU_CNT_N_LSB 8 +#define TCL_STATUS_RING_MSDU_CNT_N_MSB 31 +#define TCL_STATUS_RING_MSDU_CNT_N_MASK 0xffffff00 + +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_OFFSET 0x00000004 +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_LSB 0 +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MSB 31 +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MASK 0xffffffff + +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_OFFSET 0x00000008 +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_LSB 0 +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MSB 31 +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MASK 0xffffffff + +#define TCL_STATUS_RING_CMD_META_DATA_31_0_OFFSET 0x0000000c +#define TCL_STATUS_RING_CMD_META_DATA_31_0_LSB 0 +#define TCL_STATUS_RING_CMD_META_DATA_31_0_MSB 31 +#define TCL_STATUS_RING_CMD_META_DATA_31_0_MASK 0xffffffff + +#define TCL_STATUS_RING_CMD_META_DATA_63_32_OFFSET 0x00000010 +#define TCL_STATUS_RING_CMD_META_DATA_63_32_LSB 0 +#define TCL_STATUS_RING_CMD_META_DATA_63_32_MSB 31 +#define TCL_STATUS_RING_CMD_META_DATA_63_32_MASK 0xffffffff + +#define TCL_STATUS_RING_HASH_INDX_VAL_OFFSET 0x00000014 +#define TCL_STATUS_RING_HASH_INDX_VAL_LSB 0 +#define TCL_STATUS_RING_HASH_INDX_VAL_MSB 19 +#define TCL_STATUS_RING_HASH_INDX_VAL_MASK 0x000fffff + +#define TCL_STATUS_RING_CACHE_SET_NUM_OFFSET 0x00000014 +#define TCL_STATUS_RING_CACHE_SET_NUM_LSB 20 +#define TCL_STATUS_RING_CACHE_SET_NUM_MSB 23 +#define TCL_STATUS_RING_CACHE_SET_NUM_MASK 0x00f00000 + +#define TCL_STATUS_RING_RESERVED_5A_OFFSET 0x00000014 +#define TCL_STATUS_RING_RESERVED_5A_LSB 24 +#define TCL_STATUS_RING_RESERVED_5A_MSB 31 +#define TCL_STATUS_RING_RESERVED_5A_MASK 0xff000000 + +#define TCL_STATUS_RING_RESERVED_6A_OFFSET 0x00000018 +#define TCL_STATUS_RING_RESERVED_6A_LSB 0 +#define TCL_STATUS_RING_RESERVED_6A_MSB 31 +#define TCL_STATUS_RING_RESERVED_6A_MASK 0xffffffff + +#define TCL_STATUS_RING_RESERVED_7A_OFFSET 0x0000001c +#define TCL_STATUS_RING_RESERVED_7A_LSB 0 +#define TCL_STATUS_RING_RESERVED_7A_MSB 19 +#define TCL_STATUS_RING_RESERVED_7A_MASK 0x000fffff + +#define TCL_STATUS_RING_RING_ID_OFFSET 0x0000001c +#define TCL_STATUS_RING_RING_ID_LSB 20 +#define TCL_STATUS_RING_RING_ID_MSB 27 +#define TCL_STATUS_RING_RING_ID_MASK 0x0ff00000 + +#define TCL_STATUS_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define TCL_STATUS_RING_LOOPING_COUNT_LSB 28 +#define TCL_STATUS_RING_LOOPING_COUNT_MSB 31 +#define TCL_STATUS_RING_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/kiwi/v2/tlv_hdr.h b/hw/kiwi/v2/tlv_hdr.h new file mode 100644 index 000000000000..a370db48ea76 --- /dev/null +++ b/hw/kiwi/v2/tlv_hdr.h @@ -0,0 +1,424 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TLV_HDR_H_ +#define _TLV_HDR_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define _TLV_USERID_WIDTH_ 6 +#define _TLV_DATA_WIDTH_ 32 +#define _TLV_TAG_WIDTH_ 9 + +#define _TLV_MRV_EN_LEN_WIDTH_ 9 +#define _TLV_MRV_DIS_LEN_WIDTH_ 12 + +#define _TLV_16_DATA_WIDTH_ 16 +#define _TLV_16_TAG_WIDTH_ 5 +#define _TLV_16_LEN_WIDTH_ 4 +#define _TLV_CTAG_WIDTH_ 5 +#define _TLV_44_DATA_WIDTH_ 44 +#define _TLV_64_DATA_WIDTH_ 64 +#define _TLV_76_DATA_WIDTH_ 64 +#define _TLV_CDATA_WIDTH_ 32 +#define _TLV_CDATA_76_WIDTH_ 64 + +struct tlv_usr_16_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint16_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_16_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t tlv_cflg_reserved : 1, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_reserved : 6; +#else + uint16_t tlv_reserved : 6, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_mac_usr_32_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_mac_32_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 6; +#else + uint32_t tlv_reserved : 6, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_mac_usr_64_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, +#endif + tlv_reserved : 32; +}; + +struct tlv_mac_64_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 38; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, + tlv_reserved : 32; +#endif +}; + +struct tlv_mac_usr_44_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_reserved : 10, + pad_44to64_bit : 22; +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + pad_44to64_bit : 22, + tlv_reserved : 10; +#endif +}; + +struct tlv_mac_44_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 16, + pad_44to64_bit : 22; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + pad_44to64_bit : 22, + tlv_reserved : 10; +#endif +}; + +struct tlv_mac_usr_76_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, +#endif + tlv_reserved : 32; + uint64_t pad_64to128_bit : 64; +}; + +struct tlv_mac_76_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 38; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + tlv_reserved : 32; +#endif + uint64_t pad_64to128_bit : 64; +}; + +struct tlv_usr_c_44_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata : _TLV_CDATA_WIDTH_, + pad_44to64_bit : 20; +#else + uint64_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1, + pad_44to64_bit : 20, + tlv_cdata_upper_12 : 12; +#endif +}; + +struct tlv_usr_c_76_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata_lower_52 : 52; + uint64_t tlv_cdata_upper_12 : 12, + pad_76to128_bit : 52; +#else + uint64_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1, + tlv_cdata_middle_32 : 32; + uint64_t pad_76to96_bit : 20, + tlv_cdata_upper_12 : 12, + pad_96to128_bit : 32; +#endif +}; + +struct tlv_usr_32_hdr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, +#endif + tlv_reserved : 32; +}; + +struct tlv_32_hdr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 38; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, + tlv_reserved : 32; +#endif +}; + +struct tlv_mlo_usr_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + +struct tlv_mlo_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + +struct tlv_mac_usr_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + +struct tlv_mac_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + +struct tlv_usr_c_44_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata_lower_20 : 20; + uint32_t tlv_cdata_upper_12 : 12, + pad_44to64_bit : 20; +#else + uint32_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1; + uint32_t pad_44to64_bit : 20, + tlv_cdata_upper_12 : 12; +#endif +}; + +struct tlv_usr_c_76_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata_lower_20 : 20; + uint32_t tlv_cdata_middle_32 : 32; + uint32_t tlv_cdata_upper_12 : 12, + pad_76to96_bit : 20; + uint32_t pad_96to128_bit : 32; +#else + uint32_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1; + uint32_t tlv_cdata_middle_32 : 32; + uint32_t pad_76to96_bit : 20, + tlv_cdata_upper_12 : 12; + uint32_t pad_96to128_bit : 32; +#endif +}; + +#endif diff --git a/hw/kiwi/v2/tlv_tag_def.h b/hw/kiwi/v2/tlv_tag_def.h new file mode 100644 index 000000000000..c8fd3753a71c --- /dev/null +++ b/hw/kiwi/v2/tlv_tag_def.h @@ -0,0 +1,501 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TLV_TAG_DEF_ +#define _TLV_TAG_DEF_ + +typedef enum tlv_tag_def{ + WIFIMACTX_CBF_START_E = 0 , + WIFIPHYRX_DATA_E = 1 , + WIFIPHYRX_CBF_DATA_RESP_E = 2 , + WIFIPHYRX_ABORT_REQUEST_E = 3 , + WIFIPHYRX_USER_ABORT_NOTIFICATION_E = 4 , + WIFIMACTX_DATA_RESP_E = 5 , + WIFIMACTX_CBF_DATA_E = 6 , + WIFIMACTX_CBF_DONE_E = 7 , + WIFIPHYRX_LMR_DATA_RESP_E = 8 , + WIFIRXPCU_TO_UCODE_START_E = 9 , + WIFIRXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E = 10 , + WIFIRXPCU_TO_UCODE_FULL_MPDU_DATA_E = 11 , + WIFIRXPCU_TO_UCODE_FCS_STATUS_E = 12 , + WIFIRXPCU_TO_UCODE_MPDU_DELIMITER_E = 13 , + WIFIRXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E = 14 , + WIFIRXPCU_TO_UCODE_MPDU_HEADER_DATA_E = 15 , + WIFIRXPCU_TO_UCODE_END_E = 16 , + WIFIMACRX_CBF_READ_REQUEST_E = 32 , + WIFIMACRX_CBF_DATA_REQUEST_E = 33 , + WIFIMACRX_EXPECT_NDP_RECEPTION_E = 34 , + WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E = 35 , + WIFIMACRX_NDP_TIMEOUT_E = 36 , + WIFIMACRX_ABORT_ACK_E = 37 , + WIFIMACRX_REQ_IMPLICIT_FB_E = 38 , + WIFIMACRX_CHAIN_MASK_E = 39 , + WIFIMACRX_NAP_USER_E = 40 , + WIFIMACRX_ABORT_REQUEST_E = 41 , + WIFIPHYTX_OTHER_TRANSMIT_INFO16_E = 42 , + WIFIPHYTX_ABORT_ACK_E = 43 , + WIFIPHYTX_ABORT_REQUEST_E = 44 , + WIFIPHYTX_PKT_END_E = 45 , + WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E = 46 , + WIFIPHYTX_REQUEST_CTRL_INFO_E = 47 , + WIFIPHYTX_DATA_REQUEST_E = 48 , + WIFIPHYTX_BF_CV_LOADING_DONE_E = 49 , + WIFIPHYTX_NAP_ACK_E = 50 , + WIFIPHYTX_NAP_DONE_E = 51 , + WIFIPHYTX_OFF_ACK_E = 52 , + WIFIPHYTX_ON_ACK_E = 53 , + WIFIPHYTX_SYNTH_OFF_ACK_E = 54 , + WIFIPHYTX_DEBUG16_E = 55 , + WIFIMACTX_ABORT_REQUEST_E = 56 , + WIFIMACTX_ABORT_ACK_E = 57 , + WIFIMACTX_PKT_END_E = 58 , + WIFIMACTX_PRE_PHY_DESC_E = 59 , + WIFIMACTX_BF_PARAMS_COMMON_E = 60 , + WIFIMACTX_BF_PARAMS_PER_USER_E = 61 , + WIFIMACTX_PREFETCH_CV_E = 62 , + WIFIMACTX_USER_DESC_COMMON_E = 63 , + WIFIMACTX_USER_DESC_PER_USER_E = 64 , + WIFIEXAMPLE_USER_TLV_16_E = 65 , + WIFIEXAMPLE_TLV_16_E = 66 , + WIFIMACTX_PHY_OFF_E = 67 , + WIFIMACTX_PHY_ON_E = 68 , + WIFIMACTX_SYNTH_OFF_E = 69 , + WIFIMACTX_EXPECT_CBF_COMMON_E = 70 , + WIFIMACTX_EXPECT_CBF_PER_USER_E = 71 , + WIFIMACTX_PHY_DESC_E = 72 , + WIFIMACTX_L_SIG_A_E = 73 , + WIFIMACTX_L_SIG_B_E = 74 , + WIFIMACTX_HT_SIG_E = 75 , + WIFIMACTX_VHT_SIG_A_E = 76 , + WIFIMACTX_VHT_SIG_B_SU20_E = 77 , + WIFIMACTX_VHT_SIG_B_SU40_E = 78 , + WIFIMACTX_VHT_SIG_B_SU80_E = 79 , + WIFIMACTX_VHT_SIG_B_SU160_E = 80 , + WIFIMACTX_VHT_SIG_B_MU20_E = 81 , + WIFIMACTX_VHT_SIG_B_MU40_E = 82 , + WIFIMACTX_VHT_SIG_B_MU80_E = 83 , + WIFIMACTX_VHT_SIG_B_MU160_E = 84 , + WIFIMACTX_SERVICE_E = 85 , + WIFIMACTX_HE_SIG_A_SU_E = 86 , + WIFIMACTX_HE_SIG_A_MU_DL_E = 87 , + WIFIMACTX_HE_SIG_A_MU_UL_E = 88 , + WIFIMACTX_HE_SIG_B1_MU_E = 89 , + WIFIMACTX_HE_SIG_B2_MU_E = 90 , + WIFIMACTX_HE_SIG_B2_OFDMA_E = 91 , + WIFIMACTX_DELETE_CV_E = 92 , + WIFIMACTX_MU_UPLINK_COMMON_E = 93 , + WIFIMACTX_MU_UPLINK_USER_SETUP_E = 94 , + WIFIMACTX_OTHER_TRANSMIT_INFO_E = 95 , + WIFIMACTX_PHY_NAP_E = 96 , + WIFIMACTX_DEBUG_E = 97 , + WIFIPHYRX_ABORT_ACK_E = 98 , + WIFIPHYRX_GENERATED_CBF_DETAILS_E = 99 , + WIFIPHYRX_RSSI_LEGACY_E = 100 , + WIFIPHYRX_RSSI_HT_E = 101 , + WIFIPHYRX_USER_INFO_E = 102 , + WIFIPHYRX_PKT_END_E = 103 , + WIFIPHYRX_DEBUG_E = 104 , + WIFIPHYRX_CBF_TRANSFER_DONE_E = 105 , + WIFIPHYRX_CBF_TRANSFER_ABORT_E = 106 , + WIFIPHYRX_L_SIG_A_E = 107 , + WIFIPHYRX_L_SIG_B_E = 108 , + WIFIPHYRX_HT_SIG_E = 109 , + WIFIPHYRX_VHT_SIG_A_E = 110 , + WIFIPHYRX_VHT_SIG_B_SU20_E = 111 , + WIFIPHYRX_VHT_SIG_B_SU40_E = 112 , + WIFIPHYRX_VHT_SIG_B_SU80_E = 113 , + WIFIPHYRX_VHT_SIG_B_SU160_E = 114 , + WIFIPHYRX_VHT_SIG_B_MU20_E = 115 , + WIFIPHYRX_VHT_SIG_B_MU40_E = 116 , + WIFIPHYRX_VHT_SIG_B_MU80_E = 117 , + WIFIPHYRX_VHT_SIG_B_MU160_E = 118 , + WIFIPHYRX_HE_SIG_A_SU_E = 119 , + WIFIPHYRX_HE_SIG_A_MU_DL_E = 120 , + WIFIPHYRX_HE_SIG_A_MU_UL_E = 121 , + WIFIPHYRX_HE_SIG_B1_MU_E = 122 , + WIFIPHYRX_HE_SIG_B2_MU_E = 123 , + WIFIPHYRX_HE_SIG_B2_OFDMA_E = 124 , + WIFIPHYRX_OTHER_RECEIVE_INFO_E = 125 , + WIFIPHYRX_COMMON_USER_INFO_E = 126 , + WIFIPHYRX_DATA_DONE_E = 127 , + WIFICOEX_TX_REQ_E = 128 , + WIFIDUMMY_E = 129 , + WIFIEXAMPLE_TLV_32_NAME_E = 130 , + WIFIMPDU_LIMIT_E = 131 , + WIFINA_LENGTH_END_E = 132 , + WIFIOLE_BUF_STATUS_E = 133 , + WIFIPCU_PPDU_SETUP_DONE_E = 134 , + WIFIPCU_PPDU_SETUP_END_E = 135 , + WIFIPCU_PPDU_SETUP_INIT_E = 136 , + WIFIPCU_PPDU_SETUP_START_E = 137 , + WIFIPDG_FES_SETUP_E = 138 , + WIFIPDG_RESPONSE_E = 139 , + WIFIPDG_TX_REQ_E = 140 , + WIFISCH_WAIT_INSTR_E = 141 , + WIFITQM_FLOW_EMPTY_STATUS_E = 143 , + WIFITQM_FLOW_NOT_EMPTY_STATUS_E = 144 , + WIFITQM_GEN_MPDU_LENGTH_LIST_E = 145 , + WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 146 , + WIFITQM_GEN_MPDUS_E = 147 , + WIFITQM_GEN_MPDUS_STATUS_E = 148 , + WIFITQM_REMOVE_MPDU_E = 149 , + WIFITQM_REMOVE_MPDU_STATUS_E = 150 , + WIFITQM_REMOVE_MSDU_E = 151 , + WIFITQM_REMOVE_MSDU_STATUS_E = 152 , + WIFITQM_UPDATE_TX_MPDU_COUNT_E = 153 , + WIFITQM_WRITE_CMD_E = 154 , + WIFIOFDMA_TRIGGER_DETAILS_E = 155 , + WIFITX_DATA_E = 156 , + WIFITX_FES_SETUP_E = 157 , + WIFIRX_PACKET_E = 158 , + WIFIEXPECTED_RESPONSE_E = 159 , + WIFITX_MPDU_END_E = 160 , + WIFITX_MPDU_START_E = 161 , + WIFITX_MSDU_END_E = 162 , + WIFITX_MSDU_START_E = 163 , + WIFITX_SW_MODE_SETUP_E = 164 , + WIFITXPCU_BUFFER_STATUS_E = 165 , + WIFITXPCU_USER_BUFFER_STATUS_E = 166 , + WIFIDATA_TO_TIME_CONFIG_E = 167 , + WIFIEXAMPLE_USER_TLV_32_E = 168 , + WIFIMPDU_INFO_E = 169 , + WIFIPDG_USER_SETUP_E = 170 , + WIFITX_11AH_SETUP_E = 171 , + WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E = 172 , + WIFITX_PEER_ENTRY_E = 173 , + WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E = 174 , + WIFIEXAMPLE_USER_TLV_44_E = 175 , + WIFITX_FLUSH_E = 176 , + WIFITX_FLUSH_REQ_E = 177 , + WIFITQM_WRITE_CMD_STATUS_E = 178 , + WIFITQM_GET_MPDU_QUEUE_STATS_E = 179 , + WIFITQM_GET_MSDU_FLOW_STATS_E = 180 , + WIFIEXAMPLE_USER_CTLV_44_E = 181 , + WIFITX_FES_STATUS_START_E = 182 , + WIFITX_FES_STATUS_USER_PPDU_E = 183 , + WIFITX_FES_STATUS_USER_RESPONSE_E = 184 , + WIFITX_FES_STATUS_END_E = 185 , + WIFIRX_TRIG_INFO_E = 186 , + WIFIRXPCU_TX_SETUP_CLEAR_E = 187 , + WIFIRX_FRAME_BITMAP_REQ_E = 188 , + WIFIRX_FRAME_BITMAP_ACK_E = 189 , + WIFICOEX_RX_STATUS_E = 190 , + WIFIRX_START_PARAM_E = 191 , + WIFIRX_PPDU_START_E = 192 , + WIFIRX_PPDU_END_E = 193 , + WIFIRX_MPDU_START_E = 194 , + WIFIRX_MPDU_END_E = 195 , + WIFIRX_MSDU_START_E = 196 , + WIFIRX_MSDU_END_E = 197 , + WIFIRX_ATTENTION_E = 198 , + WIFIRECEIVED_RESPONSE_INFO_E = 199 , + WIFIRX_PHY_SLEEP_E = 200 , + WIFIRX_HEADER_E = 201 , + WIFIRX_PEER_ENTRY_E = 202 , + WIFIRX_FLUSH_E = 203 , + WIFIRX_RESPONSE_REQUIRED_INFO_E = 204 , + WIFIRX_FRAMELESS_BAR_DETAILS_E = 205 , + WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E = 206 , + WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E = 207 , + WIFITX_CBF_INFO_E = 208 , + WIFIPCU_PPDU_SETUP_USER_E = 209 , + WIFIRX_MPDU_PCU_START_E = 210 , + WIFIRX_PM_INFO_E = 211 , + WIFIRX_USER_PPDU_END_E = 212 , + WIFIRX_PRE_PPDU_START_E = 213 , + WIFIRX_PREAMBLE_E = 214 , + WIFITX_FES_SETUP_COMPLETE_E = 215 , + WIFITX_LAST_MPDU_FETCHED_E = 216 , + WIFITXDMA_STOP_REQUEST_E = 217 , + WIFIRXPCU_SETUP_E = 218 , + WIFIRXPCU_USER_SETUP_E = 219 , + WIFITX_FES_STATUS_ACK_OR_BA_E = 220 , + WIFITQM_ACKED_MPDU_E = 221 , + WIFICOEX_TX_RESP_E = 222 , + WIFICOEX_TX_STATUS_E = 223 , + WIFIMACTX_COEX_PHY_CTRL_E = 224 , + WIFICOEX_STATUS_BROADCAST_E = 225 , + WIFIRESPONSE_START_STATUS_E = 226 , + WIFIRESPONSE_END_STATUS_E = 227 , + WIFICRYPTO_STATUS_E = 228 , + WIFIRECEIVED_TRIGGER_INFO_E = 229 , + WIFICOEX_TX_STOP_CTRL_E = 230 , + WIFIRX_PPDU_ACK_REPORT_E = 231 , + WIFIRX_PPDU_NO_ACK_REPORT_E = 232 , + WIFISCH_COEX_STATUS_E = 233 , + WIFISCHEDULER_COMMAND_STATUS_E = 234 , + WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 235 , + WIFITX_FES_STATUS_PROT_E = 236 , + WIFITX_FES_STATUS_START_PPDU_E = 237 , + WIFITX_FES_STATUS_START_PROT_E = 238 , + WIFITXPCU_PHYTX_DEBUG32_E = 239 , + WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 240 , + WIFITX_MPDU_COUNT_TRANSFER_END_E = 241 , + WIFIWHO_ANCHOR_OFFSET_E = 242 , + WIFIWHO_ANCHOR_VALUE_E = 243 , + WIFIWHO_CCE_INFO_E = 244 , + WIFIWHO_COMMIT_E = 245 , + WIFIWHO_COMMIT_DONE_E = 246 , + WIFIWHO_FLUSH_E = 247 , + WIFIWHO_L2_LLC_E = 248 , + WIFIWHO_L2_PAYLOAD_E = 249 , + WIFIWHO_L3_CHECKSUM_E = 250 , + WIFIWHO_L3_INFO_E = 251 , + WIFIWHO_L4_CHECKSUM_E = 252 , + WIFIWHO_L4_INFO_E = 253 , + WIFIWHO_MSDU_E = 254 , + WIFIWHO_MSDU_MISC_E = 255 , + WIFIWHO_PACKET_DATA_E = 256 , + WIFIWHO_PACKET_HDR_E = 257 , + WIFIWHO_PPDU_END_E = 258 , + WIFIWHO_PPDU_START_E = 259 , + WIFIWHO_TSO_E = 260 , + WIFIWHO_WMAC_HEADER_PV0_E = 261 , + WIFIWHO_WMAC_HEADER_PV1_E = 262 , + WIFIWHO_WMAC_IV_E = 263 , + WIFIMPDU_INFO_END_E = 264 , + WIFIMPDU_INFO_BITMAP_E = 265 , + WIFITX_QUEUE_EXTENSION_E = 266 , + WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E = 267 , + WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 268 , + WIFITQM_ACKED_MPDU_STATUS_E = 269 , + WIFITQM_ADD_MSDU_STATUS_E = 270 , + WIFITQM_LIST_GEN_DONE_E = 271 , + WIFIWHO_TERMINATE_E = 272 , + WIFITX_LAST_MPDU_END_E = 273 , + WIFITX_CV_DATA_E = 274 , + WIFIPPDU_TX_END_E = 275 , + WIFIPROT_TX_END_E = 276 , + WIFIMPDU_INFO_GLOBAL_END_E = 277 , + WIFITQM_SCH_INSTR_GLOBAL_END_E = 278 , + WIFIRX_PPDU_END_USER_STATS_E = 279 , + WIFIRX_PPDU_END_USER_STATS_EXT_E = 280 , + WIFIREO_GET_QUEUE_STATS_E = 281 , + WIFIREO_FLUSH_QUEUE_E = 282 , + WIFIREO_FLUSH_CACHE_E = 283 , + WIFIREO_UNBLOCK_CACHE_E = 284 , + WIFIREO_GET_QUEUE_STATS_STATUS_E = 285 , + WIFIREO_FLUSH_QUEUE_STATUS_E = 286 , + WIFIREO_FLUSH_CACHE_STATUS_E = 287 , + WIFIREO_UNBLOCK_CACHE_STATUS_E = 288 , + WIFITQM_FLUSH_CACHE_E = 289 , + WIFITQM_UNBLOCK_CACHE_E = 290 , + WIFITQM_FLUSH_CACHE_STATUS_E = 291 , + WIFITQM_UNBLOCK_CACHE_STATUS_E = 292 , + WIFIRX_PPDU_END_STATUS_DONE_E = 293 , + WIFIRX_STATUS_BUFFER_DONE_E = 294 , + WIFITX_DATA_SYNC_E = 297 , + WIFIPHYRX_CBF_READ_REQUEST_ACK_E = 298 , + WIFITQM_GET_MPDU_HEAD_INFO_E = 299 , + WIFITQM_SYNC_CMD_E = 300 , + WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E = 301 , + WIFITQM_SYNC_CMD_STATUS_E = 302 , + WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 303 , + WIFITQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 304 , + WIFIREO_FLUSH_TIMEOUT_LIST_E = 305 , + WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E = 306 , + WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 307 , + WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 308 , + WIFIEXAMPLE_USER_TLV_32_NAME_E = 309 , + WIFIRX_PPDU_START_USER_INFO_E = 310 , + WIFIRX_RING_MASK_E = 311 , + WIFICOEX_MAC_NAP_E = 312 , + WIFIRXPCU_PPDU_END_INFO_E = 313 , + WIFIWHO_MESH_CONTROL_E = 314 , + WIFIPDG_SW_MODE_BW_START_E = 315 , + WIFIPDG_SW_MODE_BW_END_E = 316 , + WIFIPDG_WAIT_FOR_MAC_REQUEST_E = 317 , + WIFIPDG_WAIT_FOR_PHY_REQUEST_E = 318 , + WIFISCHEDULER_END_E = 319 , + WIFIRX_PPDU_START_DROPPED_E = 320 , + WIFIRX_PPDU_END_DROPPED_E = 321 , + WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E = 322 , + WIFIRX_MPDU_START_DROPPED_E = 323 , + WIFIRX_MSDU_START_DROPPED_E = 324 , + WIFIRX_MSDU_END_DROPPED_E = 325 , + WIFIRX_MPDU_END_DROPPED_E = 326 , + WIFIRX_ATTENTION_DROPPED_E = 327 , + WIFITXPCU_USER_SETUP_E = 328 , + WIFIRXPCU_USER_SETUP_EXT_E = 329 , + WIFICMD_PART_0_END_E = 330 , + WIFIMACTX_SYNTH_ON_E = 331 , + WIFISCH_CRITICAL_TLV_REFERENCE_E = 332 , + WIFITQM_MPDU_GLOBAL_START_E = 333 , + WIFIEXAMPLE_TLV_32_E = 334 , + WIFITQM_UPDATE_TX_MSDU_FLOW_E = 335 , + WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 336 , + WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 337 , + WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 338 , + WIFIREO_UPDATE_RX_REO_QUEUE_E = 339 , + WIFITQM_MPDU_QUEUE_EMPTY_STATUS_E = 340 , + WIFITQM_2_SCH_MPDU_AVAILABLE_E = 341 , + WIFIPDG_TRIG_RESPONSE_E = 342 , + WIFITRIGGER_RESPONSE_TX_DONE_E = 343 , + WIFIABORT_FROM_PHYRX_DETAILS_E = 344 , + WIFISCH_TQM_CMD_WRAPPER_E = 345 , + WIFIMPDUS_AVAILABLE_E = 346 , + WIFIRECEIVED_RESPONSE_INFO_PART2_E = 347 , + WIFIPHYRX_TX_START_TIMING_E = 348 , + WIFITXPCU_PREAMBLE_DONE_E = 349 , + WIFINDP_PREAMBLE_DONE_E = 350 , + WIFISCH_TQM_CMD_WRAPPER_RBO_DROP_E = 351 , + WIFISCH_TQM_CMD_WRAPPER_CONT_DROP_E = 352 , + WIFIMACTX_CLEAR_PREV_TX_INFO_E = 353 , + WIFITX_PUNCTURE_SETUP_E = 354 , + WIFIR2R_STATUS_END_E = 355 , + WIFIMACTX_PREFETCH_CV_COMMON_E = 356 , + WIFIEND_OF_FLUSH_MARKER_E = 357 , + WIFIMACTX_MU_UPLINK_COMMON_PUNC_E = 358 , + WIFIMACTX_MU_UPLINK_USER_SETUP_PUNC_E = 359 , + WIFIRECEIVED_RESPONSE_USER_7_0_E = 360 , + WIFIRECEIVED_RESPONSE_USER_15_8_E = 361 , + WIFIRECEIVED_RESPONSE_USER_23_16_E = 362 , + WIFIRECEIVED_RESPONSE_USER_31_24_E = 363 , + WIFIRECEIVED_RESPONSE_USER_36_32_E = 364 , + WIFITX_LOOPBACK_SETUP_E = 365 , + WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 366 , + WIFISCH_WAIT_INSTR_TX_PATH_E = 367 , + WIFIMACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 368 , + WIFIMACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 369 , + WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 370 , + WIFITX_WUR_DATA_E = 371 , + WIFIRX_PPDU_END_START_E = 372 , + WIFIRX_PPDU_END_MIDDLE_E = 373 , + WIFIRX_PPDU_END_LAST_E = 374 , + WIFIMACTX_BACKOFF_BASED_TRANSMISSION_E = 375 , + WIFIMACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 376 , + WIFISRP_INFO_E = 377 , + WIFIOBSS_SR_INFO_E = 378 , + WIFISCHEDULER_SW_MSG_STATUS_E = 379 , + WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 380 , + WIFIRXPCU_SETUP_COMPLETE_E = 381 , + WIFISNOOP_PPDU_START_E = 382 , + WIFISNOOP_MPDU_USR_DBG_INFO_E = 383 , + WIFISNOOP_MSDU_USR_DBG_INFO_E = 384 , + WIFISNOOP_MSDU_USR_DATA_E = 385 , + WIFISNOOP_MPDU_USR_STAT_INFO_E = 386 , + WIFISNOOP_PPDU_END_E = 387 , + WIFISNOOP_SPARE_E = 388 , + WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 390 , + WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 391 , + WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 392 , + WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 393 , + WIFISCH_TLV_WRAPPER_E = 394 , + WIFISCHEDULER_STATUS_WRAPPER_E = 395 , + WIFIMPDU_INFO_6X_E = 396 , + WIFIMACTX___RESERVED_G_0013 = 397 , + WIFIMACTX_U_SIG_EHT_SU_MU_E = 398 , + WIFIMACTX_U_SIG_EHT_TB_E = 399 , + WIFIPHYRX_U_SIG_EHT_SU_MU_E = 403 , + WIFIPHYRX_U_SIG_EHT_TB_E = 404 , + WIFIMACRX_LMR_READ_REQUEST_E = 408 , + WIFIMACRX_LMR_DATA_REQUEST_E = 409 , + WIFIPHYRX_LMR_TRANSFER_DONE_E = 410 , + WIFIPHYRX_LMR_TRANSFER_ABORT_E = 411 , + WIFIPHYRX_LMR_READ_REQUEST_ACK_E = 412 , + WIFIMACRX_SECURE_LTF_SEQ_PTR_E = 413 , + WIFIPHYRX_USER_INFO_MU_UL_E = 414 , + WIFIMPDU_QUEUE_OVERVIEW_E = 415 , + WIFISCHEDULER_NAV_INFO_E = 416 , + WIFILMR_PEER_ENTRY_E = 418 , + WIFILMR_MPDU_START_E = 419 , + WIFILMR_DATA_E = 420 , + WIFILMR_MPDU_END_E = 421 , + WIFIREO_GET_QUEUE_1K_STATS_STATUS_E = 422 , + WIFIRX_FRAME_1K_BITMAP_ACK_E = 423 , + WIFITX_FES_STATUS_1K_BA_E = 424 , + WIFITQM_ACKED_1K_MPDU_E = 425 , + WIFIMACRX_INBSS_OBSS_IND_E = 426 , + WIFIPHYRX_LOCATION_E = 427 , + WIFIMLO_TX_NOTIFICATION_SU_E = 428 , + WIFIMLO_TX_NOTIFICATION_MU_E = 429 , + WIFIMLO_TX_REQ_SU_E = 430 , + WIFIMLO_TX_REQ_MU_E = 431 , + WIFIMLO_TX_RESP_E = 432 , + WIFIMLO_RX_NOTIFICATION_E = 433 , + WIFIMLO_BKOFF_TRUNC_REQ_E = 434 , + WIFIMLO_TBTT_NOTIFICATION_E = 435 , + WIFIMLO_MESSAGE_E = 436 , + WIFIMLO_TS_SYNC_MSG_E = 437 , + WIFIMLO_FES_SETUP_E = 438 , + WIFIMLO_PDG_FES_SETUP_SU_E = 439 , + WIFIMLO_PDG_FES_SETUP_MU_E = 440 , + WIFIMPDU_INFO_1K_BITMAP_E = 441 , + WIFIMON_BUFFER_ADDR_E = 442 , + WIFITX_FRAG_STATE_E = 443 , + WIFIMACTX_EHT_SIG_USR_OFDMA_E = 446 , + WIFIPHYRX_EHT_SIG_CMN_PUNC_E = 448 , + WIFIPHYRX_EHT_SIG_CMN_OFDMA_E = 450 , + WIFIPHYRX_EHT_SIG_USR_OFDMA_E = 454 , + WIFIPHYRX_PKT_END_PART1_E = 456 , + WIFIMACTX_EXPECT_NDP_RECEPTION_E = 457 , + WIFIMACTX_SECURE_LTF_SEQ_PTR_E = 458 , + WIFIMLO_PDG_BKOFF_TRUNC_NOTIFY_E = 460 , + WIFIPHYRX___RESERVED_G_0014 = 461 , + WIFIPHYTX_LOCATION_E = 462 , + WIFIPHYTX___RESERVED_G_0014 = 463 , + WIFIMACTX_EHT_SIG_USR_SU_E = 466 , + WIFIMACTX_EHT_SIG_USR_MU_MIMO_E = 467 , + WIFIPHYRX_EHT_SIG_USR_SU_E = 468 , + WIFIPHYRX_EHT_SIG_USR_MU_MIMO_E = 469 , + WIFIPHYRX_GENERIC_U_SIG_E = 470 , + WIFIPHYRX_GENERIC_EHT_SIG_E = 471 , + WIFIOVERWRITE_RESP_START_E = 472 , + WIFIOVERWRITE_RESP_PREAMBLE_INFO_E = 473 , + WIFIOVERWRITE_RESP_FRAME_INFO_E = 474 , + WIFIOVERWRITE_RESP_END_E = 475 , + WIFIRXPCU_EARLY_RX_INDICATION_E = 476 , + WIFIMON_DROP_E = 477 , + WIFIMACRX_MU_UPLINK_COMMON_SNIFF_E = 478 , + WIFIMACRX_MU_UPLINK_USER_SETUP_SNIFF_E = 479 , + WIFIMACRX_MU_UPLINK_USER_SEL_SNIFF_E = 480 , + WIFIMACRX_MU_UPLINK_FCS_STATUS_SNIFF_E = 481 , + WIFIMACTX_PREFETCH_CV_DMA_E = 482 , + WIFIMACTX_PREFETCH_CV_PER_USER_E = 483 , + WIFIPHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E = 484 , + WIFIMACTX_BF_PARAMS_UPDATE_COMMON_E = 485 , + WIFIMACTX_BF_PARAMS_UPDATE_PER_USER_E = 486 , + WIFIRANGING_USER_DETAILS_E = 487 , + WIFIPHYTX_CV_CORR_STATUS_E = 488 , + WIFIPHYTX_CV_CORR_COMMON_E = 489 , + WIFIPHYTX_CV_CORR_USER_E = 490 , + WIFIMACTX_CV_CORR_COMMON_E = 491 , + WIFIMACTX_CV_CORR_MAC_INFO_GROUP_E = 492 , + WIFIBW_PUNCTURE_EVAL_WRAPPER_E = 493 , + WIFIMACTX_RX_NOTIFICATION_FOR_PHY_E = 494 , + WIFIMACTX_TX_NOTIFICATION_FOR_PHY_E = 495 , + WIFIMACTX_MU_UPLINK_COMMON_PER_BW_E = 496 , + WIFIMACTX_MU_UPLINK_USER_SETUP_PER_BW_E = 497 , + WIFIRX_PPDU_END_USER_STATS_EXT2_E = 498 , + WIFIFW2SW_MON_E = 499 , + WIFIWSI_DIRECT_MESSAGE_E = 500 , + WIFIMACTX_EMLSR_PRE_SWITCH_E = 501 , + WIFIMACTX_EMLSR_SWITCH_E = 502 , + WIFIMACTX_EMLSR_SWITCH_BACK_E = 503 , + WIFIPHYTX_EMLSR_SWITCH_ACK_E = 504 , + WIFIPHYTX_EMLSR_SWITCH_BACK_ACK_E = 505 , + WIFISPARE_REUSE_TAG_0_E = 506 , + WIFISPARE_REUSE_TAG_1_E = 507 , + WIFISPARE_REUSE_TAG_2_E = 508 , + WIFISPARE_REUSE_TAG_3_E = 509 +} tlv_tag_def__e; + +#endif diff --git a/hw/kiwi/v2/tx_msdu_extension.h b/hw/kiwi/v2/tx_msdu_extension.h new file mode 100644 index 000000000000..53dfa98bc527 --- /dev/null +++ b/hw/kiwi/v2/tx_msdu_extension.h @@ -0,0 +1,378 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_MSDU_EXTENSION_H_ +#define _TX_MSDU_EXTENSION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 + +struct tx_msdu_extension { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tso_enable : 1, + reserved_0a : 6, + tcp_flag : 9, + tcp_flag_mask : 9, + reserved_0b : 7; + uint32_t l2_length : 16, + ip_length : 16; + uint32_t tcp_seq_number : 32; + uint32_t ip_identification : 16, + udp_length : 16; + uint32_t checksum_offset : 14, + partial_checksum_en : 1, + reserved_4a : 1, + payload_start_offset : 14, + reserved_4b : 2; + uint32_t payload_end_offset : 14, + reserved_5a : 2, + wds : 1, + reserved_5b : 15; + uint32_t buf0_ptr_31_0 : 32; + uint32_t buf0_ptr_39_32 : 8, + extn_override : 1, + encap_type : 2, + encrypt_type : 4, + tqm_no_drop : 1, + buf0_len : 16; + uint32_t buf1_ptr_31_0 : 32; + uint32_t buf1_ptr_39_32 : 8, + epd : 1, + mesh_enable : 2, + reserved_9a : 5, + buf1_len : 16; + uint32_t buf2_ptr_31_0 : 32; + uint32_t buf2_ptr_39_32 : 8, + dscp_tid_table_num : 6, + reserved_11a : 2, + buf2_len : 16; + uint32_t buf3_ptr_31_0 : 32; + uint32_t buf3_ptr_39_32 : 8, + reserved_13a : 8, + buf3_len : 16; + uint32_t buf4_ptr_31_0 : 32; + uint32_t buf4_ptr_39_32 : 8, + reserved_15a : 8, + buf4_len : 16; + uint32_t buf5_ptr_31_0 : 32; + uint32_t buf5_ptr_39_32 : 8, + reserved_17a : 8, + buf5_len : 16; +#else + uint32_t reserved_0b : 7, + tcp_flag_mask : 9, + tcp_flag : 9, + reserved_0a : 6, + tso_enable : 1; + uint32_t ip_length : 16, + l2_length : 16; + uint32_t tcp_seq_number : 32; + uint32_t udp_length : 16, + ip_identification : 16; + uint32_t reserved_4b : 2, + payload_start_offset : 14, + reserved_4a : 1, + partial_checksum_en : 1, + checksum_offset : 14; + uint32_t reserved_5b : 15, + wds : 1, + reserved_5a : 2, + payload_end_offset : 14; + uint32_t buf0_ptr_31_0 : 32; + uint32_t buf0_len : 16, + tqm_no_drop : 1, + encrypt_type : 4, + encap_type : 2, + extn_override : 1, + buf0_ptr_39_32 : 8; + uint32_t buf1_ptr_31_0 : 32; + uint32_t buf1_len : 16, + reserved_9a : 5, + mesh_enable : 2, + epd : 1, + buf1_ptr_39_32 : 8; + uint32_t buf2_ptr_31_0 : 32; + uint32_t buf2_len : 16, + reserved_11a : 2, + dscp_tid_table_num : 6, + buf2_ptr_39_32 : 8; + uint32_t buf3_ptr_31_0 : 32; + uint32_t buf3_len : 16, + reserved_13a : 8, + buf3_ptr_39_32 : 8; + uint32_t buf4_ptr_31_0 : 32; + uint32_t buf4_len : 16, + reserved_15a : 8, + buf4_ptr_39_32 : 8; + uint32_t buf5_ptr_31_0 : 32; + uint32_t buf5_len : 16, + reserved_17a : 8, + buf5_ptr_39_32 : 8; +#endif +}; + +#define TX_MSDU_EXTENSION_TSO_ENABLE_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_TSO_ENABLE_LSB 0 +#define TX_MSDU_EXTENSION_TSO_ENABLE_MSB 0 +#define TX_MSDU_EXTENSION_TSO_ENABLE_MASK 0x00000001 + +#define TX_MSDU_EXTENSION_RESERVED_0A_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_RESERVED_0A_LSB 1 +#define TX_MSDU_EXTENSION_RESERVED_0A_MSB 6 +#define TX_MSDU_EXTENSION_RESERVED_0A_MASK 0x0000007e + +#define TX_MSDU_EXTENSION_TCP_FLAG_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_TCP_FLAG_LSB 7 +#define TX_MSDU_EXTENSION_TCP_FLAG_MSB 15 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK 0x0000ff80 + +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_LSB 16 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MSB 24 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MASK 0x01ff0000 + +#define TX_MSDU_EXTENSION_RESERVED_0B_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_RESERVED_0B_LSB 25 +#define TX_MSDU_EXTENSION_RESERVED_0B_MSB 31 +#define TX_MSDU_EXTENSION_RESERVED_0B_MASK 0xfe000000 + +#define TX_MSDU_EXTENSION_L2_LENGTH_OFFSET 0x00000004 +#define TX_MSDU_EXTENSION_L2_LENGTH_LSB 0 +#define TX_MSDU_EXTENSION_L2_LENGTH_MSB 15 +#define TX_MSDU_EXTENSION_L2_LENGTH_MASK 0x0000ffff + +#define TX_MSDU_EXTENSION_IP_LENGTH_OFFSET 0x00000004 +#define TX_MSDU_EXTENSION_IP_LENGTH_LSB 16 +#define TX_MSDU_EXTENSION_IP_LENGTH_MSB 31 +#define TX_MSDU_EXTENSION_IP_LENGTH_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_OFFSET 0x00000008 +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_LSB 0 +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MSB 31 +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_OFFSET 0x0000000c +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_LSB 0 +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MSB 15 +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MASK 0x0000ffff + +#define TX_MSDU_EXTENSION_UDP_LENGTH_OFFSET 0x0000000c +#define TX_MSDU_EXTENSION_UDP_LENGTH_LSB 16 +#define TX_MSDU_EXTENSION_UDP_LENGTH_MSB 31 +#define TX_MSDU_EXTENSION_UDP_LENGTH_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_LSB 0 +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MSB 13 +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MASK 0x00003fff + +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_LSB 14 +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MSB 14 +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MASK 0x00004000 + +#define TX_MSDU_EXTENSION_RESERVED_4A_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_RESERVED_4A_LSB 15 +#define TX_MSDU_EXTENSION_RESERVED_4A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_4A_MASK 0x00008000 + +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_LSB 16 +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MSB 29 +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MASK 0x3fff0000 + +#define TX_MSDU_EXTENSION_RESERVED_4B_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_RESERVED_4B_LSB 30 +#define TX_MSDU_EXTENSION_RESERVED_4B_MSB 31 +#define TX_MSDU_EXTENSION_RESERVED_4B_MASK 0xc0000000 + +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_LSB 0 +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MSB 13 +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MASK 0x00003fff + +#define TX_MSDU_EXTENSION_RESERVED_5A_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_RESERVED_5A_LSB 14 +#define TX_MSDU_EXTENSION_RESERVED_5A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_5A_MASK 0x0000c000 + +#define TX_MSDU_EXTENSION_WDS_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_WDS_LSB 16 +#define TX_MSDU_EXTENSION_WDS_MSB 16 +#define TX_MSDU_EXTENSION_WDS_MASK 0x00010000 + +#define TX_MSDU_EXTENSION_RESERVED_5B_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_RESERVED_5B_LSB 17 +#define TX_MSDU_EXTENSION_RESERVED_5B_MSB 31 +#define TX_MSDU_EXTENSION_RESERVED_5B_MASK 0xfffe0000 + +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_OFFSET 0x00000018 +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_LSB 8 +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MSB 8 +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MASK 0x00000100 + +#define TX_MSDU_EXTENSION_ENCAP_TYPE_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_ENCAP_TYPE_LSB 9 +#define TX_MSDU_EXTENSION_ENCAP_TYPE_MSB 10 +#define TX_MSDU_EXTENSION_ENCAP_TYPE_MASK 0x00000600 + +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_LSB 11 +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MSB 14 +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MASK 0x00007800 + +#define TX_MSDU_EXTENSION_TQM_NO_DROP_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_TQM_NO_DROP_LSB 15 +#define TX_MSDU_EXTENSION_TQM_NO_DROP_MSB 15 +#define TX_MSDU_EXTENSION_TQM_NO_DROP_MASK 0x00008000 + +#define TX_MSDU_EXTENSION_BUF0_LEN_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_BUF0_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF0_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF0_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_OFFSET 0x00000020 +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_EPD_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_EPD_LSB 8 +#define TX_MSDU_EXTENSION_EPD_MSB 8 +#define TX_MSDU_EXTENSION_EPD_MASK 0x00000100 + +#define TX_MSDU_EXTENSION_MESH_ENABLE_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_MESH_ENABLE_LSB 9 +#define TX_MSDU_EXTENSION_MESH_ENABLE_MSB 10 +#define TX_MSDU_EXTENSION_MESH_ENABLE_MASK 0x00000600 + +#define TX_MSDU_EXTENSION_RESERVED_9A_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_RESERVED_9A_LSB 11 +#define TX_MSDU_EXTENSION_RESERVED_9A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_9A_MASK 0x0000f800 + +#define TX_MSDU_EXTENSION_BUF1_LEN_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_BUF1_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF1_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF1_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_OFFSET 0x00000028 +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_LSB 8 +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_MSB 13 +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_MASK 0x00003f00 + +#define TX_MSDU_EXTENSION_RESERVED_11A_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_RESERVED_11A_LSB 14 +#define TX_MSDU_EXTENSION_RESERVED_11A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_11A_MASK 0x0000c000 + +#define TX_MSDU_EXTENSION_BUF2_LEN_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_BUF2_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF2_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF2_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_OFFSET 0x00000030 +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_RESERVED_13A_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_RESERVED_13A_LSB 8 +#define TX_MSDU_EXTENSION_RESERVED_13A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_13A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_BUF3_LEN_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_BUF3_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF3_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF3_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_OFFSET 0x00000038 +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_RESERVED_15A_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_RESERVED_15A_LSB 8 +#define TX_MSDU_EXTENSION_RESERVED_15A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_15A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_BUF4_LEN_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_BUF4_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF4_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF4_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_OFFSET 0x00000040 +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_RESERVED_17A_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_RESERVED_17A_LSB 8 +#define TX_MSDU_EXTENSION_RESERVED_17A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_17A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_BUF5_LEN_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_BUF5_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF5_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF5_LEN_MASK 0xffff0000 + +#endif diff --git a/hw/kiwi/v2/tx_rate_stats_info.h b/hw/kiwi/v2/tx_rate_stats_info.h new file mode 100644 index 000000000000..1d9de4459f9b --- /dev/null +++ b/hw/kiwi/v2/tx_rate_stats_info.h @@ -0,0 +1,112 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_RATE_STATS_INFO_H_ +#define _TX_RATE_STATS_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2 + +struct tx_rate_stats_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_rate_stats_info_valid : 1, + transmit_bw : 3, + transmit_pkt_type : 4, + transmit_stbc : 1, + transmit_ldpc : 1, + transmit_sgi : 2, + transmit_mcs : 4, + ofdma_transmission : 1, + tones_in_ru : 12, + reserved_0a : 3; + uint32_t ppdu_transmission_tsf : 32; +#else + uint32_t reserved_0a : 3, + tones_in_ru : 12, + ofdma_transmission : 1, + transmit_mcs : 4, + transmit_sgi : 2, + transmit_ldpc : 1, + transmit_stbc : 1, + transmit_pkt_type : 4, + transmit_bw : 3, + tx_rate_stats_info_valid : 1; + uint32_t ppdu_transmission_tsf : 32; +#endif +}; + +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_LSB 0 +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MSB 0 +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + +#define TX_RATE_STATS_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_BW_LSB 1 +#define TX_RATE_STATS_INFO_TRANSMIT_BW_MSB 3 +#define TX_RATE_STATS_INFO_TRANSMIT_BW_MASK 0x0000000e + +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_LSB 4 +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MSB 7 +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MASK 0x000000f0 + +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_LSB 8 +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MSB 8 +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MASK 0x00000100 + +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_LSB 9 +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MSB 9 +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MASK 0x00000200 + +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_LSB 10 +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MSB 11 +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MASK 0x00000c00 + +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_LSB 12 +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MSB 15 +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MASK 0x0000f000 + +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_LSB 16 +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MSB 16 +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MASK 0x00010000 + +#define TX_RATE_STATS_INFO_TONES_IN_RU_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TONES_IN_RU_LSB 17 +#define TX_RATE_STATS_INFO_TONES_IN_RU_MSB 28 +#define TX_RATE_STATS_INFO_TONES_IN_RU_MASK 0x1ffe0000 + +#define TX_RATE_STATS_INFO_RESERVED_0A_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_RESERVED_0A_LSB 29 +#define TX_RATE_STATS_INFO_RESERVED_0A_MSB 31 +#define TX_RATE_STATS_INFO_RESERVED_0A_MASK 0xe0000000 + +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_OFFSET 0x00000004 +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_LSB 0 +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MSB 31 +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + +#endif diff --git a/hw/kiwi/v2/uniform_descriptor_header.h b/hw/kiwi/v2/uniform_descriptor_header.h new file mode 100644 index 000000000000..f06974a20ca2 --- /dev/null +++ b/hw/kiwi/v2/uniform_descriptor_header.h @@ -0,0 +1,56 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_ +#define _UNIFORM_DESCRIPTOR_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1 + +struct uniform_descriptor_header { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t owner : 4, + buffer_type : 4, + reserved_0a : 24; +#else + uint32_t reserved_0a : 24, + buffer_type : 4, + owner : 4; +#endif +}; + +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 + +#endif diff --git a/hw/kiwi/v2/uniform_reo_cmd_header.h b/hw/kiwi/v2/uniform_reo_cmd_header.h new file mode 100644 index 000000000000..ae4423e3bec6 --- /dev/null +++ b/hw/kiwi/v2/uniform_reo_cmd_header.h @@ -0,0 +1,56 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _UNIFORM_REO_CMD_HEADER_H_ +#define _UNIFORM_REO_CMD_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER 1 + +struct uniform_reo_cmd_header { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_cmd_number : 16, + reo_status_required : 1, + reserved_0a : 15; +#else + uint32_t reserved_0a : 15, + reo_status_required : 1, + reo_cmd_number : 16; +#endif +}; + +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_LSB 17 +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_MSB 31 +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#endif diff --git a/hw/kiwi/v2/uniform_reo_status_header.h b/hw/kiwi/v2/uniform_reo_status_header.h new file mode 100644 index 000000000000..d64a576ba35f --- /dev/null +++ b/hw/kiwi/v2/uniform_reo_status_header.h @@ -0,0 +1,70 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _UNIFORM_REO_STATUS_HEADER_H_ +#define _UNIFORM_REO_STATUS_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_UNIFORM_REO_STATUS_HEADER 2 + +struct uniform_reo_status_header { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_status_number : 16, + cmd_execution_time : 10, + reo_cmd_execution_status : 2, + reserved_0a : 4; + uint32_t timestamp : 32; +#else + uint32_t reserved_0a : 4, + reo_cmd_execution_status : 2, + cmd_execution_time : 10, + reo_status_number : 16; + uint32_t timestamp : 32; +#endif +}; + +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_LSB 28 +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_MSB 31 +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_LSB 0 +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_MSB 31 +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#endif diff --git a/hw/kiwi/v2/vht_sig_a_info.h b/hw/kiwi/v2/vht_sig_a_info.h new file mode 100644 index 000000000000..09097907dd3a --- /dev/null +++ b/hw/kiwi/v2/vht_sig_a_info.h @@ -0,0 +1,161 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_A_INFO_H_ +#define _VHT_SIG_A_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_A_INFO 2 + +struct vht_sig_a_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t bandwidth : 2, + vhta_reserved_0 : 1, + stbc : 1, + group_id : 6, + n_sts : 12, + txop_ps_not_allowed : 1, + vhta_reserved_0b : 1, + reserved_0 : 8; + uint32_t gi_setting : 2, + su_mu_coding : 1, + ldpc_extra_symbol : 1, + mcs : 4, + beamformed : 1, + vhta_reserved_1 : 1, + crc : 8, + tail : 6, + reserved_1 : 7, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0 : 8, + vhta_reserved_0b : 1, + txop_ps_not_allowed : 1, + n_sts : 12, + group_id : 6, + stbc : 1, + vhta_reserved_0 : 1, + bandwidth : 2; + uint32_t rx_integrity_check_passed : 1, + reserved_1 : 7, + tail : 6, + crc : 8, + vhta_reserved_1 : 1, + beamformed : 1, + mcs : 4, + ldpc_extra_symbol : 1, + su_mu_coding : 1, + gi_setting : 2; +#endif +}; + +#define VHT_SIG_A_INFO_BANDWIDTH_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_BANDWIDTH_LSB 0 +#define VHT_SIG_A_INFO_BANDWIDTH_MSB 1 +#define VHT_SIG_A_INFO_BANDWIDTH_MASK 0x00000003 + +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_LSB 2 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MSB 2 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MASK 0x00000004 + +#define VHT_SIG_A_INFO_STBC_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_STBC_LSB 3 +#define VHT_SIG_A_INFO_STBC_MSB 3 +#define VHT_SIG_A_INFO_STBC_MASK 0x00000008 + +#define VHT_SIG_A_INFO_GROUP_ID_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_GROUP_ID_LSB 4 +#define VHT_SIG_A_INFO_GROUP_ID_MSB 9 +#define VHT_SIG_A_INFO_GROUP_ID_MASK 0x000003f0 + +#define VHT_SIG_A_INFO_N_STS_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_N_STS_LSB 10 +#define VHT_SIG_A_INFO_N_STS_MSB 21 +#define VHT_SIG_A_INFO_N_STS_MASK 0x003ffc00 + +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_LSB 22 +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MSB 22 +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MASK 0x00400000 + +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_LSB 23 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MSB 23 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MASK 0x00800000 + +#define VHT_SIG_A_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_RESERVED_0_LSB 24 +#define VHT_SIG_A_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_A_INFO_RESERVED_0_MASK 0xff000000 + +#define VHT_SIG_A_INFO_GI_SETTING_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_GI_SETTING_LSB 0 +#define VHT_SIG_A_INFO_GI_SETTING_MSB 1 +#define VHT_SIG_A_INFO_GI_SETTING_MASK 0x00000003 + +#define VHT_SIG_A_INFO_SU_MU_CODING_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_SU_MU_CODING_LSB 2 +#define VHT_SIG_A_INFO_SU_MU_CODING_MSB 2 +#define VHT_SIG_A_INFO_SU_MU_CODING_MASK 0x00000004 + +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_LSB 3 +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MSB 3 +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000008 + +#define VHT_SIG_A_INFO_MCS_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_MCS_LSB 4 +#define VHT_SIG_A_INFO_MCS_MSB 7 +#define VHT_SIG_A_INFO_MCS_MASK 0x000000f0 + +#define VHT_SIG_A_INFO_BEAMFORMED_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_BEAMFORMED_LSB 8 +#define VHT_SIG_A_INFO_BEAMFORMED_MSB 8 +#define VHT_SIG_A_INFO_BEAMFORMED_MASK 0x00000100 + +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_LSB 9 +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MSB 9 +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MASK 0x00000200 + +#define VHT_SIG_A_INFO_CRC_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_CRC_LSB 10 +#define VHT_SIG_A_INFO_CRC_MSB 17 +#define VHT_SIG_A_INFO_CRC_MASK 0x0003fc00 + +#define VHT_SIG_A_INFO_TAIL_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_TAIL_LSB 18 +#define VHT_SIG_A_INFO_TAIL_MSB 23 +#define VHT_SIG_A_INFO_TAIL_MASK 0x00fc0000 + +#define VHT_SIG_A_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_RESERVED_1_LSB 24 +#define VHT_SIG_A_INFO_RESERVED_1_MSB 30 +#define VHT_SIG_A_INFO_RESERVED_1_MASK 0x7f000000 + +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/kiwi/v2/wbm2sw_completion_ring_rx.h b/hw/kiwi/v2/wbm2sw_completion_ring_rx.h new file mode 100644 index 000000000000..60b2cb30f908 --- /dev/null +++ b/hw/kiwi/v2/wbm2sw_completion_ring_rx.h @@ -0,0 +1,312 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _WBM2SW_COMPLETION_RING_RX_H_ +#define _WBM2SW_COMPLETION_RING_RX_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_msdu_desc_info.h" +#include "rx_mpdu_desc_info.h" +#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_RX 8 + +struct wbm2sw_completion_ring_rx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t release_source_module : 3, + bm_action : 3, + buffer_or_desc_type : 3, + return_buffer_manager : 4, + reserved_2a : 2, + cache_id : 1, + cookie_conversion_status : 1, + rxdma_push_reason : 2, + rxdma_error_code : 5, + reo_push_reason : 2, + reo_error_code : 5, + wbm_internal_error : 1; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_phys_addr_31_0 : 32; + uint32_t buffer_phys_addr_39_32 : 8, + sw_buffer_cookie : 20, + looping_count : 4; +#else + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t wbm_internal_error : 1, + reo_error_code : 5, + reo_push_reason : 2, + rxdma_error_code : 5, + rxdma_push_reason : 2, + cookie_conversion_status : 1, + cache_id : 1, + reserved_2a : 2, + return_buffer_manager : 4, + buffer_or_desc_type : 3, + bm_action : 3, + release_source_module : 3; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_phys_addr_31_0 : 32; + uint32_t looping_count : 4, + sw_buffer_cookie : 20, + buffer_phys_addr_39_32 : 8; +#endif +}; + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_LSB 3 +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MSB 5 +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MASK 0x00000038 + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_LSB 9 +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MSB 12 +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 + +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_LSB 13 +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MSB 14 +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MASK 0x00006000 + +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_LSB 15 +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MSB 15 +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MASK 0x00008000 + +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 + +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_LSB 17 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MSB 18 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 + +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_LSB 19 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MSB 23 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 + +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_LSB 24 +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MSB 25 +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MASK 0x03000000 + +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_LSB 26 +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MSB 30 +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 + +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000 + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_OFFSET 0x00000018 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MSB 7 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MASK 0x000000ff + +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_LSB 8 +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MSB 27 +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MASK 0x0fffff00 + +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_LSB 28 +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/kiwi/v2/wbm2sw_completion_ring_tx.h b/hw/kiwi/v2/wbm2sw_completion_ring_tx.h new file mode 100644 index 000000000000..892c62951ee3 --- /dev/null +++ b/hw/kiwi/v2/wbm2sw_completion_ring_tx.h @@ -0,0 +1,261 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _WBM2SW_COMPLETION_RING_TX_H_ +#define _WBM2SW_COMPLETION_RING_TX_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "tx_rate_stats_info.h" +#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_TX 8 + +struct wbm2sw_completion_ring_tx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t release_source_module : 3, + cache_id : 1, + reserved_2a : 2, + buffer_or_desc_type : 3, + return_buffer_manager : 4, + tqm_release_reason : 4, + rbm_override_valid : 1, + sw_buffer_cookie_11_0 : 12, + cookie_conversion_status : 1, + wbm_internal_error : 1; + uint32_t tqm_status_number : 24, + transmit_count : 7, + sw_release_details_valid : 1; + uint32_t ack_frame_rssi : 8, + first_msdu : 1, + last_msdu : 1, + fw_tx_notify_frame : 3, + buffer_timestamp : 19; + struct tx_rate_stats_info tx_rate_stats; + uint32_t sw_peer_id : 16, + tid : 4, + sw_buffer_cookie_19_12 : 8, + looping_count : 4; +#else + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t wbm_internal_error : 1, + cookie_conversion_status : 1, + sw_buffer_cookie_11_0 : 12, + rbm_override_valid : 1, + tqm_release_reason : 4, + return_buffer_manager : 4, + buffer_or_desc_type : 3, + reserved_2a : 2, + cache_id : 1, + release_source_module : 3; + uint32_t sw_release_details_valid : 1, + transmit_count : 7, + tqm_status_number : 24; + uint32_t buffer_timestamp : 19, + fw_tx_notify_frame : 3, + last_msdu : 1, + first_msdu : 1, + ack_frame_rssi : 8; + struct tx_rate_stats_info tx_rate_stats; + uint32_t looping_count : 4, + sw_buffer_cookie_19_12 : 8, + tid : 4, + sw_peer_id : 16; +#endif +}; + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_LSB 3 +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MSB 3 +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MASK 0x00000008 + +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_LSB 4 +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MSB 5 +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MASK 0x00000030 + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_LSB 9 +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MSB 12 +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 + +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_LSB 13 +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MSB 16 +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MASK 0x0001e000 + +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_LSB 17 +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MSB 17 +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MASK 0x00020000 + +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_LSB 18 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MSB 29 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MASK 0x3ffc0000 + +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_LSB 30 +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MSB 30 +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MASK 0x40000000 + +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MASK 0x80000000 + +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MSB 23 +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MASK 0x00ffffff + +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_LSB 24 +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MSB 30 +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MASK 0x7f000000 + +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_LSB 31 +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 + +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MSB 7 +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MASK 0x000000ff + +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_LSB 8 +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MSB 8 +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MASK 0x00000100 + +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_LSB 9 +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MSB 9 +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MASK 0x00000200 + +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_LSB 10 +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MSB 12 +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_LSB 13 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MASK 0xffffe000 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB 1 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB 3 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB 15 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0000f000 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 16 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 16 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00010000 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB 17 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB 28 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK 0x1ffe0000 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_RESERVED_0A_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_RESERVED_0A_LSB 29 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_RESERVED_0A_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_RESERVED_0A_MASK 0xe0000000 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MSB 15 +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MASK 0x0000ffff + +#define WBM2SW_COMPLETION_RING_TX_TID_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_TID_LSB 16 +#define WBM2SW_COMPLETION_RING_TX_TID_MSB 19 +#define WBM2SW_COMPLETION_RING_TX_TID_MASK 0x000f0000 + +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_LSB 20 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MSB 27 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MASK 0x0ff00000 + +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_LSB 28 +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/kiwi/v2/wbm_buffer_ring.h b/hw/kiwi/v2/wbm_buffer_ring.h new file mode 100644 index 000000000000..f4e5fb31b49d --- /dev/null +++ b/hw/kiwi/v2/wbm_buffer_ring.h @@ -0,0 +1,58 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _WBM_BUFFER_RING_H_ +#define _WBM_BUFFER_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_BUFFER_RING 2 + +struct wbm_buffer_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buf_addr_info; +#else + struct buffer_addr_info buf_addr_info; +#endif +}; + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#endif diff --git a/hw/kiwi/v2/wbm_link_descriptor_ring.h b/hw/kiwi/v2/wbm_link_descriptor_ring.h new file mode 100644 index 000000000000..74d179c0207a --- /dev/null +++ b/hw/kiwi/v2/wbm_link_descriptor_ring.h @@ -0,0 +1,58 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _WBM_LINK_DESCRIPTOR_RING_H_ +#define _WBM_LINK_DESCRIPTOR_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2 + +struct wbm_link_descriptor_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info desc_addr_info; +#else + struct buffer_addr_info desc_addr_info; +#endif +}; + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#endif diff --git a/hw/kiwi/v2/wbm_release_ring.h b/hw/kiwi/v2/wbm_release_ring.h new file mode 100644 index 000000000000..c3e7260ae567 --- /dev/null +++ b/hw/kiwi/v2/wbm_release_ring.h @@ -0,0 +1,135 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _WBM_RELEASE_RING_H_ +#define _WBM_RELEASE_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_RELEASE_RING 8 + +struct wbm_release_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t release_source_module : 3, + reserved_2a : 3, + buffer_or_desc_type : 3, + reserved_2b : 22, + wbm_internal_error : 1; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 28, + looping_count : 4; +#else + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t wbm_internal_error : 1, + reserved_2b : 22, + buffer_or_desc_type : 3, + reserved_2a : 3, + release_source_module : 3; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t looping_count : 4, + reserved_7a : 28; +#endif +}; + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 + +#define WBM_RELEASE_RING_RESERVED_2A_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RESERVED_2A_LSB 3 +#define WBM_RELEASE_RING_RESERVED_2A_MSB 5 +#define WBM_RELEASE_RING_RESERVED_2A_MASK 0x00000038 + +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + +#define WBM_RELEASE_RING_RESERVED_2B_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RESERVED_2B_LSB 9 +#define WBM_RELEASE_RING_RESERVED_2B_MSB 30 +#define WBM_RELEASE_RING_RESERVED_2B_MASK 0x7ffffe00 + +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_LSB 31 +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MSB 31 +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MASK 0x80000000 + +#define WBM_RELEASE_RING_RESERVED_3A_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RESERVED_3A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_3A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_3A_MASK 0xffffffff + +#define WBM_RELEASE_RING_RESERVED_4A_OFFSET 0x00000010 +#define WBM_RELEASE_RING_RESERVED_4A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_4A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_4A_MASK 0xffffffff + +#define WBM_RELEASE_RING_RESERVED_5A_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RESERVED_5A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_5A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_5A_MASK 0xffffffff + +#define WBM_RELEASE_RING_RESERVED_6A_OFFSET 0x00000018 +#define WBM_RELEASE_RING_RESERVED_6A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_6A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_6A_MASK 0xffffffff + +#define WBM_RELEASE_RING_RESERVED_7A_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RESERVED_7A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_7A_MSB 27 +#define WBM_RELEASE_RING_RESERVED_7A_MASK 0x0fffffff + +#define WBM_RELEASE_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM_RELEASE_RING_LOOPING_COUNT_LSB 28 +#define WBM_RELEASE_RING_LOOPING_COUNT_MSB 31 +#define WBM_RELEASE_RING_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/kiwi/v2/wbm_release_ring_rx.h b/hw/kiwi/v2/wbm_release_ring_rx.h new file mode 100644 index 000000000000..d65b9bcf9531 --- /dev/null +++ b/hw/kiwi/v2/wbm_release_ring_rx.h @@ -0,0 +1,321 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _WBM_RELEASE_RING_RX_H_ +#define _WBM_RELEASE_RING_RX_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_msdu_desc_info.h" +#include "rx_mpdu_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_RELEASE_RING_RX 8 + +struct wbm_release_ring_rx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t release_source_module : 3, + bm_action : 3, + buffer_or_desc_type : 3, + first_msdu_index : 4, + reserved_2a : 2, + cache_id : 1, + cookie_conversion_status : 1, + rxdma_push_reason : 2, + rxdma_error_code : 5, + reo_push_reason : 2, + reo_error_code : 5, + wbm_internal_error : 1; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 20, + ring_id : 8, + looping_count : 4; +#else + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t wbm_internal_error : 1, + reo_error_code : 5, + reo_push_reason : 2, + rxdma_error_code : 5, + rxdma_push_reason : 2, + cookie_conversion_status : 1, + cache_id : 1, + reserved_2a : 2, + first_msdu_index : 4, + buffer_or_desc_type : 3, + bm_action : 3, + release_source_module : 3; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t reserved_6a : 32; + uint32_t looping_count : 4, + ring_id : 8, + reserved_7a : 20; +#endif +}; + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + +#define WBM_RELEASE_RING_RX_BM_ACTION_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_BM_ACTION_LSB 3 +#define WBM_RELEASE_RING_RX_BM_ACTION_MSB 5 +#define WBM_RELEASE_RING_RX_BM_ACTION_MASK 0x00000038 + +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_LSB 9 +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MSB 12 +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MASK 0x00001e00 + +#define WBM_RELEASE_RING_RX_RESERVED_2A_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RESERVED_2A_LSB 13 +#define WBM_RELEASE_RING_RX_RESERVED_2A_MSB 14 +#define WBM_RELEASE_RING_RX_RESERVED_2A_MASK 0x00006000 + +#define WBM_RELEASE_RING_RX_CACHE_ID_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_CACHE_ID_LSB 15 +#define WBM_RELEASE_RING_RX_CACHE_ID_MSB 15 +#define WBM_RELEASE_RING_RX_CACHE_ID_MASK 0x00008000 + +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 + +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_LSB 17 +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MSB 18 +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 + +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_LSB 19 +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MSB 23 +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 + +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_LSB 24 +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MSB 25 +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MASK 0x03000000 + +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_LSB 26 +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MSB 30 +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 + +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000 + +#define WBM_RELEASE_RING_RX_RESERVED_6A_OFFSET 0x00000018 +#define WBM_RELEASE_RING_RX_RESERVED_6A_LSB 0 +#define WBM_RELEASE_RING_RX_RESERVED_6A_MSB 31 +#define WBM_RELEASE_RING_RX_RESERVED_6A_MASK 0xffffffff + +#define WBM_RELEASE_RING_RX_RESERVED_7A_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RX_RESERVED_7A_LSB 0 +#define WBM_RELEASE_RING_RX_RESERVED_7A_MSB 19 +#define WBM_RELEASE_RING_RX_RESERVED_7A_MASK 0x000fffff + +#define WBM_RELEASE_RING_RX_RING_ID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RX_RING_ID_LSB 20 +#define WBM_RELEASE_RING_RX_RING_ID_MSB 27 +#define WBM_RELEASE_RING_RX_RING_ID_MASK 0x0ff00000 + +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_LSB 28 +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_MSB 31 +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/kiwi/v2/wbm_release_ring_tx.h b/hw/kiwi/v2/wbm_release_ring_tx.h new file mode 100644 index 000000000000..e62f63e0c9df --- /dev/null +++ b/hw/kiwi/v2/wbm_release_ring_tx.h @@ -0,0 +1,277 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _WBM_RELEASE_RING_TX_H_ +#define _WBM_RELEASE_RING_TX_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "tx_rate_stats_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_RELEASE_RING_TX 8 + +struct wbm_release_ring_tx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t release_source_module : 3, + bm_action : 3, + buffer_or_desc_type : 3, + first_msdu_index : 4, + tqm_release_reason : 4, + rbm_override_valid : 1, + rbm_override : 4, + reserved_2a : 7, + cache_id : 1, + cookie_conversion_status : 1, + wbm_internal_error : 1; + uint32_t tqm_status_number : 24, + transmit_count : 7, + sw_release_details_valid : 1; + uint32_t ack_frame_rssi : 8, + first_msdu : 1, + last_msdu : 1, + fw_tx_notify_frame : 3, + buffer_timestamp : 19; + struct tx_rate_stats_info tx_rate_stats; + uint32_t sw_peer_id : 16, + tid : 4, + tqm_status_number_31_24 : 8, + looping_count : 4; +#else + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t wbm_internal_error : 1, + cookie_conversion_status : 1, + cache_id : 1, + reserved_2a : 7, + rbm_override : 4, + rbm_override_valid : 1, + tqm_release_reason : 4, + first_msdu_index : 4, + buffer_or_desc_type : 3, + bm_action : 3, + release_source_module : 3; + uint32_t sw_release_details_valid : 1, + transmit_count : 7, + tqm_status_number : 24; + uint32_t buffer_timestamp : 19, + fw_tx_notify_frame : 3, + last_msdu : 1, + first_msdu : 1, + ack_frame_rssi : 8; + struct tx_rate_stats_info tx_rate_stats; + uint32_t looping_count : 4, + tqm_status_number_31_24 : 8, + tid : 4, + sw_peer_id : 16; +#endif +}; + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + +#define WBM_RELEASE_RING_TX_BM_ACTION_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_BM_ACTION_LSB 3 +#define WBM_RELEASE_RING_TX_BM_ACTION_MSB 5 +#define WBM_RELEASE_RING_TX_BM_ACTION_MASK 0x00000038 + +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_LSB 9 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MSB 12 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MASK 0x00001e00 + +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_LSB 13 +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MSB 16 +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MASK 0x0001e000 + +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_LSB 17 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MSB 17 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MASK 0x00020000 + +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_LSB 18 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MSB 21 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MASK 0x003c0000 + +#define WBM_RELEASE_RING_TX_RESERVED_2A_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RESERVED_2A_LSB 22 +#define WBM_RELEASE_RING_TX_RESERVED_2A_MSB 28 +#define WBM_RELEASE_RING_TX_RESERVED_2A_MASK 0x1fc00000 + +#define WBM_RELEASE_RING_TX_CACHE_ID_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_CACHE_ID_LSB 29 +#define WBM_RELEASE_RING_TX_CACHE_ID_MSB 29 +#define WBM_RELEASE_RING_TX_CACHE_ID_MASK 0x20000000 + +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_LSB 30 +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MSB 30 +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MASK 0x40000000 + +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MASK 0x80000000 + +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_LSB 0 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MSB 23 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MASK 0x00ffffff + +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_OFFSET 0x0000000c +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_LSB 24 +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MSB 30 +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MASK 0x7f000000 + +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_LSB 31 +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MSB 31 +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 + +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_LSB 0 +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MSB 7 +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MASK 0x000000ff + +#define WBM_RELEASE_RING_TX_FIRST_MSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_LSB 8 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_MSB 8 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_MASK 0x00000100 + +#define WBM_RELEASE_RING_TX_LAST_MSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_LAST_MSDU_LSB 9 +#define WBM_RELEASE_RING_TX_LAST_MSDU_MSB 9 +#define WBM_RELEASE_RING_TX_LAST_MSDU_MASK 0x00000200 + +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_LSB 10 +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MSB 12 +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 + +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_LSB 13 +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MSB 31 +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MASK 0xffffe000 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB 1 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB 3 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB 15 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0000f000 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 16 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 16 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00010000 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB 17 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB 28 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK 0x1ffe0000 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_RESERVED_0A_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_RESERVED_0A_LSB 29 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_RESERVED_0A_MSB 31 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_RESERVED_0A_MASK 0xe0000000 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + +#define WBM_RELEASE_RING_TX_SW_PEER_ID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_SW_PEER_ID_LSB 0 +#define WBM_RELEASE_RING_TX_SW_PEER_ID_MSB 15 +#define WBM_RELEASE_RING_TX_SW_PEER_ID_MASK 0x0000ffff + +#define WBM_RELEASE_RING_TX_TID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_TID_LSB 16 +#define WBM_RELEASE_RING_TX_TID_MSB 19 +#define WBM_RELEASE_RING_TX_TID_MASK 0x000f0000 + +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_LSB 20 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MSB 27 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MASK 0x0ff00000 + +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_LSB 28 +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_MSB 31 +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/kiwi/v2/wcss_seq_hwiobase.h b/hw/kiwi/v2/wcss_seq_hwiobase.h new file mode 100644 index 000000000000..103c99a42dca --- /dev/null +++ b/hw/kiwi/v2/wcss_seq_hwiobase.h @@ -0,0 +1,111 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef __WCSS_SEQ_HWIOBASE_H__ +#define __WCSS_SEQ_HWIOBASE_H__ + +#define WCSS_CFGBUS_BASE 0x00008000 +#define WCSS_CFGBUS_BASE_SIZE 0x00008000 +#define WCSS_CFGBUS_BASE_PHYS 0x00008000 + +#define UMAC_NOC_BASE 0x00140000 +#define UMAC_NOC_BASE_SIZE 0x00004400 +#define UMAC_NOC_BASE_PHYS 0x00140000 + +#define PHYA0_BASE 0x00300000 +#define PHYA0_BASE_SIZE 0x00300000 +#define PHYA0_BASE_PHYS 0x00300000 + +#define PHYA1_BASE 0x00600000 +#define PHYA1_BASE_SIZE 0x00300000 +#define PHYA1_BASE_PHYS 0x00600000 + +#define DMAC_BASE 0x00900000 +#define DMAC_BASE_SIZE 0x00080000 +#define DMAC_BASE_PHYS 0x00900000 + +#define UMAC_BASE 0x00a00000 +#define UMAC_BASE_SIZE 0x0004d000 +#define UMAC_BASE_PHYS 0x00a00000 + +#define PMAC0_BASE 0x00a80000 +#define PMAC0_BASE_SIZE 0x00040000 +#define PMAC0_BASE_PHYS 0x00a80000 + +#define PMAC1_BASE 0x00ac0000 +#define PMAC1_BASE_SIZE 0x00040000 +#define PMAC1_BASE_PHYS 0x00ac0000 + +#define CXC_BASE 0x00b40000 +#define CXC_BASE_SIZE 0x00010000 +#define CXC_BASE_PHYS 0x00b40000 + +#define WFSS_PMM_BASE 0x00b50000 +#define WFSS_PMM_BASE_SIZE 0x00002401 +#define WFSS_PMM_BASE_PHYS 0x00b50000 + +#define WFSS_CC_BASE 0x00b60000 +#define WFSS_CC_BASE_SIZE 0x00008000 +#define WFSS_CC_BASE_PHYS 0x00b60000 + +#define WCMN_CORE_BASE 0x00b68000 +#define WCMN_CORE_BASE_SIZE 0x000008a9 +#define WCMN_CORE_BASE_PHYS 0x00b68000 + +#define WIFI_CFGBUS_APB_TSLV_BASE 0x00b6b000 +#define WIFI_CFGBUS_APB_TSLV_BASE_SIZE 0x00001000 +#define WIFI_CFGBUS_APB_TSLV_BASE_PHYS 0x00b6b000 + +#define WFSS_CFGBUS_BASE 0x00b6c000 +#define WFSS_CFGBUS_BASE_SIZE 0x000000a0 +#define WFSS_CFGBUS_BASE_PHYS 0x00b6c000 + +#define WIFI_CFGBUS_AHB_TSLV_BASE 0x00b6d000 +#define WIFI_CFGBUS_AHB_TSLV_BASE_SIZE 0x00001000 +#define WIFI_CFGBUS_AHB_TSLV_BASE_PHYS 0x00b6d000 + +#define UMAC_ACMT_BASE 0x00b6e000 +#define UMAC_ACMT_BASE_SIZE 0x00001000 +#define UMAC_ACMT_BASE_PHYS 0x00b6e000 + +#define WCSS_CC_BASE 0x00b80000 +#define WCSS_CC_BASE_SIZE 0x00010000 +#define WCSS_CC_BASE_PHYS 0x00b80000 + +#define PMM_TOP_BASE 0x00b90000 +#define PMM_TOP_BASE_SIZE 0x00010000 +#define PMM_TOP_BASE_PHYS 0x00b90000 + +#define WCSS_TOP_CMN_BASE 0x00ba0000 +#define WCSS_TOP_CMN_BASE_SIZE 0x00004000 +#define WCSS_TOP_CMN_BASE_PHYS 0x00ba0000 + +#define MSIP_BASE 0x00bb0000 +#define MSIP_BASE_SIZE 0x00010000 +#define MSIP_BASE_PHYS 0x00bb0000 + +#define DBG_BASE 0x01000000 +#define DBG_BASE_SIZE 0x00100000 +#define DBG_BASE_PHYS 0x01000000 + +#define Q6SS_WLAN_BASE 0x01100000 +#define Q6SS_WLAN_BASE_SIZE 0x00100000 +#define Q6SS_WLAN_BASE_PHYS 0x01100000 + +#endif diff --git a/hw/kiwi/v2/wcss_seq_hwioreg_umac.h b/hw/kiwi/v2/wcss_seq_hwioreg_umac.h new file mode 100644 index 000000000000..9ce4197c35f7 --- /dev/null +++ b/hw/kiwi/v2/wcss_seq_hwioreg_umac.h @@ -0,0 +1,324 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef __WCSS_SEQ_HWIOREG_UMAC_H__ +#define __WCSS_SEQ_HWIOREG_UMAC_H__ + +#include "seq_hwio.h" +#include "wcss_seq_hwiobase.h" +#ifdef SCALE_INCLUDES +#include "HALhwio.h" +#else +#include "msmhwio.h" +#endif + +#define WBM_REG_REG_BASE (UMAC_BASE + 0x00034000) +#define HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x40) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x44) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff +#define HWIO_WBM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 + +#define HWIO_WBM_R0_MISC_CONTROL_ADDR(x) ((x) + 0x7c) +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x) ((x) + 0x94) +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM_COOKIE_CONV_GLOBAL_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM_COOKIE_CONV_GLOBAL_ENABLE_SHFT 8 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW6_COOKIE_CONVERSION_EN_BMSK 0x80 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW6_COOKIE_CONVERSION_EN_SHFT 7 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW5_COOKIE_CONVERSION_EN_BMSK 0x40 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW5_COOKIE_CONVERSION_EN_SHFT 6 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW4_COOKIE_CONVERSION_EN_BMSK 0x20 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW4_COOKIE_CONVERSION_EN_SHFT 5 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW3_COOKIE_CONVERSION_EN_BMSK 0x10 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW3_COOKIE_CONVERSION_EN_SHFT 4 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW2_COOKIE_CONVERSION_EN_BMSK 0x8 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW2_COOKIE_CONVERSION_EN_SHFT 3 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW1_COOKIE_CONVERSION_EN_BMSK 0x4 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW1_COOKIE_CONVERSION_EN_SHFT 2 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW0_COOKIE_CONVERSION_EN_BMSK 0x2 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW0_COOKIE_CONVERSION_EN_SHFT 1 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2FW_COOKIE_CONVERSION_EN_BMSK 0x1 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2FW_COOKIE_CONVERSION_EN_SHFT 0 + +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x) ((x) + 0x240) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_BMSK 0x7fc +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_SHFT 2 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_BMSK 0x2 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_SHFT 1 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x) ((x) + 0x244) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_BMSK 0xffff0000 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_SHFT 16 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_BMSK 0xffff +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x) ((x) + 0x250) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x) ((x) + 0x254) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK 0xffffff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT 8 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK 0xff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x) ((x) + 0x260) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x) ((x) + 0x264) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK 0x1fff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT 8 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x) ((x) + 0x270) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x) ((x) + 0x274) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK 0x1fff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT 8 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x) ((x) + 0x27c) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x37c) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0xd3c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x) ((x) + 0xd4c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xe08) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xe80) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x) ((x) + 0x3010) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x) ((x) + 0x30b8) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x) ((x) + 0x30c8) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x) ((x) + 0x30d0) +#define REO_REG_REG_BASE (UMAC_BASE + 0x00038000) +#define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x) ((x) + 0x0) +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK 0x8 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_SHFT 3 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK 0x4 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_SHFT 2 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x) ((x) + 0xc) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x) ((x) + 0x10) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT 0 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x) ((x) + 0x28) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK 0xf0000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT 28 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK 0xf000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT 24 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK 0xf00000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT 20 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK 0xf0000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT 16 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK 0xf000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT 12 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK 0xf00 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT 8 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK 0xf0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT 4 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK 0xf +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT 0 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x) ((x) + 0x2c) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT 24 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT 20 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT 16 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT 12 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT 8 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_SHFT 4 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_SHFT 0 + +#define HWIO_REO_R0_PN_IN_DEST_ADDR(x) ((x) + 0x4c) +#define HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x50) +#define HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x54) +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_BMSK 0x100000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_SHFT 20 +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_BMSK 0x80000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_SHFT 19 +#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 +#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff +#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x) ((x) + 0x28c) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x) ((x) + 0x304) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x) ((x) + 0x4e4) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x) ((x) + 0x4e8) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x) ((x) + 0x4ec) +#define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) ((x) + 0x4f4) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x4f8) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x4fc) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x508) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x52c) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x530) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) ((x) + 0x534) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x538) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x53c) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x540) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x) ((x) + 0x544) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) ((x) + 0x55c) +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x) ((x) + 0x8a4) +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0xa84) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x) ((x) + 0xb08) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x) ((x) + 0xb0c) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x) ((x) + 0xb10) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x) ((x) + 0xb14) +#define HWIO_REO_R0_MISC_CTL_ADDR(x) ((x) + 0xb7c) +#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_BMSK 0x1e00000 +#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_SHFT 21 +#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK 0x1e0000 +#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_SHFT 17 +#define HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x) ((x) + 0x3020) +#define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x) ((x) + 0x3028) +#define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x) ((x) + 0x3048) +#define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x) ((x) + 0x304c) +#define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x) ((x) + 0x3050) +#define HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x) ((x) + 0x3088) +#define HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x) ((x) + 0x30a8) +#define MAC_TCL_REG_REG_BASE (UMAC_BASE + 0x00044000) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) ((x) + 0x20) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK 0x800000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT 23 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n) ((base) + 0X8C + (0x4*(n))) +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT 17 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT 15 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT 14 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT 12 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT 11 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT 10 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT 9 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT 8 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT 7 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT 3 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT 1 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT 0 + +#define HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n) ((base) + 0X240 + (0x4*(n))) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK 0xffffffff +#define HWIO_TCL_R0_PCP_TID_MAP_ADDR(x) ((x) + 0x6c0) +#define HWIO_TCL_R0_PCP_TID_MAP_RMSK 0xffffff +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT 21 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT 18 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT 15 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT 12 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT 9 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT 6 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT 3 +#define HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x) ((x) + 0x6e8) +#define HWIO_TCL_R0_TID_MAP_PRTY_RMSK 0xef +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) ((x) + 0x900) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) ((x) + 0x904) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) ((x) + 0x908) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) ((x) + 0x910) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x91c) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x920) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x930) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x934) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x948) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x94c) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) ((x) + 0x950) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) ((x) + 0x978) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x) ((x) + 0xb58) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x) ((x) + 0xd38) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x) ((x) + 0x2000) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x) ((x) + 0x2004) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x) ((x) + 0x2008) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x) ((x) + 0x2028) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x) ((x) + 0x2048) +#endif diff --git a/hw/kiwi/v2/wcss_version.h b/hw/kiwi/v2/wcss_version.h new file mode 100644 index 000000000000..89a2c59e9015 --- /dev/null +++ b/hw/kiwi/v2/wcss_version.h @@ -0,0 +1,20 @@ + +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#define WCSS_VERSION 2219 -- GitLab From f80d1b12a34f4acfc6c3742ff8e380ef6871b24a Mon Sep 17 00:00:00 2001 From: Vinay Adella Date: Thu, 3 Feb 2022 22:41:33 +0530 Subject: [PATCH 19/42] fw-api: Add rx_reo_queue_1k.h header for qcn9224 This is needed to configure reo desc for 1k ADDBA Change-Id: Ife4b5917d82ed1ed6789af50d64414007a82f89e --- hw/qcn9224/rx_reo_queue_1k.h | 266 +++++++++++++++++++++++++++++++++++ 1 file changed, 266 insertions(+) create mode 100644 hw/qcn9224/rx_reo_queue_1k.h diff --git a/hw/qcn9224/rx_reo_queue_1k.h b/hw/qcn9224/rx_reo_queue_1k.h new file mode 100644 index 000000000000..76ce3dc2149b --- /dev/null +++ b/hw/qcn9224/rx_reo_queue_1k.h @@ -0,0 +1,266 @@ + +/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_REO_QUEUE_1K_H_ +#define _RX_REO_QUEUE_1K_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" +#define NUM_OF_DWORDS_RX_REO_QUEUE_1K 32 + + +struct rx_reo_queue_1k { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_descriptor_header descriptor_header; + uint32_t rx_bitmap_319_288 : 32; + uint32_t rx_bitmap_351_320 : 32; + uint32_t rx_bitmap_383_352 : 32; + uint32_t rx_bitmap_415_384 : 32; + uint32_t rx_bitmap_447_416 : 32; + uint32_t rx_bitmap_479_448 : 32; + uint32_t rx_bitmap_511_480 : 32; + uint32_t rx_bitmap_543_512 : 32; + uint32_t rx_bitmap_575_544 : 32; + uint32_t rx_bitmap_607_576 : 32; + uint32_t rx_bitmap_639_608 : 32; + uint32_t rx_bitmap_671_640 : 32; + uint32_t rx_bitmap_703_672 : 32; + uint32_t rx_bitmap_735_704 : 32; + uint32_t rx_bitmap_767_736 : 32; + uint32_t rx_bitmap_799_768 : 32; + uint32_t rx_bitmap_831_800 : 32; + uint32_t rx_bitmap_863_832 : 32; + uint32_t rx_bitmap_895_864 : 32; + uint32_t rx_bitmap_927_896 : 32; + uint32_t rx_bitmap_959_928 : 32; + uint32_t rx_bitmap_991_960 : 32; + uint32_t rx_bitmap_1023_992 : 32; + uint32_t reserved_24 : 32; + uint32_t reserved_25 : 32; + uint32_t reserved_26 : 32; + uint32_t reserved_27 : 32; + uint32_t reserved_28 : 32; + uint32_t reserved_29 : 32; + uint32_t reserved_30 : 32; + uint32_t reserved_31 : 32; +#else + struct uniform_descriptor_header descriptor_header; + uint32_t rx_bitmap_319_288 : 32; + uint32_t rx_bitmap_351_320 : 32; + uint32_t rx_bitmap_383_352 : 32; + uint32_t rx_bitmap_415_384 : 32; + uint32_t rx_bitmap_447_416 : 32; + uint32_t rx_bitmap_479_448 : 32; + uint32_t rx_bitmap_511_480 : 32; + uint32_t rx_bitmap_543_512 : 32; + uint32_t rx_bitmap_575_544 : 32; + uint32_t rx_bitmap_607_576 : 32; + uint32_t rx_bitmap_639_608 : 32; + uint32_t rx_bitmap_671_640 : 32; + uint32_t rx_bitmap_703_672 : 32; + uint32_t rx_bitmap_735_704 : 32; + uint32_t rx_bitmap_767_736 : 32; + uint32_t rx_bitmap_799_768 : 32; + uint32_t rx_bitmap_831_800 : 32; + uint32_t rx_bitmap_863_832 : 32; + uint32_t rx_bitmap_895_864 : 32; + uint32_t rx_bitmap_927_896 : 32; + uint32_t rx_bitmap_959_928 : 32; + uint32_t rx_bitmap_991_960 : 32; + uint32_t rx_bitmap_1023_992 : 32; + uint32_t reserved_24 : 32; + uint32_t reserved_25 : 32; + uint32_t reserved_26 : 32; + uint32_t reserved_27 : 32; + uint32_t reserved_28 : 32; + uint32_t reserved_29 : 32; + uint32_t reserved_30 : 32; + uint32_t reserved_31 : 32; +#endif +}; + +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 + +#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_OFFSET 0x00000004 +#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_OFFSET 0x00000008 +#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_OFFSET 0x0000000c +#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_OFFSET 0x00000010 +#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_OFFSET 0x00000014 +#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_OFFSET 0x00000018 +#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_OFFSET 0x0000001c +#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_OFFSET 0x00000020 +#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_OFFSET 0x00000024 +#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_OFFSET 0x00000028 +#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_OFFSET 0x0000002c +#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_OFFSET 0x00000030 +#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_OFFSET 0x00000034 +#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_OFFSET 0x00000038 +#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_OFFSET 0x0000003c +#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_OFFSET 0x00000040 +#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_OFFSET 0x00000044 +#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_OFFSET 0x00000048 +#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_OFFSET 0x0000004c +#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_OFFSET 0x00000050 +#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_OFFSET 0x00000054 +#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_OFFSET 0x00000058 +#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_OFFSET 0x0000005c +#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_24_OFFSET 0x00000060 +#define RX_REO_QUEUE_1K_RESERVED_24_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_24_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_24_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_25_OFFSET 0x00000064 +#define RX_REO_QUEUE_1K_RESERVED_25_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_25_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_25_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_26_OFFSET 0x00000068 +#define RX_REO_QUEUE_1K_RESERVED_26_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_26_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_26_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_27_OFFSET 0x0000006c +#define RX_REO_QUEUE_1K_RESERVED_27_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_27_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_27_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_28_OFFSET 0x00000070 +#define RX_REO_QUEUE_1K_RESERVED_28_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_28_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_28_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_29_OFFSET 0x00000074 +#define RX_REO_QUEUE_1K_RESERVED_29_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_29_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_29_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_30_OFFSET 0x00000078 +#define RX_REO_QUEUE_1K_RESERVED_30_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_30_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_30_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_31_OFFSET 0x0000007c +#define RX_REO_QUEUE_1K_RESERVED_31_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_31_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_31_MASK 0xffffffff + +#endif -- GitLab From 7436f9abf6c29f5c780e64155bacce9074b97930 Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 9 Feb 2022 06:00:53 -0800 Subject: [PATCH 20/42] fw-api: CL 17180216 - update fw common interface files Change-Id: I12f5323493f80861a144b57614cf7250a933112f WMI: add security type scores to roaming AP scoring CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 3 ++- fw/wmi_unified.h | 36 ++++++++++++++++++++++++++++++++++-- 2 files changed, 36 insertions(+), 3 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 0036baeff2a7..2323aa78e920 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -3044,7 +3044,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_MCAST_GROUP_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_score_delta_param, roam_score_delta_param_list, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_cnd_min_rssi_param, roam_cnd_min_rssi_param_list, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_cnd_vendor_scoring_param, roam_cnd_vendor_scoring_param, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_owe_ap_profile, owe_ap_profile, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_owe_ap_profile, owe_ap_profile, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, authmode_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_AP_PROFILE); diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index cf27c6e69767..529e9ae615b9 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -16552,7 +16552,15 @@ typedef struct { #define WLAN_ROAM_SCORE_BAND_5G_INDEX 1 #define WLAN_ROAM_SCORE_BAND_6G_INDEX 2 /* 3 is reserved */ -#define WLAN_ROAM_SCORE_MAX_BAND_INDEX 4 +#define WLAN_ROAM_SCORE_MAX_BAND_NUM_INDICES 4 +#define WLAN_ROAM_SCORE_MAX_BAND_INDEX WLAN_ROAM_SCORE_MAX_BAND_NUM_INDICES + +#define WLAN_ROAM_SCORE_SECURITY_WPA_INDEX 0 +#define WLAN_ROAM_SCORE_SECURITY_WPA2_INDEX 1 +#define WLAN_ROAM_SCORE_SECURITY_WPA3_INDEX 2 +/* 3 is reserved */ +#define WLAN_ROAM_SCORE_SECURITY_MAX_NUM_INDICES 4 + #define WMI_ROAM_GET_BAND_SCORE_PERCENTAGE(value32, band_index) WMI_GET_BITS(value32, (8 * (band_index)), 8) #define WMI_ROAM_SET_BAND_SCORE_PERCENTAGE(value32, score_pcnt, band_index) WMI_SET_BITS(value32, (8 * (band_index)), 8, score_pcnt) @@ -16572,6 +16580,10 @@ typedef struct { #define WLAN_ROAM_SCORE_MLO_INDEX 4 #define WMI_ROAM_GET_MLO_SCORE_PERCENTAGE(value32, mlo_index) WMI_GET_BITS(value32, (8 * (mlo_index)), 8) #define WMI_ROAM_SET_MLO_SCORE_PERCENTAGE(value32, score_pcnt, mlo_index) WMI_SET_BITS(value32, (8 * (mlo_index)), 8, score_pcnt) +#define WMI_ROAM_GET_SECURITY_SCORE_PERCENTAGE(value32, security_index) \ + WMI_GET_BITS(value32, (8 * (security_index)), 8) +#define WMI_ROAM_SET_SECURITY_SCORE_PERCENTAGE(value32, score_pcnt, security_index) \ + WMI_SET_BITS(value32, (8 * (security_index)), 8, score_pcnt) /** best_rssi_threshold: Roamable AP RSSI equal or better than this threshold, full rssi score 100. Units in dBm. @@ -16715,6 +16727,20 @@ typedef struct { A_UINT32 score_pcnt15_to_12; } wmi_roam_cnd_oce_wan_scoring; +/** + * Use macro WMI_ROAM_CND_GET/SET_SECURITY_SCORE_PERCENTAGE + * to get and set the value respectively. + * BITS 0-7 :- It contains scoring percentage of WPA security + * BITS 8-15 :- It contains scoring percentage of WPA2 security + * BITS 16-23 :- It contains scoring percentage of WPA3 security + * BITS 24-31 :- reserved + * + * The value of each score must be 0-100 + */ +typedef struct { + A_UINT32 score_pcnt; +} wmi_roam_cnd_security_scoring; + typedef enum { WMI_VENDOR_ROAM_SCORE_ALGORITHM_ID_NONE = 0, /* Legacy roam score algorithm */ WMI_VENDOR_ROAM_SCORE_ALGORITHM_ID_RSSI_CU_BASED = 1, /* Roam score algorithm based on RSSI and CU */ @@ -16813,6 +16839,9 @@ typedef struct { * Value 0 should be ignored */ A_UINT32 btc_etp_factor; + /* Scoring for security mode */ + A_INT32 security_weightage_pcnt; + wmi_roam_cnd_security_scoring security_scoring; } wmi_roam_cnd_scoring_param; typedef struct { @@ -17091,13 +17120,15 @@ typedef struct { A_UINT32 vdev_id; /* - * Following this structure is the TLV: + * Following this structure are the TLVs: * wmi_ap_profile ap_profile; <-- AP profile info * wmi_roam_cnd_scoring_param roam_cnd_scoring_param * wmi_roam_score_delta_param roam_score_delta_param_list[] * wmi_roam_cnd_min_rssi_param roam_cnd_min_rssi_param_list[] * wmi_roam_cnd_vendor_scoring_param roam_cnd_vendor_scoring_param[] * wmi_owe_ap_profile owe_ap_profile[] + * A_UINT32 authmode_list[] <-- List of authmode allowed for roaming. + * Refer WMI_AUTH_ for authmode values. */ } wmi_roam_ap_profile_fixed_param; @@ -33369,6 +33400,7 @@ typedef enum { WMI_ROAM_CND_OCE_AP_TX_PWR_SCORING = 0x00000800, /* FW considers OCE AP Tx power scoring */ WMI_ROAM_CND_OCE_AP_SUBNET_ID_SCORING = 0x00001000, /* FW considers OCE AP subnet id scoring */ WMI_ROAM_CND_SAE_PK_AP_SCORING = 0x00002000, /* FW considers SAE-PK enabled AP scoring */ + WMI_ROAM_CND_SECURITY_SCORING = 0x00004000, /* FW considers security scoring */ } WMI_ROAM_CND_SCORING_PARAMS; typedef struct { -- GitLab From ee1691737a48d85f099c72eb32e595bc15c3e2d4 Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 9 Feb 2022 06:01:28 -0800 Subject: [PATCH 21/42] fw-api: CL 17183819 - update fw common interface files Add SAWF DEF_QUEUES_MAP_REPORT_REQ flag to report existing vs. hypothetical TIDS Currently the FWs HTT_T2H SAWF DEF_QUEUES_MAP_REPORT_CONF generating code checks whether the default MSDU queues within a TID object within the peer in question are linked to a service class.This doesnt account for cases where a DEF_QUEUES_MAP_REQ has been sent for a peer, but the peer currently has no object for the TID in question because no data for that TID has shown up yet.A flag is being added to specify whether the FWs report should consider only the currently-existing TID objects within the peer, or if it should also consider hypothetical TID objects that could be created within the peer in the future. Change-Id: I9307ef731869e38c1ed447a38a210accfe52a04f CRs-Fixed: 2262693 --- fw/htt.h | 70 +++++++++++++++++++++++++++++++++++++++----------------- 1 file changed, 49 insertions(+), 21 deletions(-) diff --git a/fw/htt.h b/fw/htt.h index fa6f4648b772..e07d20c271a5 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -9355,7 +9355,7 @@ PREPACK struct htt_h2t_sawf_def_queues_map_req { * dword0 - b'7:0 - msg_type: This will be set to * 0x1d (HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ) * b'15:8 - service class ID - * dword1 - b'31:16 - peer ID + * b'31:16 - peer ID * A HTT_H2T_SAWF_DEF_QUEUES_UNMAP_PEER_ID_WILDCARD * value for peer ID indicates that the target should * apply the UNMAP_REQ to all peers. @@ -9371,27 +9371,26 @@ PREPACK struct htt_h2t_sawf_def_queues_unmap_req { #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_M 0x0000FF00 #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_S 8 -#define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_GET(_var) \ - (((_var) & HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_M) >> \ +#define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_GET(word0) \ + (((word0) & HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_M) >> \ HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_S) -#define HTT_RX_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_SET(_var, _val) \ +#define HTT_RX_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID, _val); \ - ((_var) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_S)); \ + ((word0) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_S)); \ } while (0) #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_M 0xFFFF0000 #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_S 16 -#define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_GET(_var) \ - (((_var) & HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_M) >> \ +#define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_GET(word0) \ + (((word0) & HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_M) >> \ HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_S) -#define HTT_RX_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_SET(_var, _val) \ +#define HTT_RX_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID, _val); \ - ((_var) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_S)); \ + ((word0) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_S)); \ } while (0) - /* * MSG_TYPE => HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ * @@ -9403,45 +9402,74 @@ PREPACK struct htt_h2t_sawf_def_queues_unmap_req { * to report what service class (if any) the default MSDU queues for * each of the specified TIDs are linked to. * - * |31 16|15 8|7 0| + * |31 16|15 8|7 1| 0| * |------------------------------+--------------+--------------| * | peer ID | TID mask | msg type | * |------------------------------------------------------------| + * | reserved |ETO| + * |------------------------------------------------------------| * Header fields: * dword0 - b'7:0 - msg_type: This will be set to * 0x1e (HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ) * b'15:8 - TID mask - * dword1 - b'31:16 - peer ID + * b'31:16 - peer ID + * dword1 - b'0 - "Existing Tids Only" flag + * If this flag is set, the DEF_QUEUES_MAP_REPORT_CONF + * message generated by this REQ will only show the + * mapping for TIDs that actually exist in the target's + * peer object. + * Any TIDs that are covered by a MAP_REQ but which + * do not actually exist will be shown as being + * unmapped (i.e. svc class ID 0xff). + * If this flag is cleared, the MAP_REPORT_CONF message + * will consider not only the mapping of TIDs currently + * existing in the peer, but also the mapping that will + * be applied for any TID objects created within this + * peer in the future. + * b'31:1 - reserved for future use */ PREPACK struct htt_h2t_sawf_def_queues_map_report_req { A_UINT32 msg_type :8, tid_mask :8, peer_id :16; + A_UINT32 existing_tids_only:1, + reserved :31; } POSTPACK; -#define HTT_SAWF_DEF_QUEUES_MAP_REPORT_REQ_BYTES 4 +#define HTT_SAWF_DEF_QUEUES_MAP_REPORT_REQ_BYTES 8 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_M 0x0000FF00 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_S 8 -#define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_GET(_var) \ - (((_var) & HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_M) >> \ +#define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_GET(word0) \ + (((word0) & HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_M) >> \ HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_S) -#define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_SET(_var, _val) \ +#define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK, _val); \ - ((_var) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_S));\ + ((word0) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_S));\ } while (0) #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_M 0xFFFF0000 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_S 16 -#define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_GET(_var) \ - (((_var) & HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_M) >> \ +#define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_GET(word0) \ + (((word0) & HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_M) >> \ HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_S) -#define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_SET(_var, _val) \ +#define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID, _val); \ - ((_var) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_S)); \ + ((word0) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_S)); \ + } while (0) + +#define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_M 0x00000001 +#define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_S 0 +#define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_GET(word1) \ + (((word1) & HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_M) >> \ + HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_S) +#define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_SET(word1, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY, _val); \ + ((word1) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_S)); \ } while (0) -- GitLab From 0d36ba4c4a859005e516a9fa1d81a96402d4634a Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 10 Feb 2022 18:00:52 -0800 Subject: [PATCH 22/42] fw-api: CL 17204425 - update fw common interface files Change-Id: I7fdadbd7fd6681180b7b3934c2c0ec44157b8a92 WMI: add recapture_sample_on_gain_change flag to spectral cfg msg CRs-Fixed: 2262693 --- fw/wmi_unified.h | 6 ++++++ fw/wmi_version.h | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 529e9ae615b9..c4af03a276a2 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -6814,6 +6814,12 @@ typedef struct { * agile span center frequency2 (MHz), 0 for normal scan. */ A_UINT32 spectral_scan_center_freq2; + /** + * Flag to enable re-capture of FFT sample if the previous sample has + * AGC gain change bit set. + * Re-capture will be enabled only if scan period is greater than 50us. + */ + A_UINT32 recapture_sample_on_gain_change; } wmi_vdev_spectral_configure_cmd_fixed_param; /* diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 1af8f408ac81..4d3473fa119c 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1114 +#define __WMI_REVISION_ 1115 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From ae8d05fbfc04bb1bbc5e03516f1eb7cb84e0118c Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 11 Feb 2022 06:01:12 -0800 Subject: [PATCH 23/42] fw-api: CL 17207899 - update fw common interface files HTT stats: add 11AX vs. 11BE flag for UL MU-MIMO rx trigger stats Change-Id: Iabe86877f51f9de99658d3dbae54e03bd711e58a CRs-Fixed: 2262693 --- fw/htt_stats.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/fw/htt_stats.h b/fw/htt_stats.h index 2c3ba33babc3..677e12ac8b35 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -534,6 +534,26 @@ typedef enum { HTT_RX_UL_TRIGGER_STATS_UPLOAD_11BE_OFDMA, } htt_rx_ul_trigger_stats_upload_t; +/* + * The htt_rx_ul_mumimo_trigger_stats_upload_t enum values are + * provided by the host as one of the config param elements in + * the HTT_H2T EXT_STATS_REQ message, for stats type == + * HTT_DBG_EXT_STATS_PDEV_UL_MUMIMO_TRIG_STATS. + */ +typedef enum { + /* + * Upload 11ax UL MUMIMO RX Trigger stats + * TLV: htt_rx_pdev_ul_mumimo_trig_stats_tlv + */ + HTT_RX_UL_MUMIMO_TRIGGER_STATS_UPLOAD_11AX, + + /* + * Upload 11be UL MUMIMO RX Trigger stats + * TLV: htt_rx_pdev_ul_mumimo_trig_be_stats_tlv + */ + HTT_RX_UL_MUMIMO_TRIGGER_STATS_UPLOAD_11BE, +} htt_rx_ul_mumimo_trigger_stats_upload_t; + #define HTT_STATS_MAX_STRING_SZ32 4 #define HTT_STATS_MACID_INVALID 0xff #define HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS 10 -- GitLab From 7c08e6a93203293199ae49a95b7a096e2dae7633 Mon Sep 17 00:00:00 2001 From: spuligil Date: Sat, 12 Feb 2022 06:00:57 -0800 Subject: [PATCH 24/42] fw-api: CL 17216446 - update fw common interface files add WMI_SERVICE_BIOS_SAR_SUPPORT def Change-Id: I6214a2dc05aa743468e57159f4bb19e8e8bdd2ed CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + fw/wmi_version.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 2d95602afac7..5d8de4b99d0b 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -576,6 +576,7 @@ typedef enum { WMI_SERVICE_AFC_RESET_SUPPORT = 323, /* Indicates FW supports AFC reset */ WMI_SERVICE_FP_PHY_ERR_FILTER_SUPPORT = 324, /* FW supports monitor ring configurations for filtering in PHY error packets */ WMI_IS_RADAR_FOUND_CHAN_FREQ_IS_CENTER_FREQ = 325, /* FW Supporting radar event on the actual center frequency radar was detected */ + WMI_SERVICE_BIOS_SAR_SUPPORT = 326, /* FW support for SAR parameter stored in BIOS */ WMI_MAX_EXT2_SERVICE diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 4d3473fa119c..ce12b834dc2e 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1115 +#define __WMI_REVISION_ 1116 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 565084e521c42611f450f408b9b3f1c850f0d27e Mon Sep 17 00:00:00 2001 From: spuligil Date: Sun, 13 Feb 2022 06:01:09 -0800 Subject: [PATCH 25/42] fw-api: CL 17220375 - update fw common interface files Change-Id: Idc9ce211b8050b443ab85543c20c4a1fe9514b23 WMI: add partner link data to STATS_EXT_EVENT msg, add vdev_id for MLO cases CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 6 ++++-- fw/wmi_unified.h | 51 ++++++++++++++++++++++++++++++++++++++++++++++- fw/wmi_version.h | 2 +- 3 files changed, 55 insertions(+), 4 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 2323aa78e920..0215d20b9d21 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1242,6 +1242,7 @@ typedef enum { WMITLV_TAG_STRUC_wmi_rtt_pasn_deauth_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_tx_send_params_ext, WMITLV_TAG_STRUC_wmi_mgmt_rx_params_ext, + WMITLV_TAG_STRUC_wmi_partner_link_stats, } WMITLV_TAG_ID; /* @@ -5836,10 +5837,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_DIAG_DATA_CONTAINER_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_estimated_linkspeed_event_fixed_param, wmi_peer_estimated_linkspeed_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ESTIMATED_LINKSPEED_EVENTID); -/* NAN Response/Indication Event */ #define WMITLV_TABLE_WMI_STATS_EXT_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_stats_ext_event_fixed_param, wmi_stats_ext_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_partner_link_stats, partner_link_stats, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, partner_link_data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_STATS_EXT_EVENTID); #define WMITLV_TABLE_WMI_OFFLOAD_PROB_RESP_TX_STATUS_EVENTID(id,op,buf,len) \ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index c4af03a276a2..7c0a60999037 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -9497,6 +9497,22 @@ typedef struct { */ } wmi_channel_stats; +/* this structure used for pass vdev id in stats events */ +typedef struct { + union { + struct { + A_UINT32 id : 31, /* the vdev ID */ + validate: 1; /* validate bit, the vdev ID is only valid if this bit set as 1 */ + }; + A_UINT32 vdev_id; + }; +} wmi_vdev_id_info; + +#define WMI_VDEV_ID_INFO_GET_VDEV_ID(vdev_id_info) WMI_GET_BITS(vdev_id_info, 0, 31) +#define WMI_VDEV_ID_INFO_SET_VDEV_ID(vdev_id_info, value) WMI_SET_BITS(vdev_id_info, 0, 31, value) +#define WMI_VDEV_ID_INFO_GET_VALIDATE(vdev_id_info) WMI_GET_BITS(vdev_id_info, 31, 1) +#define WMI_VDEV_ID_INFO_SET_VALIDATE(vdev_id_info, value) WMI_SET_BITS(vdev_id_info, 31, 1, value) + /* * Each step represents 0.5 dB. The starting value is 0 dBm. * Thus the TPC levels cover 0 dBm to 31.5 dBm inclusive in 0.5 dB steps. @@ -9557,6 +9573,8 @@ typedef struct { A_UINT32 power_level_offset; /* radio id for this tx time per power level statistics (if multiple radio supported) */ A_UINT32 radio_id; + /** Indicates the vdev id of the stats for MLO stats query */ + wmi_vdev_id_info vdev_id_info; /* * This TLV will be followed by a TLV containing a variable-length array of * A_UINT32 with tx time per power level data @@ -9573,7 +9591,7 @@ typedef struct { /** Radio statistics (once started) do not stop or get reset unless wifi_clear_link_stats is invoked */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_stats_event_fixed_param */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_radio_link_stats_event_fixed_param */ /** unique id identifying the request, given in the request stats command */ A_UINT32 request_id; /** Number of radios*/ @@ -9592,6 +9610,8 @@ typedef struct { * event having additional channels for the same radio. */ A_UINT32 more_channels; + /** Indicates the vdev id of the stats for MLO stats query */ + wmi_vdev_id_info vdev_id_info; /* * This TLV is followed by another TLV of array of bytes * size of(struct wmi_radio_link_stats); @@ -9670,6 +9690,8 @@ typedef struct { A_UINT32 peer_event_number; /** Indicates if there are more peers which will be sent as seperate peer_stats event */ A_UINT32 more_data; + /** Indicates the vdev id of the stats for MLO stats query */ + wmi_vdev_id_info vdev_id_info; /** * This TLV is followed by another TLV @@ -9948,6 +9970,8 @@ typedef struct { A_UINT32 last_event; /** number of extended MIB stats event structures (wmi_mib_extd_stats) */ A_UINT32 num_mib_extd_stats; + /** Indicates the vdev id of the stats for MLO stats query */ + wmi_vdev_id_info vdev_id_info; /* This TLV is followed by another TLV of array of bytes * A_UINT8 data[]; @@ -10409,6 +10433,8 @@ typedef struct { A_UINT32 rx_mcs_array_len; /** Array size of stats_period[] which contains several stats periods. */ A_UINT32 stats_period_array_len; + /** Indicates the vdev id for MLO case */ + wmi_vdev_id_info vdev_id_info; /** * This TLV is followed by TLVs below: @@ -23502,6 +23528,15 @@ typedef struct { */ } wmi_req_stats_ext_cmd_fixed_param; +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_partner_link_stats */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 data_length; /* length of the stats for this vdev */ + A_UINT32 offset; /* offset of the stats from partner_link_data for this vdev */ +} wmi_partner_link_stats; + typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_stats1_event_fix_param */ A_UINT32 vdev_id; /** vdev ID */ @@ -23511,6 +23546,18 @@ typedef struct { * Following this structure is the TLV: * A_UINT8 data[]; <-- length in byte given by field data_len. */ + /* This structure is used to send information of partner links. + * Following this structure is the TLV: + * wmi_partner_link_stats partner_link_stats[]; + */ + /* This structure is used to send REQ binary blobs of stats of partner + * links from firmware to application/service where Host drv is pass + * through. + * Following this structure is the TLV partner_link_stats: + * A_UINT8 partner_link_stats_data[]; <-- length and offset in byte + * units given by TLV + * wmi_partner_link_stats. + */ } wmi_stats_ext_event_fixed_param; typedef struct { @@ -27795,6 +27842,8 @@ typedef struct { A_UINT32 peer_ps_valid; /* This field indicates the time since target boot-up in MilliSeconds. */ A_UINT32 peer_ps_timestamp; + /* Indicates the vdev id for MLO case */ + wmi_vdev_id_info vdev_id_info; } wmi_peer_sta_ps_statechange_event_fixed_param; /* WMI_PDEV_FIPS_EVENTID */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index ce12b834dc2e..625f1c910241 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1116 +#define __WMI_REVISION_ 1117 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 6a8285ae457387d725359cc6da15689c5ea460d0 Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 15 Feb 2022 06:00:57 -0800 Subject: [PATCH 26/42] fw-api: CL 17233205 - update fw common interface files add WMI_WLM_LL_XR def, deprecate WMI_WLM_LL_MODERATE def Change-Id: I6dfdb5caf428f9536e06a747331dd036fd0e6064 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 3 ++- fw/wmi_version.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 7c0a60999037..0d01e97e9b40 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -31683,7 +31683,8 @@ typedef struct { /* Definition of latency levels */ typedef enum { WMI_WLM_LL_NORMAL = 0x0, - WMI_WLM_LL_MODERATE = 0x1, + /* DEPRECATED */ WMI_WLM_LL_MODERATE = 0x1, + WMI_WLM_LL_XR = 0x1, WMI_WLM_LL_LOW = 0x2, WMI_WLM_LL_ULTRA_LOW = 0x3, } WMI_WLM_LATENCY_LEVEL; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 625f1c910241..1a2ed13a4045 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1117 +#define __WMI_REVISION_ 1118 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 43fb9a75aa82b614a5fc41f89091a9b516de68e2 Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 16 Feb 2022 06:00:56 -0800 Subject: [PATCH 27/42] fw-api: CL 17246272 - update fw common interface files Change-Id: Icb472993edf13e35f339e3f7709de489bc4f3e33 WMI: add service_ids array to NDP_IND event msg CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 3 ++- fw/wmi_unified.h | 4 ++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 0215d20b9d21..e70d4993d384 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -5767,7 +5767,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_NDP_END_RSP_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_cfg, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_app_info, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_scid, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_transport_ip_param, wmi_ndp_transport_ip_param, ndp_transport_ip_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_transport_ip_param, wmi_ndp_transport_ip_param, ndp_transport_ip_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, service_id, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_NDP_INDICATION_EVENTID); /** NDP confirm event diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 0d01e97e9b40..5d2567741fce 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -22995,6 +22995,8 @@ typedef struct { A_UINT32 nan_scid_len; /** Self NDI mac address */ wmi_mac_addr self_ndi_mac_addr; + /** Number of bytes in TLV service_id */ + A_UINT32 service_id_len; /** * TLV (tag length value) parameters follow the ndp_indication * structure. The TLV's are: @@ -23002,6 +23004,8 @@ typedef struct { * A_UINT8 ndp_app_info[]; * A_UINT8 nan_scid[]; * wmi_ndp_transport_ip_param ndp_transport_ip_param; + * A_UINT8 service_id[service_id_len]; <- holds a single service ID of an + * indeterminate number of bytes (most likely 6 bytes) */ } wmi_ndp_indication_event_fixed_param_PROTOTYPE; -- GitLab From ecc219cd2db79461b51837fb9c45e020d28868b7 Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 16 Feb 2022 06:01:28 -0800 Subject: [PATCH 28/42] fw-api: CL 17248910 - update fw common interface files HTT stats: add RU size and EHT sig MCS to tx pdev rate stats TLVs Change-Id: I1c6456592f561122543f4a0ed1d1e024e454ebb2 CRs-Fixed: 2262693 --- fw/htt_stats.h | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/fw/htt_stats.h b/fw/htt_stats.h index 677e12ac8b35..b9a69fd17fa4 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -4149,6 +4149,40 @@ typedef enum { #define HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS 16 /* 0...13,-2,-1 */ #define HTT_TX_PDEV_STATS_NUM_BE_BW_COUNTERS 5 /* 20,40,80,160,320 MHz */ +#define HTT_TX_PDEV_STATS_NUM_HE_SIG_B_MCS_COUNTERS 6 +#define HTT_TX_PDEV_STATS_NUM_EHT_SIG_MCS_COUNTERS 4 + +typedef enum { + HTT_TX_PDEV_STATS_AX_RU_SIZE_26, + HTT_TX_PDEV_STATS_AX_RU_SIZE_52, + HTT_TX_PDEV_STATS_AX_RU_SIZE_106, + HTT_TX_PDEV_STATS_AX_RU_SIZE_242, + HTT_TX_PDEV_STATS_AX_RU_SIZE_484, + HTT_TX_PDEV_STATS_AX_RU_SIZE_996, + HTT_TX_PDEV_STATS_AX_RU_SIZE_996x2, + HTT_TX_PDEV_STATS_NUM_AX_RU_SIZE_COUNTERS, +} HTT_TX_PDEV_STATS_AX_RU_SIZE; + +typedef enum { + HTT_TX_PDEV_STATS_BE_RU_SIZE_26, + HTT_TX_PDEV_STATS_BE_RU_SIZE_52, + HTT_TX_PDEV_STATS_BE_RU_SIZE_52_26, + HTT_TX_PDEV_STATS_BE_RU_SIZE_106, + HTT_TX_PDEV_STATS_BE_RU_SIZE_106_26, + HTT_TX_PDEV_STATS_BE_RU_SIZE_242, + HTT_TX_PDEV_STATS_BE_RU_SIZE_484, + HTT_TX_PDEV_STATS_BE_RU_SIZE_484_242, + HTT_TX_PDEV_STATS_BE_RU_SIZE_996, + HTT_TX_PDEV_STATS_BE_RU_SIZE_996_484, + HTT_TX_PDEV_STATS_BE_RU_SIZE_996_484_242, + HTT_TX_PDEV_STATS_BE_RU_SIZE_996x2, + HTT_TX_PDEV_STATS_BE_RU_SIZE_996x2_484, + HTT_TX_PDEV_STATS_BE_RU_SIZE_996x3, + HTT_TX_PDEV_STATS_BE_RU_SIZE_996x3_484, + HTT_TX_PDEV_STATS_BE_RU_SIZE_996x4, + HTT_TX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS, +} HTT_TX_PDEV_STATS_BE_RU_SIZE; + typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -4271,6 +4305,10 @@ typedef struct { A_UINT32 reduced_ax_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; /** 11AX HE DL MU OFDMA TX BW stats at reduced channel config */ A_UINT32 reduced_ax_mu_ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; + /** 11AX HE DL MU OFDMA TX RU Size stats */ + A_UINT32 ofdma_tx_ru_size[HTT_TX_PDEV_STATS_NUM_AX_RU_SIZE_COUNTERS]; + /** 11AX HE DL MU OFDMA HE-SIG-B MCS stats */ + A_UINT32 ofdma_he_sig_b_mcs[HTT_TX_PDEV_STATS_NUM_HE_SIG_B_MCS_COUNTERS]; } htt_tx_pdev_rate_stats_tlv; typedef struct { @@ -4349,6 +4387,10 @@ typedef struct { A_UINT32 be_ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_BE_BW_COUNTERS]; /** 11BE EHT DL MU OFDMA TX guard interval stats */ A_UINT32 be_ofdma_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; + /** 11BE EHT DL MU OFDMA TX RU Size stats */ + A_UINT32 be_ofdma_tx_ru_size[HTT_TX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS]; + /** 11BE EHT DL MU OFDMA EHT-SIG MCS stats */ + A_UINT32 be_ofdma_eht_sig_mcs[HTT_TX_PDEV_STATS_NUM_EHT_SIG_MCS_COUNTERS]; } htt_tx_pdev_rate_stats_be_ofdma_tlv; /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TX_RATE -- GitLab From 0f8064949c3485b9c8c77c549de123fbda4e4e97 Mon Sep 17 00:00:00 2001 From: Neelansh Mittal Date: Fri, 11 Feb 2022 21:58:51 +0530 Subject: [PATCH 29/42] fw-api: Add missing qcn9224 hdrs Add missing qcn9224 hdrs for PPE Change-Id: Ib70ec456520299bff8179c20611f5fbabf507042 CRs-Fixed: 3129081 --- hw/qcn9224/wcss_seq_hwioreg_umac.h | 200 ++++++++++++++++++++++++++++- 1 file changed, 194 insertions(+), 6 deletions(-) diff --git a/hw/qcn9224/wcss_seq_hwioreg_umac.h b/hw/qcn9224/wcss_seq_hwioreg_umac.h index 6441ff3cd16c..4860d11e746a 100644 --- a/hw/qcn9224/wcss_seq_hwioreg_umac.h +++ b/hw/qcn9224/wcss_seq_hwioreg_umac.h @@ -1,5 +1,5 @@ -/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. +/* Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -16,9 +16,9 @@ #ifndef __WCSS_SEQ_HWIOREG_UMAC_H__ #define __WCSS_SEQ_HWIOREG_UMAC_H__ - - - + + + #include "seq_hwio.h" #include "wcss_seq_hwiobase.h" @@ -12556,7 +12556,7 @@ out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x),m,v,HWIO_REO_R0_C #define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff #define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_SHFT 0 - + #define MAC_TCL_REG_REG_BASE (UMAC_BASE + 0x00044000) #define MAC_TCL_REG_REG_BASE_SIZE 0x3000 #define MAC_TCL_REG_REG_BASE_USED 0x205c @@ -16028,4 +16028,192 @@ out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x),m,v,HWIO_REO_R0_C #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_BMSK 0xffff #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_SHFT 0 -#endif +#define HWIO_TCL_R0_CMN_CONFIG_PPE_ADDR(x) ((x) + 0x28) +#define HWIO_TCL_R0_CMN_CONFIG_PPE_PHYS(x) ((x) + 0x28) +#define HWIO_TCL_R0_CMN_CONFIG_PPE_OFFS (0x28) +#define HWIO_TCL_R0_CMN_CONFIG_PPE_RMSK 0x7fffffff +#define HWIO_TCL_R0_CMN_CONFIG_PPE_POR 0x120c3fe8 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CMN_CONFIG_PPE_ATTR 0x3 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_IN(x) \ + in_dword(HWIO_TCL_R0_CMN_CONFIG_PPE_ADDR(x)) +#define HWIO_TCL_R0_CMN_CONFIG_PPE_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CMN_CONFIG_PPE_ADDR(x), m) +#define HWIO_TCL_R0_CMN_CONFIG_PPE_OUT(x, v) \ + out_dword(HWIO_TCL_R0_CMN_CONFIG_PPE_ADDR(x),v) +#define HWIO_TCL_R0_CMN_CONFIG_PPE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_CMN_CONFIG_PPE_ADDR(x),m,v,HWIO_TCL_R0_CMN_CONFIG_PPE_IN(x)) +#define HWIO_TCL_R0_CMN_CONFIG_PPE_PPE_MAX_DATA_LENGTH_BMSK 0x7ffe0000 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_PPE_MAX_DATA_LENGTH_SHFT 17 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_PPE_MAX_DATA_OFFSET_BMSK 0x1ffe0 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_PPE_MAX_DATA_OFFSET_SHFT 5 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_BMSK 0x10 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_SHFT 4 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_DATA_BUF_ERR_EXCEPTION_BMSK 0x8 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_DATA_BUF_ERR_EXCEPTION_SHFT 3 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK 0x4 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_SHFT 2 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK 0x2 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_SHFT 1 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK 0x1 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_SHFT 0 + +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_ADDR(x) ((x) + 0x190) +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_PHYS(x) ((x) + 0x190) +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_OFFS (0x190) +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_RMSK 0xf +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_POR 0x00000002 +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_ATTR 0x3 +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_IN(x) \ + in_dword(HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_ADDR(x)) +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_ADDR(x), m) +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_ADDR(x),v) +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_ADDR(x),m,v,HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_IN(x)) +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_MSB_BMSK 0xf +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_MSB_SHFT 0 + +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(base,n) ((base) + 0X194 + (0x4*(n))) +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_PHYS(base,n) ((base) + 0X194 + (0x4*(n))) +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_OFFS(n) (0X194 + (0x4*(n))) +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_RMSK 0x3fffffff +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_MAXn 31 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_POR 0x20000000 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ATTR 0x3 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(base,n), HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_RMSK) +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(base,n), mask) +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_OUTI(base,n,val) \ + out_dword(HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(base,n),val) +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(base,n),mask,val,HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_INI(base,n)) +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_DROP_PREC_ENABLE_BMSK 0x20000000 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_DROP_PREC_ENABLE_SHFT 29 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_TO_FW_BMSK 0x10000000 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_TO_FW_SHFT 28 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK 0x8000000 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_SHFT 27 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_SEARCH_INDEX_REG_NUM_BMSK 0x7000000 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_SEARCH_INDEX_REG_NUM_SHFT 24 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VDEV_ID_BMSK 0xff0000 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VDEV_ID_SHFT 16 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_BANK_ID_BMSK 0xfc00 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_BANK_ID_SHFT 10 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_PMAC_ID_BMSK 0x300 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_PMAC_ID_SHFT 8 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VP_NUM_BMSK 0xff +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VP_NUM_SHFT 0 + +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_ADDR(base,n) ((base) + 0X214 + (0x4*(n))) +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_PHYS(base,n) ((base) + 0X214 + (0x4*(n))) +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_OFFS(n) (0X214 + (0x4*(n))) +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_RMSK 0xffffff +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_MAXn 7 +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_POR 0x00000000 +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_ATTR 0x3 +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_ADDR(base,n), HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_RMSK) +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_ADDR(base,n), mask) +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_OUTI(base,n,val) \ + out_dword(HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_ADDR(base,n),val) +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_ADDR(base,n),mask,val,HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_INI(base,n)) +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_CACHE_SET_BMSK 0xf00000 +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_CACHE_SET_SHFT 20 +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_SEARCH_INDEX_BMSK 0xfffff +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_SEARCH_INDEX_SHFT 0 + +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(x) ((x) + 0x234) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_PHYS(x) ((x) + 0x234) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_OFFS (0x234) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_RMSK 0x3fffffff +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_POR 0x00000000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ATTR 0x3 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_IN(x) \ + in_dword(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(x)) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(x), m) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(x),v) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(x),m,v,HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_IN(x)) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_9_BMSK 0x38000000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_9_SHFT 27 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_8_BMSK 0x7000000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_8_SHFT 24 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_7_BMSK 0xe00000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_7_SHFT 21 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_6_BMSK 0x1c0000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_6_SHFT 18 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_5_BMSK 0x38000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_5_SHFT 15 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_4_BMSK 0x7000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_4_SHFT 12 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_3_BMSK 0xe00 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_3_SHFT 9 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_2_BMSK 0x1c0 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_2_SHFT 6 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_1_BMSK 0x38 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_1_SHFT 3 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_BMSK 0x7 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_SHFT 0 + +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(x) ((x) + 0x238) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_PHYS(x) ((x) + 0x238) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_OFFS (0x238) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_RMSK 0x3ffff +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_POR 0x00000000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ATTR 0x3 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_IN(x) \ + in_dword(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(x)) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(x), m) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(x),v) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(x),m,v,HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_IN(x)) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_15_BMSK 0x38000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_15_SHFT 15 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_14_BMSK 0x7000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_14_SHFT 12 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_13_BMSK 0xe00 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_13_SHFT 9 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_12_BMSK 0x1c0 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_12_SHFT 6 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_11_BMSK 0x38 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_11_SHFT 3 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_BMSK 0x7 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_SHFT 0 + +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_ADDR(x) ((x) + 0x23c) +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_PHYS(x) ((x) + 0x23c) +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_OFFS (0x23c) +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_RMSK 0x3f +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_POR 0x00000039 +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_ATTR 0x3 +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_IN(x) \ + in_dword(HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_ADDR(x)) +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_ADDR(x), m) +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_ADDR(x),v) +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_ADDR(x),m,v,HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_IN(x)) +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_RED_2_BMSK 0x30 +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_RED_2_SHFT 4 +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_YELLOW_1_BMSK 0xc +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_YELLOW_1_SHFT 2 +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_GREEN_0_BMSK 0x3 +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_GREEN_0_SHFT 0 + +#endif -- GitLab From ea1999d4038a8f052e9cd0da305684526bd0b523 Mon Sep 17 00:00:00 2001 From: Srinivas Girigowda Date: Wed, 16 Feb 2022 21:22:29 -0800 Subject: [PATCH 30/42] fw-api: Add HWIO_WBM_R0_WBM_CFG_2 related macros Add HWIO_WBM_R0_WBM_CFG_2 related macros. Change-Id: Ia2a2a1c633442167691c4aa568f2c723fdd225be CRs-Fixed: 3132540 --- hw/kiwi/v2/wcss_seq_hwioreg_umac.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/hw/kiwi/v2/wcss_seq_hwioreg_umac.h b/hw/kiwi/v2/wcss_seq_hwioreg_umac.h index 9ce4197c35f7..7c7ebed4f901 100644 --- a/hw/kiwi/v2/wcss_seq_hwioreg_umac.h +++ b/hw/kiwi/v2/wcss_seq_hwioreg_umac.h @@ -190,6 +190,30 @@ #define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff #define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 +#define HWIO_WBM_R0_WBM_CFG_2_ADDR(x) ((x) + 0x90) +#define HWIO_WBM_R0_WBM_CFG_2_PHYS(x) ((x) + 0x90) +#define HWIO_WBM_R0_WBM_CFG_2_OFFS (0x90) +#define HWIO_WBM_R0_WBM_CFG_2_RMSK 0x4b +#define HWIO_WBM_R0_WBM_CFG_2_POR 0x00000040 +#define HWIO_WBM_R0_WBM_CFG_2_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_CFG_2_ATTR 0x3 +#define HWIO_WBM_R0_WBM_CFG_2_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_CFG_2_ADDR(x)) +#define HWIO_WBM_R0_WBM_CFG_2_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_CFG_2_ADDR(x), m) +#define HWIO_WBM_R0_WBM_CFG_2_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_CFG_2_ADDR(x),v) +#define HWIO_WBM_R0_WBM_CFG_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_CFG_2_ADDR(x),m,v,HWIO_WBM_R0_WBM_CFG_2_IN(x)) +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_BMSK 0x40 +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_SHFT 6 +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_CONV_INDICATION_EN_BMSK 0x8 +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_CONV_INDICATION_EN_SHFT 3 +#define HWIO_WBM_R0_WBM_CFG_2_ERROR_PATH_COOKIE_CONV_EN_BMSK 0x2 +#define HWIO_WBM_R0_WBM_CFG_2_ERROR_PATH_COOKIE_CONV_EN_SHFT 1 +#define HWIO_WBM_R0_WBM_CFG_2_RELEASE_PATH_COOKIE_CONV_EN_BMSK 0x1 +#define HWIO_WBM_R0_WBM_CFG_2_RELEASE_PATH_COOKIE_CONV_EN_SHFT 0 + #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x) ((x) + 0x28c) #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT 8 -- GitLab From 7abfbb26977efc99f86140ccc0de5402ac8f5c7e Mon Sep 17 00:00:00 2001 From: Nandha Kishore Easwaran Date: Wed, 2 Feb 2022 12:51:51 +0530 Subject: [PATCH 31/42] fw-api: Add Big endian support in headers Add Big endian support in HW headers for qcn9224 Change-Id: I807a2859ff3019933ad97db79dd9c058ddd545d6 --- hw/qcn9224/rx_mpdu_info.h | 2 +- hw/qcn9224/rx_mpdu_start.h | 2 +- hw/qcn9224/rx_msdu_desc_info.h | 2 +- hw/qcn9224/rx_msdu_end.h | 2 +- hw/qcn9224/rxpt_classify_info.h | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/qcn9224/rx_mpdu_info.h b/hw/qcn9224/rx_mpdu_info.h index 3997d555cfe4..3a21aa299c5b 100644 --- a/hw/qcn9224/rx_mpdu_info.h +++ b/hw/qcn9224/rx_mpdu_info.h @@ -33,7 +33,7 @@ struct rx_mpdu_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN +#ifndef BIG_ENDIAN_HOST struct rxpt_classify_info rxpt_classify_info_details; uint32_t rx_reo_queue_desc_addr_31_0 : 32; uint32_t rx_reo_queue_desc_addr_39_32 : 8, diff --git a/hw/qcn9224/rx_mpdu_start.h b/hw/qcn9224/rx_mpdu_start.h index 812c667da64d..c19311311449 100644 --- a/hw/qcn9224/rx_mpdu_start.h +++ b/hw/qcn9224/rx_mpdu_start.h @@ -35,7 +35,7 @@ struct rx_mpdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN +#ifndef BIG_ENDIAN_HOST struct rx_mpdu_info rx_mpdu_info_details; #else struct rx_mpdu_info rx_mpdu_info_details; diff --git a/hw/qcn9224/rx_msdu_desc_info.h b/hw/qcn9224/rx_msdu_desc_info.h index b982268931a6..2826e5d7558c 100644 --- a/hw/qcn9224/rx_msdu_desc_info.h +++ b/hw/qcn9224/rx_msdu_desc_info.h @@ -32,7 +32,7 @@ struct rx_msdu_desc_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN +#ifndef BIG_ENDIAN_HOST uint32_t first_msdu_in_mpdu_flag : 1, last_msdu_in_mpdu_flag : 1, msdu_continuation : 1, diff --git a/hw/qcn9224/rx_msdu_end.h b/hw/qcn9224/rx_msdu_end.h index 53182070b3fe..418c648ff921 100644 --- a/hw/qcn9224/rx_msdu_end.h +++ b/hw/qcn9224/rx_msdu_end.h @@ -34,7 +34,7 @@ struct rx_msdu_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN +#ifndef BIG_ENDIAN_HOST uint32_t rxpcu_mpdu_filter_in_category : 2, sw_frame_group_id : 7, reserved_0 : 7, diff --git a/hw/qcn9224/rxpt_classify_info.h b/hw/qcn9224/rxpt_classify_info.h index 333ec3a50f7e..e21d907f4ecd 100644 --- a/hw/qcn9224/rxpt_classify_info.h +++ b/hw/qcn9224/rxpt_classify_info.h @@ -32,7 +32,7 @@ struct rxpt_classify_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN +#ifndef BIG_ENDIAN_HOST uint32_t reo_destination_indication : 5, lmac_peer_id_msb : 2, use_flow_id_toeplitz_clfy : 1, -- GitLab From 14bd0d0341893d3b338f978c7a6aa1775274bbd4 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 17 Feb 2022 06:01:02 -0800 Subject: [PATCH 32/42] fw-api: CL 17257656 - update fw common interface files Change-Id: Iecc0926f6acf72b72a0795be02ee3c6cbbe24df5 WMI: add WMI_PDEV_PARAM_SA_PARALLEL_MODE_GPIO_DRIVE_CFG def CRs-Fixed: 2262693 --- fw/wmi_unified.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 5d2567741fce..23e039730557 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -8131,6 +8131,12 @@ typedef enum { /* Param to enable/disable updating scrambler seed feature */ WMI_PDEV_PARAM_EN_UPDATE_SCRAM_SEED, + /* + * Param to set the GPIO Drive Configuration value for + * Smart Antenna Parallel Mode + */ + WMI_PDEV_PARAM_SA_PARALLEL_MODE_GPIO_DRIVE_CFG, + } WMI_PDEV_PARAM; #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1) -- GitLab From 760ab5baffe53d02c853fad44afc5d457d81b8c5 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 17 Feb 2022 18:00:53 -0800 Subject: [PATCH 33/42] fw-api: CL 17259959 - update fw common interface files HTT stats: add more CV counters to tx sounding stats TLV Change-Id: I0b200ed705d5a102a880bf72ecec67c822ff25a9 CRs-Fixed: 2262693 --- fw/htt_stats.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/fw/htt_stats.h b/fw/htt_stats.h index b9a69fd17fa4..2939e38b270d 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -5702,26 +5702,49 @@ typedef struct { A_UINT32 cv_dma_not_done_err; A_UINT32 cv_update_failed; /* cv query stats */ + /** total times CV query happened */ A_UINT32 cv_total_query; + /** total pattern based CV query */ A_UINT32 cv_total_pattern_query; + /** total BW based CV query */ A_UINT32 cv_total_bw_query; + /** incorrect encoding in CV flags */ A_UINT32 cv_invalid_bw_coding; + /** forced sounding enabled for the peer */ A_UINT32 cv_forced_sounding; + /** standalone sounding sequence on-going */ A_UINT32 cv_standalone_sounding; + /** NC of available CV lower than expected */ A_UINT32 cv_nc_mismatch; + /** feedback type different from expected */ A_UINT32 cv_fb_type_mismatch; + /** CV BW not equal to expected BW for OFDMA */ A_UINT32 cv_ofdma_bw_mismatch; + /** CV BW not greater than or equal to expected BW */ A_UINT32 cv_bw_mismatch; + /** CV pattern not matching with the expected pattern */ A_UINT32 cv_pattern_mismatch; + /** CV available is of different preamble type than expected. */ A_UINT32 cv_preamble_mismatch; + /** NR of available CV is lower than expected. */ A_UINT32 cv_nr_mismatch; + /** CV in use count has exceeded threshold and cannot be used further. */ A_UINT32 cv_in_use_cnt_exceeded; + /** A valid CV has been found. */ A_UINT32 cv_found; + /** No valid CV was found. */ A_UINT32 cv_not_found; /** Sounding per user in 320MHz bandwidth */ A_UINT32 sounding_320[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; /** Counts number of soundings for all steering modes in 320MHz bandwidth */ A_UINT32 cbf_320[HTT_TXBF_MAX_NUM_OF_MODES]; + /* This part can be used for new counters added for CV query/upload. */ + /** non-trigger based ranging sequence on-going */ + A_UINT32 cv_ntbr_sounding; + /** CV found, but upload is in progress. */ + A_UINT32 cv_found_upload_in_progress; + /** Expired CV found during query. */ + A_UINT32 cv_expired_during_query; } htt_tx_sounding_stats_tlv; /* STATS_TYPE : HTT_DBG_EXT_STATS_TX_SOUNDING_INFO -- GitLab From 04762423e8d4dc0f45d5f8d5396f442b6f9e408c Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 18 Feb 2022 06:01:02 -0800 Subject: [PATCH 34/42] fw-api: CL 17265976 - update fw common interface files Change-Id: Icd05a861ec537cd805e95af4cd9229af3dc052c1 HTT: reduce rx_mpdu_end_word_mask in rx ring select cfg from 16 -> 3 bits CRs-Fixed: 2262693 --- fw/htt.h | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/fw/htt.h b/fw/htt.h index e07d20c271a5..fd7e3a669408 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -5682,10 +5682,11 @@ enum htt_srng_ring_id { * phyrx_abort_request_reason enum definition. * dword14- b'0:15 - rx_mpdu_start_word_mask: word mask for rx mpdu start, * applicable if word mask enabled - * - b'16:31 - rx_mpdu_end_word_mask: word mask value for rx mpdu end, + * - b'16:18 - rx_mpdu_end_word_mask: word mask value for rx mpdu end, * applicable if word mask enabled + * - b'19:31 - rsvd7 * dword15- b'0:16 - rx_msdu_end_word_mask - b'17:31 - rsvd5 + * - b'17:31 - rsvd5 * dword17- b'0 - en_rx_tlv_pkt_offset: * 0: RX_PKT TLV logging at offset 0 for the subsequent * buffer @@ -5738,7 +5739,8 @@ PREPACK struct htt_rx_ring_selection_cfg_t { A_UINT32 phy_err_mask; A_UINT32 phy_err_mask_cont; A_UINT32 rx_mpdu_start_word_mask:16, - rx_mpdu_end_word_mask: 16; + rx_mpdu_end_word_mask: 3, + rsvd7: 13; A_UINT32 rx_msdu_end_word_mask: 17, rsvd5: 15; A_UINT32 en_rx_tlv_pkt_offset: 1, @@ -6182,15 +6184,15 @@ PREPACK struct htt_rx_ring_selection_cfg_t { ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_S)); \ } while (0) -#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_M 0xFFFF0000 +#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_M 0x00070000 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_S 16 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_GET(_var) \ (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_M)>> \ - HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_S) -#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_SET(_var, _val) \ + HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_S) +#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_SET(_var, _val) \ do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK, _val);\ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_S)); \ + HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK, _val);\ + ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_S)); \ } while (0) #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_M 0x0001FFFF -- GitLab From f482410ea5ca7279a35c48d53a65c8a77435e0d7 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 18 Feb 2022 06:01:45 -0800 Subject: [PATCH 35/42] fw-api: CL 17267055 - update fw common interface files add WMI_SERVICE_REO_QREF_SUPPORT def Change-Id: I705fb9c118bbd490283b37d9fe089e499d67b237 CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + fw/wmi_version.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 5d8de4b99d0b..daa971169584 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -577,6 +577,7 @@ typedef enum { WMI_SERVICE_FP_PHY_ERR_FILTER_SUPPORT = 324, /* FW supports monitor ring configurations for filtering in PHY error packets */ WMI_IS_RADAR_FOUND_CHAN_FREQ_IS_CENTER_FREQ = 325, /* FW Supporting radar event on the actual center frequency radar was detected */ WMI_SERVICE_BIOS_SAR_SUPPORT = 326, /* FW support for SAR parameter stored in BIOS */ + WMI_SERVICE_REO_QREF_SUPPORT = 327, /* FW supports REO QREF */ WMI_MAX_EXT2_SERVICE diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 1a2ed13a4045..b66e11477c6c 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1118 +#define __WMI_REVISION_ 1119 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From b7ad8d9a163ce4fa94ffcc28d76044dcbf5507b0 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 18 Feb 2022 12:01:02 -0800 Subject: [PATCH 36/42] fw-api: CL 17270680 - update fw common interface files Change-Id: Ia268ba67737e6da00734eae663b83d3aff11b5ba WMI: add reg chan priority info in REG_CHAN_LIST_CC_EXT EVENT msg CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 4 +++- fw/wmi_unified.h | 24 ++++++++++++++++++++---- fw/wmi_version.h | 2 +- 3 files changed, 24 insertions(+), 6 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index e70d4993d384..ee42f9a52c47 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1243,6 +1243,7 @@ typedef enum { WMITLV_TAG_STRUC_wmi_tx_send_params_ext, WMITLV_TAG_STRUC_wmi_mgmt_rx_params_ext, WMITLV_TAG_STRUC_wmi_partner_link_stats, + WMITLV_TAG_STRUC_wmi_regulatory_chan_priority_struct, } WMITLV_TAG_ID; /* @@ -6052,7 +6053,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_REG_CHAN_LIST_CC_EVENTID); /* Ext regulatory channel list of current country code */ #define WMITLV_TABLE_WMI_REG_CHAN_LIST_CC_EXT_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_reg_chan_list_cc_event_ext_fixed_param, wmi_reg_chan_list_cc_event_ext_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_regulatory_rule_ext_struct, reg_rule_array, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_regulatory_rule_ext_struct, reg_rule_array, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_regulatory_chan_priority_struct, reg_chan_priority, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_REG_CHAN_LIST_CC_EXT_EVENTID); /* WMI AFC info event */ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 23e039730557..418dc7dc9bab 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -30983,6 +30983,20 @@ typedef struct { */ } wmi_regulatory_rule_ext_struct; +#define WMI_REG_CHAN_PRIORITY_FREQ_GET(freq_info) WMI_GET_BITS(freq_info, 0, 16) +#define WMI_REG_CHAN_PRIORITY_FREQ_SET(freq_info, value) WMI_SET_BITS(freq_info, 0, 16, value) + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_regulatory_chan_priority_struct */ + A_UINT32 freq_info; + /* freq_info: + * bits 15:0 = u16 Cutoff Frequency value for Prioritization (in MHz units) + * The frequencies above this value will be prioritized and + * the frequencies below this value will be de-prioritized. + * bits 31:16 = reserved for future + */ +} wmi_regulatory_chan_priority_struct; + typedef enum { WMI_REG_DFS_UNINIT_REGION = 0, WMI_REG_DFS_FCC_REGION = 1, @@ -31085,10 +31099,12 @@ typedef struct { A_UINT32 num_6g_reg_rules_client_lpi[WMI_REG_CLIENT_MAX]; A_UINT32 num_6g_reg_rules_client_vlp[WMI_REG_CLIENT_MAX]; /* - * This fixed_param TLV is followed by wmi_regulatory_rule_ext struct TLV array. - * Within the reg rule ext TLV array, the 2G elements occur first, - * then the 5G elements, then the 6G elements (AP SG, AP LPI, AP VLP, - * client SP x4, client LPI x4, client vlp x4). + * This fixed_param TLV is followed by the following TLVs: + * - wmi_regulatory_rule_ext reg_rule_array[] struct TLV array. + * Within the reg rule ext TLV array, the 2G elements occur first, + * then the 5G elements, then the 6G elements (AP SG, AP LPI, AP VLP, + * client SP x4, client LPI x4, client vlp x4). + * - wmi_regulatory_chan_priority_struct reg_chan_priority[] */ } wmi_reg_chan_list_cc_event_ext_fixed_param; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index b66e11477c6c..442deb82315d 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1119 +#define __WMI_REVISION_ 1120 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From dc2e78f14a8ea7c818ff6aba4acd32fac1948f03 Mon Sep 17 00:00:00 2001 From: spuligil Date: Sat, 19 Feb 2022 06:00:57 -0800 Subject: [PATCH 37/42] fw-api: CL 17281689 - update fw common interface files HTT stats: add PER stats for 320 MHz BW Change-Id: I0793bbf2297e45248095435a8526861435a3e885 CRs-Fixed: 2262693 --- fw/htt_stats.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/fw/htt_stats.h b/fw/htt_stats.h index 2939e38b270d..96c2818e8d93 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -6179,6 +6179,9 @@ typedef struct { htt_tx_rate_stats_t per_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; + /** 320MHz extension for PER */ + htt_tx_rate_stats_t per_bw320; + } htt_tx_rate_stats_per_tlv; /* NOTE: -- GitLab From 94172670278afc02e1d521a3a1ef3eb69cce121a Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 23 Feb 2022 06:00:50 -0800 Subject: [PATCH 38/42] fw-api: CL 17313419 - update fw common interface files add HTT_TCL_METADATA_VER_SZ def Change-Id: I1838747d15d5510c3d867b9a90a35424204b2df7 CRs-Fixed: 2262693 --- fw/htt.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/fw/htt.h b/fw/htt.h index fd7e3a669408..46ee4f47074f 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -338,6 +338,8 @@ enum HTT_OPTION_TLV_TAGS { HTT_OPTION_TLV_TAG_TCL_METADATA_VER = 0x5, }; +#define HTT_TCL_METADATA_VER_SZ 4 + PREPACK struct htt_option_tlv_header_t { A_UINT8 tag; A_UINT8 length; -- GitLab From 29e67ff2b9d72c6bc035a8077d6bea1cb73da94d Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 23 Feb 2022 18:00:57 -0800 Subject: [PATCH 39/42] fw-api: CL 17323774 - update fw common interface files Change-Id: If5705212bf691ea252986be81707da8df36174f1 HTT: change htt_t2h_sawf_msduq_event.ast_index to 4 bits CRs-Fixed: 2262693 --- fw/htt.h | 56 +++++++++++++++++++++++++++++++++----------------------- 1 file changed, 33 insertions(+), 23 deletions(-) diff --git a/fw/htt.h b/fw/htt.h index 46ee4f47074f..75edcd65816a 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -18092,15 +18092,15 @@ PREPACK struct htt_t2h_sawf_def_queues_map_report_conf { * of the newly created MSDUQ and some other identifiers to uniquely identity * the newly created MSDUQ * - * |31 27| 24|23 16|15 11|10|9 8|7 4|3 0| - * |------------------------------+----------------------+--------------| - * | peer ID | HTT qtype | msg type | - * |--------+---------------------+---------------+--+---+-------+------| - * |reserved| Ast Index |FO|WC | HLOS | remap| - * | | | | | TID | TID | - * |---------------------+----------------------------------------------| - * | reserved1 | tgt_opaque_id | - * |---------------------+----------------------------------------------| + * |31 27| 24|23 16|15|14 11|10|9 8|7 4|3 0| + * |------------------------------+------------------------+--------------| + * | peer ID | HTT qtype | msg type | + * |---------------------------------+--------------+--+---+-------+------| + * | reserved |AST list index|FO|WC | HLOS | remap| + * | | | | | TID | TID | + * |---------------------+------------------------------------------------| + * | reserved1 | tgt_opaque_id | + * |---------------------+------------------------------------------------| * * Header fields: * @@ -18116,10 +18116,20 @@ PREPACK struct htt_t2h_sawf_def_queues_map_report_conf { * TCL Data Command : Beryllium * b10 - flow_override (FO), as sent by host in * TCL Data Command: Beryllium - * b11:26 - ast_index - * Dummy AST Index in case of Lithium, - * Default AST Index in case of Beryllium - * b27:32 - reserved + * b11:14 - ast_list_idx + * Array index into the list of extension AST entries + * (not the actual AST 16-bit index). + * The ast_list_idx is one-based, with the following + * range of values: + * - legacy targets supporting 16 user-defined + * MSDU queues: 1-2 + * - legacy targets supporting 48 user-defined + * MSDU queues: 1-6 + * - new targets: 0 (peer_id is used instead) + * Note that since ast_list_idx is one-based, + * the host will need to subtract 1 to use it as an + * index into a list of extension AST entries. + * b15:31 - reserved * * dword2 - b'23:0 - tgt_opaque_id Opaque Tx flow number which is a * unique MSDUQ id in firmware @@ -18134,8 +18144,8 @@ PREPACK struct htt_t2h_sawf_msduq_event { hlos_tid : 4, who_classify_info_sel : 2, flow_override : 1, - ast_index :16, - reserved : 5; + ast_list_idx : 4, + reserved :17; A_UINT32 tgt_opaque_id :24, reserved1 : 8; @@ -18210,15 +18220,15 @@ PREPACK struct htt_t2h_sawf_msduq_event { ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_S)); \ } while (0) -#define HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_INDEX_M 0x07FFF800 -#define HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_INDEX_S 11 -#define HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_INDEX_GET(_var) \ - (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_INDEX_M) >> \ - HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_INDEX_S) -#define HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_INDEX_SET(_var, _val) \ +#define HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_M 0x00007800 +#define HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_S 11 +#define HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_GET(_var) \ + (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_M) >> \ + HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_S) +#define HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_SET(_var, _val) \ do { \ - HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_INDEX, _val); \ - ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_INDEX_S)); \ + HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX, _val); \ + ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_S)); \ } while (0) -- GitLab From 76832df6c5971c0f9fb1051452ab904ce6991eaa Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 24 Feb 2022 06:00:53 -0800 Subject: [PATCH 40/42] fw-api: CL 17328421 - update fw common interface files Change-Id: I356ee46be03be70f9851e670d012b1fd2be1d16d WMI: add PDEV_RSSI_DBM_CONVERISON_PARAMS_INFO EVENT msg CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 13 +++++++- fw/wmi_unified.h | 85 +++++++++++++++++++++++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 98 insertions(+), 2 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index ee42f9a52c47..beafc6bd462e 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1244,6 +1244,9 @@ typedef enum { WMITLV_TAG_STRUC_wmi_mgmt_rx_params_ext, WMITLV_TAG_STRUC_wmi_partner_link_stats, WMITLV_TAG_STRUC_wmi_regulatory_chan_priority_struct, + WMITLV_TAG_STRUC_wmi_rssi_dbm_conversion_fixed_param, + WMITLV_TAG_STRUC_wmi_rssi_dbm_conversion_params_info, + WMITLV_TAG_STRUC_wmi_rssi_dbm_conversion_temp_offset_info, } WMITLV_TAG_ID; /* @@ -2013,6 +2016,7 @@ typedef enum { OP(WMI_SPECTRAL_CAPABILITIES_EVENTID) \ OP(WMI_RTT_PASN_PEER_CREATE_REQ_EVENTID) \ OP(WMI_RTT_PASN_PEER_DELETE_EVENTID) \ + OP(WMI_PDEV_RSSI_DBM_CONVERSION_PARAMS_INFO_EVENTID) \ /* add new EVT_LIST elements above this line */ @@ -5121,10 +5125,17 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_UPDATE_CTLTABLE_EVENTID); WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_GET_TX_POWER_EVENTID); /* Channel Info Event */ -#define WMITLV_TABLE_WMI_CHAN_INFO_EVENTID(id,op,buf,len) \ +#define WMITLV_TABLE_WMI_CHAN_INFO_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_chan_info_event_fixed_param, wmi_chan_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_CHAN_INFO_EVENTID); +/* RSSI dB to dBm conversion params info event to host */ +#define WMITLV_TABLE_WMI_PDEV_RSSI_DBM_CONVERSION_PARAMS_INFO_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rssi_dbm_conversion_fixed_param, wmi_rssi_dbm_conversion_params_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rssi_dbm_conversion_params_info, rssi_dbm_conversion_params, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rssi_dbm_conversion_temp_offset_info, rssi_temp_offset, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_RSSI_DBM_CONVERSION_PARAMS_INFO_EVENTID); + /* Phy Error Event */ #define WMITLV_TABLE_WMI_PHYERR_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_comb_phyerr_rx_hdr, wmi_comb_phyerr_rx_hdr, hdr, WMITLV_SIZE_FIX) \ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 418dc7dc9bab..b3936bcfb540 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -89,6 +89,8 @@ extern "C" { #define MAX_AOA_PHASEDELTA 31 /* 62 gain values */ +#define MAX_20MHZ_SEGMENTS 16 /* 320 MHz / 20 MHz = 16 (20 MHz subbands) */ + /* The WLAN_MAX_AC macro cannot be changed without breaking WMI compatibility. */ /* The maximum value of access category */ @@ -1599,6 +1601,12 @@ typedef enum { /* Event to send packet log decode information */ WMI_PDEV_PKTLOG_DECODE_INFO_EVENTID, + /** + * RSSI dB to dDm conversion params info event + * sent to host after channel/bw/chainmask change per pdev. + */ + WMI_PDEV_RSSI_DBM_CONVERSION_PARAMS_INFO_EVENTID, + /* VDEV specific events */ /** VDEV started event in response to VDEV_START request */ @@ -16048,6 +16056,83 @@ typedef struct { A_UINT32 per_chain_noise_floor[WMI_MAX_CHAINS]; } wmi_chan_info_event_fixed_param; +/** + * The below three structures are the params used for converting RSSI + * from dB to dBm units. + */ + +typedef struct{ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rssi_dbm_conversion_params_info */ + /* Current operating bandwidth as per wmi_channel_width */ + A_UINT32 curr_bw; + /* Current rx chainmask */ + A_UINT32 curr_rx_chainmask; + /* HW noise floor in dBm per chain, per 20MHz subband */ + A_INT32 nf_hw_dbm[MAX_ANTENNA_EIGHT][MAX_20MHZ_SEGMENTS]; + /* 3 Bytes of xbar_config are used for RF to BB mapping*/ + /* Samples of xbar_config, + * If xbar_config is 0xFAC688(hex): + * RF chains 0-7 are connected to BB chains 0-7 + * here, + * bits 0 to 2 = 0, maps BB chain 0 for RF chain 0 + * bits 3 to 5 = 1, maps BB chain 1 for RF chain 1 + * bits 6 to 8 = 2, maps BB chain 2 for RF chain 2 + * bits 9 to 11 = 3, maps BB chain 3 for RF chain 3 + * bits 12 to 14 = 4, maps BB chain 4 for RF chain 4 + * bits 15 to 17 = 5, maps BB chain 5 for RF chain 5 + * bits 18 to 20 = 6, maps BB chain 6 for RF chain 6 + * bits 21 to 23 = 7, maps BB chain 7 for RF chain 7 + * + * If xbar_config is 0x688FAC(hex): + * RF chains 0-3 are connected to BB chains 4-7 + * RF chains 4-7 are connected to BB chains 0-3 + * here, + * bits 0 to 2 = 4, maps BB chain 4 for RF chain 0 + * bits 3 to 5 = 5, maps BB chain 5 for RF chain 1 + * bits 6 to 8 = 6, maps BB chain 6 for RF chain 2 + * bits 9 to 11 = 7, maps BB chain 7 for RF chain 3 + * bits 12 to 14 = 0, maps BB chain 0 for RF chain 4 + * bits 15 to 17 = 1, maps BB chain 1 for RF chain 5 + * bits 18 to 20 = 2, maps BB chain 2 for RF chain 6 + * bits 21 to 23 = 3, maps BB chain 3 for RF chain 7 + */ + A_UINT32 xbar_config; + /* The below xlna_bypass params needed in old target architecture + * generation, not applicable for current target architecture generation. + * Values will be zero for current target architectures. */ + /* Low noise amplifier bypass offset; signed integer; units are in dB */ + A_INT32 xlna_bypass_offset; + /* Low noise amplifier bypass threshold; signed integer; units are in dB */ + A_INT32 xlna_bypass_threshold; +} wmi_rssi_dbm_conversion_params_info; + +typedef struct{ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rssi_dbm_conversion_temp_offset_info */ + /** + * RSSI offset based on the current temperature, signed integer, + * units are in dB + */ + A_INT32 rssi_temp_offset; +} wmi_rssi_dbm_conversion_temp_offset_info; + +/** + * RSSI dB to dBm conversion params event to host + */ +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rssi_dbm_conversion_fixed_param */ + /* PDEV id */ + A_UINT32 pdev_id; + /** + * Followed by these TLVs below. + * wmi_rssi_dbm_convresion_params_info rssi_dbm_conversion_param[0 or 1] + * wmi_rssi_dbm_conversion_params_info will be sent in case of + * channel, BW, rx_chainmask change. + * wmi_rssi_dbm_conversion_temp_offset_info rssi_temp_offset[0 or 1] + * wmi_rssi_dbm_conversion_temp_offset_info will be sent when the + * RSSI temp offset changes. + */ +} wmi_rssi_dbm_conversion_params_info_event_fixed_param; + /** * Non wlan interference event */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 442deb82315d..72f825ec83d5 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1120 +#define __WMI_REVISION_ 1121 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From f725ae710e51e7a20a1cc05d4ba1001028ba33ab Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 25 Feb 2022 18:00:51 -0800 Subject: [PATCH 41/42] fw-api: CL 17346132 - update fw common interface files Change-Id: Ia91aa849642db109dd21a4d948568ac1ebb8d0d9 WMI: add peer_type_bitmap to vdev_delete_all_peer_cmd CRs-Fixed: 2262693 --- fw/wmi.h | 2 +- fw/wmi_services.h | 1 + fw/wmi_unified.h | 20 ++++++++++++++++++++ fw/wmi_version.h | 2 +- 4 files changed, 23 insertions(+), 2 deletions(-) diff --git a/fw/wmi.h b/fw/wmi.h index 30b01c6857ea..bf99cd6dfd2d 100644 --- a/fw/wmi.h +++ b/fw/wmi.h @@ -145,7 +145,7 @@ typedef enum { GROUP_USAGE = 0x01, TX_USAGE = 0x02, /* default Tx Key - Static WEP only */ PMK_USAGE = 0x04, /* PMK cache */ - PASN_USAGE = 0x08, /* is PASN based key */ + LTF_USAGE = 0x08, /* LTF key seed */ } KEY_USAGE; /* * List of Events (target to host) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index daa971169584..0343c3c9a037 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -578,6 +578,7 @@ typedef enum { WMI_IS_RADAR_FOUND_CHAN_FREQ_IS_CENTER_FREQ = 325, /* FW Supporting radar event on the actual center frequency radar was detected */ WMI_SERVICE_BIOS_SAR_SUPPORT = 326, /* FW support for SAR parameter stored in BIOS */ WMI_SERVICE_REO_QREF_SUPPORT = 327, /* FW supports REO QREF */ + WMI_SERVICE_DELETE_ALL_PEER_BITMAP_SUPPORT = 328, /* target supports cmd to delete all specific peer type within a vdev */ WMI_MAX_EXT2_SERVICE diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index b3936bcfb540..c2c62d1374ef 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -15140,10 +15140,27 @@ typedef struct { wmi_mac_addr peer_macaddr; } wmi_peer_delete_cmd_fixed_param; +#define WMI_VDEV_ALL_PEER_MAX_BITMAP_WORD32 ((WMI_PEER_TYPE_HOST_MAX+31) / 32) + +#define WMI_VDEV_DELETE_ALL_PEER_BITMAP_SET(param, peer_type) \ + WMI_SET_BITS(param[peer_type / 32], (peer_type % 32), 1, 1) + +#define WMI_VDEV_DELETE_ALL_PEER_BITMAP_GET(param, peer_type) \ + WMI_GET_BITS(param[peer_type / 32], (peer_type % 32), 1) + typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_delete_all_peer_cmd_fixed_param */ /** unique id identifying the VDEV, generated by the caller */ A_UINT32 vdev_id; + /** + * Host can request for deletion of peers specific to wmi_peer_type + * through below bitmap. + * Macro's WMI_VDEV_DELETE_ALL_PEER_BITMAP_SET & + * WMI_VDEV_DELETE_ALL_PEER_BITMAP_GET are used for accessing purpose. + * And if bitmap array is filled with zeros, firmware needs to delete + * all peers. + */ + A_UINT32 peer_type_bitmap[WMI_VDEV_ALL_PEER_MAX_BITMAP_WORD32]; } wmi_vdev_delete_all_peer_cmd_fixed_param; typedef struct { @@ -16600,6 +16617,7 @@ enum { WMI_AUTH_FT_RSNA_FILS_SHA384, WMI_AUTH_WPA3_SAE, WMI_AUTH_WPA3_OWE, + WMI_AUTH_PASN, }; typedef enum { @@ -37657,6 +37675,8 @@ typedef struct { wmi_mac_addr peer_mac_addr; /* Return status. 0 for success, non-zero otherwise */ A_UINT32 status; + /* Source address used for doing PASN authentication */ + wmi_mac_addr source_mac_addr; } wmi_rtt_pasn_auth_status_param; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 72f825ec83d5..087f68e5582e 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1121 +#define __WMI_REVISION_ 1122 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 50c4615a8ea84183a645ed8a216993d7fea7ac3a Mon Sep 17 00:00:00 2001 From: spuligil Date: Sat, 26 Feb 2022 18:00:54 -0800 Subject: [PATCH 42/42] fw-api: CL 17350518 - update fw common interface files WMI stats: add AFC STAT Change-Id: I2eb054092fca9070960090626d21ffaeb3ad9aa1 CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 4 +- fw/wmi_unified.h | 139 +++++++++++++++++++++++++++++++++++++++++++++- fw/wmi_version.h | 2 +- 3 files changed, 142 insertions(+), 3 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index beafc6bd462e..ca9d65bccebf 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1247,6 +1247,7 @@ typedef enum { WMITLV_TAG_STRUC_wmi_rssi_dbm_conversion_fixed_param, WMITLV_TAG_STRUC_wmi_rssi_dbm_conversion_params_info, WMITLV_TAG_STRUC_wmi_rssi_dbm_conversion_temp_offset_info, + WMITLV_TAG_STRUC_wmi_ctrl_path_afc_stats_struct, } WMITLV_TAG_ID; /* @@ -6345,7 +6346,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STATS_INFO_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_awgn_stats_struct, ctrl_path_awgn_stats, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_btcoex_stats_struct, ctrl_path_btcoex_stats, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_bmiss_stats_struct, ctrl_path_bmiss_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_odd_addr_read_struct, ctrl_path_odd_addr_read, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_odd_addr_read_struct, ctrl_path_odd_addr_read, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_afc_stats_struct, ctrl_path_afc_stats, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_CTRL_PATH_STATS_EVENTID); #define WMITLV_TABLE_WMI_RADIO_CHAN_STATS_EVENTID(id, op, buf, len) \ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index c2c62d1374ef..4fe182cea1da 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -11149,6 +11149,136 @@ typedef struct { A_UINT32 is_success; } wmi_ctrl_path_odd_addr_read_struct; +/* + * The wmi_ctrl_path_afc_stats_struct is used to send AFC stats within + * the WMI_CTRL_PATH_STATS_EVENT message, in response to a + * WMI_REQUEST_CTRL_PATH_STATS_CMD message for the stat type + * WMI_REQUEST_CTRL_PATH_AFC_STAT. + */ +typedef struct { + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ctrl_path_afc_stats_struct */ + A_UINT32 tlv_header; + + A_UINT32 pdev_id; /* pdev_id for identifying the MAC/PHY */ + + /* Count of new request ID everytime it is generated */ + A_UINT32 request_id_count; + /* Count of total number of AFC payload received */ + A_UINT32 response_count; + /* Count of total number of invalid AFC response */ + A_UINT32 invalid_response_count; + /* Count of total number of AFC resets received */ + A_UINT32 reset_count; + + /* AFC Response error counters*/ + + /* + * Count of total number of incorrect payload received due to + * request ID and response + * Increments when request ID doesn't match with response. + */ + A_UINT32 id_mismatch_count; + + /* + * Count of total number of "local_error_code" success event + * received as part of the AFC response payload in the below struct + * "afc_spectrum_inquiry_resp_bin_type" + */ + A_UINT32 local_err_code_success; + + /* + * Count of total number of "local_error_code" failure event + * received as part of the AFC response payload in the below struct + * "afc_spectrum_inquiry_resp_bin_type" + */ + A_UINT32 local_err_code_failure; + + /* + * The below fields are used to denote the count of + * different server response code received in "afc_serv_resp_code" + * received as part of "afc_spectrum_inquiry_resp_bin_type" + * These resp codes are as per the WFA spec + */ + /* afc_serv_resp_code = version not supported */ + A_UINT32 serv_resp_code_100; + /* afc_serv_resp_code = Device disallowed */ + A_UINT32 serv_resp_code_101; + /* afc_serv_resp_code = Missing param */ + A_UINT32 serv_resp_code_102; + /* afc_serv_resp_code = invalid value */ + A_UINT32 serv_resp_code_103; + /* afc_serv_resp_code = unexpected param */ + A_UINT32 serv_resp_code_106; + /* afc_serv_resp_code = unsupported spectrum */ + A_UINT32 serv_resp_code_300; + + /* + * AFC Compliance tracker + */ + /* proxy_standalone_0 + * This field displays the value of Request ID check disable received + * as part of the INI knob + */ + A_UINT32 proxy_standalone_0; + /* proxy_standalone_1 + * This field displays the value of Timer check disable received + * as part of the INI knob + */ + A_UINT32 proxy_standalone_1; + + /* Count of successful power events sent to host */ + A_UINT32 power_event_counter; + /* Count of total force LPI power mode switch when grace count expires */ + A_UINT32 force_LPI_counter; + + /* + * Count of total number of successful host set + * TPC command received within the compliance timer + */ + A_UINT32 tpc_wmi_success_count; + + /* + * Count of total number of failed host set + * TPC command. This is incremented when compliance timer expires + */ + A_UINT32 tpc_wmi_failure_count; + + /* + * These counters are incremented as part of the + * Regulatory Compliance check done on the AFC payload + * received from server + */ + /* Incorrect PSD value recieved in freq Obj */ + A_UINT32 psd_failure_count; + /* Incorrect End freq recieved in freq Obj */ + A_UINT32 psd_end_freq_failure_count; + /* Incorrect Start freq recieved in freq Obj */ + A_UINT32 psd_start_freq_failure_count; + /* Incorrect EIRP received in channel obj */ + A_UINT32 eirp_failure_count; + /* Incorrect centre freq channel received in channel obj */ + A_UINT32 cfreq_failure_count; + + /* + * AFC Current status + */ + /* Current Request ID */ + A_UINT32 request_id; + /* grace_timer_count + * This grace counter increments only after TTL expiry. + * Cleared to zero once valid payload is received. + */ + A_UINT32 grace_timer_count; + /* Current TTL Time in seconds from last valid payload response */ + A_UINT32 cur_ttl_timer; + /* deployment_mode + * 6G AP deployment mode denoting indoor or outdoor + * Indoor = 1, Outdoor = 2 + */ + A_UINT32 deployment_mode; +} wmi_ctrl_path_afc_stats_struct; + typedef struct { /** TLV tag and len; tag equals * WMITLV_TAG_STRUC_wmi_ctrl_path_stats_event_fixed_param */ @@ -28951,6 +29081,7 @@ typedef enum { WMI_REQUEST_CTRL_PATH_BTCOEX_STAT = 8, WMI_REQUEST_CTRL_PATH_BMISS_STAT = 9, WMI_REQUEST_CTRL_PATH_ODD_ADDR_READ = 10, + WMI_REQUEST_CTRL_PATH_AFC_STAT = 11, } wmi_ctrl_path_stats_id; typedef enum { @@ -30932,7 +31063,13 @@ typedef struct { typedef struct { A_UINT32 channel_cfi; /* channel center frequency index */ - A_UINT32 max_eirp_pwr; /* maximum permissible EIRP available for above CFI in dBm, value is stored in 0.01 dBm steps */ + /* + * maximum permissible EIRP available for above CFI in dBm, + * value is stored in 0.01 dBm steps. + * Note: This A_UINT32 field can receive negative EIRP value from AFC + * server. These negative EIRP value cases are handled internally. + */ + A_UINT32 max_eirp_pwr; } afc_eirp_info; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 087f68e5582e..20fce35cf1d3 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1122 +#define __WMI_REVISION_ 1123 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab