Merge with rsync://rsync.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git (f5d9b97e) · Commits · e / devices / android_kernel_xiaomi_nabu

arch/arm/boot/compressed/head-xscale.S

+7 −0

Original line number	Diff line number	Diff line
		@@ -47,3 +47,10 @@ __XScale_start:
		orr r7, r7, #(MACH_TYPE_GTWX5715 & 0xff00)
		#endif

		#ifdef CONFIG_ARCH_IXP2000
		mov r1, #-1
		mov r0, #0xd6000000
		str r1, [r0, #0x14]
		str r1, [r0, #0x18]
		#endif

arch/arm/kernel/entry-armv.S

+11 −5

Original line number	Diff line number	Diff line
		@@ -269,7 +269,7 @@ __pabt_svc:
		add r5, sp, #S_PC
		ldmia r7, {r2 - r4} @ Get USR pc, cpsr

		#if __LINUX_ARM_ARCH__ < 6
		#if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
		@ make sure our user space atomic helper is aborted
		cmp r2, #VIRT_OFFSET
		bichs r3, r3, #PSR_Z_BIT
		@@ -616,11 +616,17 @@ __kuser_helper_start:

		__kuser_cmpxchg: @ 0xffff0fc0

		#if __LINUX_ARM_ARCH__ < 6
		#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)

		#ifdef CONFIG_SMP /* sanity check */
		#error "CONFIG_SMP on a machine supporting pre-ARMv6 processors?"
		#endif
		/*
		* Poor you. No fast solution possible...
		* The kernel itself must perform the operation.
		* A special ghost syscall is used for that (see traps.c).
		*/
		swi #0x9ffff0
		mov pc, lr

		#elif __LINUX_ARM_ARCH__ < 6

		/*
		* Theory of operation:

arch/arm/kernel/traps.c

+49 −0

Original line number	Diff line number	Diff line
		@@ -464,6 +464,55 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
		#endif
		return 0;

		#ifdef CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG
		/*
		* Atomically store r1 in r2 if r2 is equal to r0 for user space.
		* Return zero in r0 if *MEM was changed or non-zero if no exchange
		* happened. Also set the user C flag accordingly.
		* If access permissions have to be fixed up then non-zero is
		* returned and the operation has to be re-attempted.
		*
		* NOTE: This is a ghost syscall private to the kernel. Only the
		* __kuser_cmpxchg code in entry-armv.S should be aware of its
		* existence. Don't ever use this from user code.
		*/
		case 0xfff0:
		{
		extern void do_DataAbort(unsigned long addr, unsigned int fsr,
		struct pt_regs *regs);
		unsigned long val;
		unsigned long addr = regs->ARM_r2;
		struct mm_struct *mm = current->mm;
		pgd_t pgd; pmd_t pmd; pte_t *pte;

		regs->ARM_cpsr &= ~PSR_C_BIT;
		spin_lock(&mm->page_table_lock);
		pgd = pgd_offset(mm, addr);
		if (!pgd_present(*pgd))
		goto bad_access;
		pmd = pmd_offset(pgd, addr);
		if (!pmd_present(*pmd))
		goto bad_access;
		pte = pte_offset_map(pmd, addr);
		if (!pte_present(pte) \|\| !pte_write(pte))
		goto bad_access;
		val = (unsigned long )addr;
		val -= regs->ARM_r0;
		if (val == 0) {
		(unsigned long )addr = regs->ARM_r1;
		regs->ARM_cpsr \|= PSR_C_BIT;
		}
		spin_unlock(&mm->page_table_lock);
		return val;

		bad_access:
		spin_unlock(&mm->page_table_lock);
		/* simulate a read access fault */
		do_DataAbort(addr, 15 + (1 << 11), regs);
		return -1;
		}
		#endif

		default:
		/* Calls 9f00xx..9f07ff are defined to return -ENOSYS
		if not implemented, rather than raising SIGILL. This

arch/arm/lib/io-writesw-armv4.S

+3 −3

Original line number	Diff line number	Diff line
		@@ -87,9 +87,9 @@ ENTRY(__raw_writesw)
		subs r2, r2, #2
		orr ip, ip, r3, push_hbyte1
		strh ip, [r0]
		bpl 2b
		bpl 1b

		3: tst r2, #1
		2: movne ip, r3, lsr #8
		tst r2, #1
		3: movne ip, r3, lsr #8
		strneh ip, [r0]
		mov pc, lr

arch/arm/mach-pxa/mainstone.c

+9 −0

Original line number	Diff line number	Diff line
		@@ -304,6 +304,15 @@ static void __init mainstone_map_io(void)
		PWER = 0xC0000002;
		PRER = 0x00000002;
		PFER = 0x00000002;
		/* for use I SRAM as framebuffer. */
		PSLR \|= 0xF04;
		PCFR = 0x66;
		/* For Keypad wakeup. */
		KPC &=~KPC_ASACT;
		KPC \|=KPC_AS;
		PKWR = 0x000FD000;
		/* Need read PKWR back after set it. */
		PKWR;
		}

		MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")