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Commit f5ae861d authored by Junaid Shahid's avatar Junaid Shahid Committed by Greg Kroah-Hartman
Browse files

kvm: apic: Flush TLB after APIC mode/address change if VPIDs are in use 



commit a468f2db upstream.

Currently, KVM flushes the TLB after a change to the APIC access page
address or the APIC mode when EPT mode is enabled. However, even in
shadow paging mode, a TLB flush is needed if VPIDs are being used, as
specified in the Intel SDM Section 29.4.5.

So replace vmx_flush_tlb_ept_only() with vmx_flush_tlb(), which will
flush if either EPT or VPIDs are in use.

Signed-off-by: default avatarJunaid Shahid <junaids@google.com>
Reviewed-by: default avatarJim Mattson <jmattson@google.com>
Signed-off-by: default avatarRadim Krčmář <rkrcmar@redhat.com>
Cc: "Jitindar SIngh, Suraj" <surajjs@amazon.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 06006511

arch/x86/kvm/vmx.c

+4 −10
Original line number Diff line number Diff line
@@ -4444,12 +4444,6 @@ static void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa) 
	__vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);

}



static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)

{

	if (enable_ept)

		vmx_flush_tlb(vcpu, true);

}



static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)

{

	ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
@@ -9320,7 +9314,7 @@ static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set) 
	} else {

		sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;

		sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;

		vmx_flush_tlb_ept_only(vcpu);

		vmx_flush_tlb(vcpu, true);

	}

	vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
@@ -9348,7 +9342,7 @@ static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa) 
	    !nested_cpu_has2(get_vmcs12(&vmx->vcpu),

			     SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {

		vmcs_write64(APIC_ACCESS_ADDR, hpa);

		vmx_flush_tlb_ept_only(vcpu);

		vmx_flush_tlb(vcpu, true);

	}

}
@@ -11243,7 +11237,7 @@ static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, 
		}

	} else if (nested_cpu_has2(vmcs12,

				   SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {

		vmx_flush_tlb_ept_only(vcpu);

		vmx_flush_tlb(vcpu, true);

	}



	/*
@@ -12198,7 +12192,7 @@ static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, 
	} else if (!nested_cpu_has_ept(vmcs12) &&

		   nested_cpu_has2(vmcs12,

				   SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {

		vmx_flush_tlb_ept_only(vcpu);

		vmx_flush_tlb(vcpu, true);

	}



	/* This is needed for same reason as it was needed in prepare_vmcs02 */