Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f576fb6a authored by John Crispin's avatar John Crispin Committed by Ralf Baechle
Browse files

MIPS: ralink: cleanup the soc specific pinmux data 



Before we had a pinctrl driver we used a custom OF api. This patch converts the
soc specific pinmux data to a new set of structs. We also add some new pinmux
setings.

Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8009/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 4248f7f1

arch/mips/include/asm/mach-ralink/mt7620.h

+30 −11
Original line number Diff line number Diff line
@@ -82,7 +82,6 @@ 
#define MT7620_DDR2_SIZE_MIN		32

#define MT7620_DDR2_SIZE_MAX		256



#define MT7620_GPIO_MODE_I2C		BIT(0)

#define MT7620_GPIO_MODE_UART0_SHIFT	2

#define MT7620_GPIO_MODE_UART0_MASK	0x7

#define MT7620_GPIO_MODE_UART0(x)	((x) << MT7620_GPIO_MODE_UART0_SHIFT)
@@ -94,16 +93,36 @@ 
#define MT7620_GPIO_MODE_GPIO_UARTF	0x5

#define MT7620_GPIO_MODE_GPIO_I2S	0x6

#define MT7620_GPIO_MODE_GPIO		0x7

#define MT7620_GPIO_MODE_UART1		BIT(5)

#define MT7620_GPIO_MODE_MDIO		BIT(8)

#define MT7620_GPIO_MODE_RGMII1		BIT(9)

#define MT7620_GPIO_MODE_RGMII2		BIT(10)

#define MT7620_GPIO_MODE_SPI		BIT(11)

#define MT7620_GPIO_MODE_SPI_REF_CLK	BIT(12)

#define MT7620_GPIO_MODE_WLED		BIT(13)

#define MT7620_GPIO_MODE_JTAG		BIT(15)

#define MT7620_GPIO_MODE_EPHY		BIT(15)

#define MT7620_GPIO_MODE_WDT		BIT(22)



#define MT7620_GPIO_MODE_NAND		0

#define MT7620_GPIO_MODE_SD		1

#define MT7620_GPIO_MODE_ND_SD_GPIO	2

#define MT7620_GPIO_MODE_ND_SD_MASK	0x3

#define MT7620_GPIO_MODE_ND_SD_SHIFT	18



#define MT7620_GPIO_MODE_PCIE_RST	0

#define MT7620_GPIO_MODE_PCIE_REF	1

#define MT7620_GPIO_MODE_PCIE_GPIO	2

#define MT7620_GPIO_MODE_PCIE_MASK	0x3

#define MT7620_GPIO_MODE_PCIE_SHIFT	16



#define MT7620_GPIO_MODE_WDT_RST	0

#define MT7620_GPIO_MODE_WDT_REF	1

#define MT7620_GPIO_MODE_WDT_GPIO	2

#define MT7620_GPIO_MODE_WDT_MASK	0x3

#define MT7620_GPIO_MODE_WDT_SHIFT	21



#define MT7620_GPIO_MODE_I2C		0

#define MT7620_GPIO_MODE_UART1		5

#define MT7620_GPIO_MODE_MDIO		8

#define MT7620_GPIO_MODE_RGMII1		9

#define MT7620_GPIO_MODE_RGMII2		10

#define MT7620_GPIO_MODE_SPI		11

#define MT7620_GPIO_MODE_SPI_REF_CLK	12

#define MT7620_GPIO_MODE_WLED		13

#define MT7620_GPIO_MODE_JTAG		15

#define MT7620_GPIO_MODE_EPHY		15

#define MT7620_GPIO_MODE_PA		20



static inline int mt7620_get_eco(void)

{

arch/mips/include/asm/mach-ralink/pinmux.h

0 → 100644
+55 −0
Original line number Diff line number Diff line 
/*

 *  This program is free software; you can redistribute it and/or modify

 *  it under the terms of the GNU General Public License version 2 as

 *  publishhed by the Free Software Foundation.

 *

 *  Copyright (C) 2012 John Crispin <blogic@openwrt.org>

 */



#ifndef _RT288X_PINMUX_H__

#define _RT288X_PINMUX_H__



#define FUNC(name, value, pin_first, pin_count) \

	{ name, value, pin_first, pin_count }



#define GRP(_name, _func, _mask, _shift) \

	{ .name = _name, .mask = _mask, .shift = _shift, \

	  .func = _func, .gpio = _mask, \

	  .func_count = ARRAY_SIZE(_func) }



#define GRP_G(_name, _func, _mask, _gpio, _shift) \

	{ .name = _name, .mask = _mask, .shift = _shift, \

	  .func = _func, .gpio = _gpio, \

	  .func_count = ARRAY_SIZE(_func) }



struct rt2880_pmx_group;



struct rt2880_pmx_func {

	const char *name;

	const char value;



	int pin_first;

	int pin_count;

	int *pins;



	int *groups;

	int group_count;



	int enabled;

};



struct rt2880_pmx_group {

	const char *name;

	int enabled;



	const u32 shift;

	const char mask;

	const char gpio;



	struct rt2880_pmx_func *func;

	int func_count;

};



extern struct rt2880_pmx_group *rt2880_pinmux_data;



#endif

arch/mips/include/asm/mach-ralink/rt305x.h

+20 −15
Original line number Diff line number Diff line
@@ -125,24 +125,29 @@ static inline int soc_is_rt5350(void) 
#define RT305X_GPIO_GE0_TXD0		40

#define RT305X_GPIO_GE0_RXCLK		51



#define RT305X_GPIO_MODE_I2C		BIT(0)

#define RT305X_GPIO_MODE_SPI		BIT(1)

#define RT305X_GPIO_MODE_UART0_SHIFT	2

#define RT305X_GPIO_MODE_UART0_MASK	0x7

#define RT305X_GPIO_MODE_UART0(x)	((x) << RT305X_GPIO_MODE_UART0_SHIFT)

#define RT305X_GPIO_MODE_UARTF		0x0

#define RT305X_GPIO_MODE_PCM_UARTF	0x1

#define RT305X_GPIO_MODE_PCM_I2S	0x2

#define RT305X_GPIO_MODE_I2S_UARTF	0x3

#define RT305X_GPIO_MODE_PCM_GPIO	0x4

#define RT305X_GPIO_MODE_GPIO_UARTF	0x5

#define RT305X_GPIO_MODE_GPIO_I2S	0x6

#define RT305X_GPIO_MODE_GPIO		0x7

#define RT305X_GPIO_MODE_UART1		BIT(5)

#define RT305X_GPIO_MODE_JTAG		BIT(6)

#define RT305X_GPIO_MODE_MDIO		BIT(7)

#define RT305X_GPIO_MODE_SDRAM		BIT(8)

#define RT305X_GPIO_MODE_RGMII		BIT(9)

#define RT305X_GPIO_MODE_UARTF		0

#define RT305X_GPIO_MODE_PCM_UARTF	1

#define RT305X_GPIO_MODE_PCM_I2S	2

#define RT305X_GPIO_MODE_I2S_UARTF	3

#define RT305X_GPIO_MODE_PCM_GPIO	4

#define RT305X_GPIO_MODE_GPIO_UARTF	5

#define RT305X_GPIO_MODE_GPIO_I2S	6

#define RT305X_GPIO_MODE_GPIO		7



#define RT305X_GPIO_MODE_I2C		0

#define RT305X_GPIO_MODE_SPI		1

#define RT305X_GPIO_MODE_UART1		5

#define RT305X_GPIO_MODE_JTAG		6

#define RT305X_GPIO_MODE_MDIO		7

#define RT305X_GPIO_MODE_SDRAM		8

#define RT305X_GPIO_MODE_RGMII		9

#define RT5350_GPIO_MODE_PHY_LED	14

#define RT5350_GPIO_MODE_SPI_CS1	21

#define RT3352_GPIO_MODE_LNA		18

#define RT3352_GPIO_MODE_PA		20



#define RT3352_SYSC_REG_SYSCFG0		0x010

#define RT3352_SYSC_REG_SYSCFG1         0x014

arch/mips/include/asm/mach-ralink/rt3883.h

+9 −7
Original line number Diff line number Diff line
@@ -112,8 +112,6 @@ 
#define RT3883_CLKCFG1_PCI_CLK_EN	BIT(19)

#define RT3883_CLKCFG1_UPHY0_CLK_EN	BIT(18)



#define RT3883_GPIO_MODE_I2C		BIT(0)

#define RT3883_GPIO_MODE_SPI		BIT(1)

#define RT3883_GPIO_MODE_UART0_SHIFT	2

#define RT3883_GPIO_MODE_UART0_MASK	0x7

#define RT3883_GPIO_MODE_UART0(x)	((x) << RT3883_GPIO_MODE_UART0_SHIFT)
@@ -125,11 +123,15 @@ 
#define RT3883_GPIO_MODE_GPIO_UARTF	0x5

#define RT3883_GPIO_MODE_GPIO_I2S	0x6

#define RT3883_GPIO_MODE_GPIO		0x7

#define RT3883_GPIO_MODE_UART1		BIT(5)

#define RT3883_GPIO_MODE_JTAG		BIT(6)

#define RT3883_GPIO_MODE_MDIO		BIT(7)

#define RT3883_GPIO_MODE_GE1		BIT(9)

#define RT3883_GPIO_MODE_GE2		BIT(10)



#define RT3883_GPIO_MODE_I2C		0

#define RT3883_GPIO_MODE_SPI		1

#define RT3883_GPIO_MODE_UART1		5

#define RT3883_GPIO_MODE_JTAG		6

#define RT3883_GPIO_MODE_MDIO		7

#define RT3883_GPIO_MODE_GE1		9

#define RT3883_GPIO_MODE_GE2		10



#define RT3883_GPIO_MODE_PCI_SHIFT	11

#define RT3883_GPIO_MODE_PCI_MASK	0x7

#define RT3883_GPIO_MODE_PCI		(RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)

arch/mips/ralink/common.h

+0 −19
Original line number Diff line number Diff line
@@ -11,25 +11,6 @@ 


#define RAMIPS_SYS_TYPE_LEN	32



struct ralink_pinmux_grp {

	const char *name;

	u32 mask;

	int gpio_first;

	int gpio_last;

};



struct ralink_pinmux {

	struct ralink_pinmux_grp *mode;

	struct ralink_pinmux_grp *uart;

	int uart_shift;

	u32 uart_mask;

	void (*wdt_reset)(void);

	struct ralink_pinmux_grp *pci;

	int pci_shift;

	u32 pci_mask;

};

extern struct ralink_pinmux rt_gpio_pinmux;



struct ralink_soc_info {

	unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];

	unsigned char *compatible;