Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f4696752 authored by Alexander Shiyan's avatar Alexander Shiyan Committed by Shawn Guo
Browse files

ARM: i.MX: Use of_clk_get_by_name() for timer clocks for DT case. 



Use of_clk_get_by_name() for timer clocks for DT case.
This patch eliminates a lot of unneeded clk_register_clkdev()
calls for GPT.

Signed-off-by: default avatarAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: default avatarShawn Guo <shawn.guo@freescale.com>
parent 186d28c1

arch/arm/mach-imx/clk-imx1.c

+2 −3
Original line number Diff line number Diff line
@@ -76,9 +76,6 @@ static void __init _mx1_clocks_init(unsigned long fref) 
		if (IS_ERR(clk[i]))

			pr_err("imx1 clk %d: register failed with %ld\n",

				i, PTR_ERR(clk[i]));



	clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx-gpt.0");

	clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx-gpt.0");

}



int __init mx1_clocks_init(unsigned long fref)
@@ -87,6 +84,8 @@ int __init mx1_clocks_init(unsigned long fref) 


	_mx1_clocks_init(fref);



	clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx-gpt.0");

	clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx-gpt.0");

	clk_register_clkdev(clk[IMX1_CLK_DMA_GATE], "ahb", "imx1-dma");

	clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-dma");

	clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.0");

arch/arm/mach-imx/clk-imx25.c

+2 −3
Original line number Diff line number Diff line
@@ -234,9 +234,6 @@ static int __init __mx25_clocks_init(unsigned long osc_rate) 
	/* Clock source for gpt must be derived from AHB */

	clk_set_parent(clk[per5_sel], clk[ahb]);



	clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");

	clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");



	/*

	 * Let's initially set up CLKO parent as ipg, since this configuration

	 * is used on some imx25 board designs to clock the audio codec.
@@ -250,6 +247,8 @@ int __init mx25_clocks_init(void) 
{

	__mx25_clocks_init(24000000);



	clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");

	clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");

	/* i.mx25 has the i.mx21 type uart */

	clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0");

	clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0");

arch/arm/mach-imx/clk-imx51-imx53.c

+0 −2
Original line number Diff line number Diff line
@@ -292,8 +292,6 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base) 
			pr_err("i.MX5 clk %d: register failed with %ld\n",

				i, PTR_ERR(clk[i]));



	clk_register_clkdev(clk[IMX5_CLK_GPT_HF_GATE], "per", "imx-gpt.0");

	clk_register_clkdev(clk[IMX5_CLK_GPT_IPG_GATE], "ipg", "imx-gpt.0");

	clk_register_clkdev(clk[IMX5_CLK_UART1_PER_GATE], "per", "imx21-uart.0");

	clk_register_clkdev(clk[IMX5_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");

	clk_register_clkdev(clk[IMX5_CLK_UART2_PER_GATE], "per", "imx21-uart.1");

arch/arm/mach-imx/clk-imx6q.c

+0 −2
Original line number Diff line number Diff line
@@ -442,8 +442,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) 
	clk_data.clk_num = ARRAY_SIZE(clk);

	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);



	clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");

	clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");

	clk_register_clkdev(clk[enet_ref], "enet_ref", NULL);



	if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||

arch/arm/mach-imx/clk-imx6sl.c

+0 −3
Original line number Diff line number Diff line
@@ -357,9 +357,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) 
	clk_data.clk_num = ARRAY_SIZE(clks);

	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);



	clk_register_clkdev(clks[IMX6SL_CLK_GPT], "ipg", "imx-gpt.0");

	clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0");



	/* Ensure the AHB clk is at 132MHz. */

	ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000);

	if (ret)