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Commit f3f1f03e authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: DCE6 disp eng pll updates 



Rename the function to better match the functionality.
DCPLL became PLL0 on DCE6.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent fef9f91f

drivers/gpu/drm/radeon/atombios_crtc.c

+10 −5
Original line number Diff line number Diff line
@@ -737,7 +737,7 @@ union set_pixel_clock { 
/* on DCE5, make sure the voltage is high enough to support the

 * required disp clk.

 */

static void atombios_crtc_set_dcpll(struct radeon_device *rdev,

static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,

				    u32 dispclk)

{

	u8 frev, crev;
@@ -767,6 +767,9 @@ static void atombios_crtc_set_dcpll(struct radeon_device *rdev, 
			 * SetPixelClock provides the dividers

			 */

			args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);

			if (ASIC_IS_DCE6(rdev))

				args.v6.ucPpll = ATOM_PPLL0;

			else

				args.v6.ucPpll = ATOM_DCPLL;

			break;

		default:
@@ -1521,10 +1524,12 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) 


}



void radeon_atom_dcpll_init(struct radeon_device *rdev)

void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)

{

	/* always set DCPLL */

	if (ASIC_IS_DCE4(rdev)) {

	if (ASIC_IS_DCE6(rdev))

		atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);

	else if (ASIC_IS_DCE4(rdev)) {

		struct radeon_atom_ss ss;

		bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,

								   ASIC_INTERNAL_SS_ON_DCPLL,
@@ -1532,7 +1537,7 @@ void radeon_atom_dcpll_init(struct radeon_device *rdev) 
		if (ss_enabled)

			atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, &ss);

		/* XXX: DCE5, make sure voltage, dispclk is high enough */

		atombios_crtc_set_dcpll(rdev, rdev->clock.default_dispclk);

		atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);

		if (ss_enabled)

			atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, &ss);

	}

drivers/gpu/drm/radeon/radeon_device.c

+1 −1
Original line number Diff line number Diff line
@@ -967,7 +967,7 @@ int radeon_resume_kms(struct drm_device *dev) 
	/* init dig PHYs, disp eng pll */

	if (rdev->is_atom_bios) {

		radeon_atom_encoder_init(rdev);

		radeon_atom_dcpll_init(rdev);

		radeon_atom_disp_eng_pll_init(rdev);

	}

	/* reset hpd state */

	radeon_hpd_init(rdev);

drivers/gpu/drm/radeon/radeon_display.c

+1 −1
Original line number Diff line number Diff line
@@ -1296,7 +1296,7 @@ int radeon_modeset_init(struct radeon_device *rdev) 
	/* init dig PHYs, disp eng pll */

	if (rdev->is_atom_bios) {

		radeon_atom_encoder_init(rdev);

		radeon_atom_dcpll_init(rdev);

		radeon_atom_disp_eng_pll_init(rdev);

	}



	/* initialize hpd */

drivers/gpu/drm/radeon/radeon_mode.h

+1 −1
Original line number Diff line number Diff line
@@ -491,7 +491,7 @@ extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 
				    struct drm_connector *connector);

extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);

extern void radeon_atom_encoder_init(struct radeon_device *rdev);

extern void radeon_atom_dcpll_init(struct radeon_device *rdev);

extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);

extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,

					   int action, uint8_t lane_num,

					   uint8_t lane_set);