Commit f3d795d9 authored Jan 19, 2018 by Jayachandran C Committed by Catalin Marinas Jan 23, 2018

arm64: Branch predictor hardening for Cavium ThunderX2



Use PSCI based mitigation for speculative execution attacks targeting
the branch predictor. We use the same mechanism as the one used for
Cortex-A CPUs, we expect the PSCI version call to have a side effect
of clearing the BTBs.

Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Jayachandran C <jnair@caviumnetworks.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

parent 55b35d07

arch/arm64/kernel/cpu_errata.c

+10 −0

Original line number	Diff line number	Diff line
		@@ -359,6 +359,16 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
		.capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
		MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
		},
		{
		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
		MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
		.enable = enable_psci_bp_hardening,
		},
		{
		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
		MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
		.enable = enable_psci_bp_hardening,
		},
		#endif
		{
		}