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Commit f35f5a99 authored by Will Deacon's avatar Will Deacon Committed by Greg Kroah-Hartman
Browse files

arm64: kpti: Whitelist Cortex-A CPUs that don't implement the CSV3 field 



commit 2a355ec25729053bb9a1a89b6c1d1cdd6c3b3fb1 upstream.

While the CSV3 field of the ID_AA64_PFR0 CPU ID register can be checked
to see if a CPU is susceptible to Meltdown and therefore requires kpti
to be enabled, existing CPUs do not implement this field.

We therefore whitelist all unaffected Cortex-A CPUs that do not implement
the CSV3 field.

Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Cc: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent c0ccb4da

arch/arm64/kernel/cpufeature.c

+6 −0
Original line number Diff line number Diff line
@@ -895,6 +895,12 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 
	static const struct midr_range kpti_safe_list[] = {

		MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),

		MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),

		MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),

		MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),

		MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),

		MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),

		MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),

		MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),

		{ /* sentinel */ }

	};

	char const *str = "command line option";