[POWERPC] 8xx: powerpc port of core CPM PIC

ifeq ($(ARCH),powerpc)

obj-$(CONFIG_MTD)		+= rom.o

obj-$(CONFIG_CPM2)		+= cpm2_common.o cpm2_pic.o

obj-$(CONFIG_8xx)		+= mpc8xx_pic.o commproc.o

obj-$(CONFIG_UCODE_PATCH)	+= micropatch.o

endif

/*

 * General Purpose functions for the global management of the

 * Communication Processor Module.

 * Copyright (c) 1997 Dan error_act (dmalek@jlc.net)

 *

 * In addition to the individual control of the communication

 * channels, there are a few functions that globally affect the

 * communication processor.

 *

 * Buffer descriptors must be allocated from the dual ported memory

 * space.  The allocator for that is here.  When the communication

 * process is reset, we reclaim the memory available.  There is

 * currently no deallocator for this memory.

 * The amount of space available is platform dependent.  On the

 * MBX, the EPPC software loads additional microcode into the

 * communication processor, and uses some of the DP ram for this

 * purpose.  Current, the first 512 bytes and the last 256 bytes of

 * memory are used.  Right now I am conservative and only use the

 * memory that can never be used for microcode.  If there are

 * applications that require more DP ram, we can expand the boundaries

 * but then we have to be careful of any downloaded microcode.

 */

#include <linux/errno.h>

#include <linux/sched.h>

#include <linux/kernel.h>

#include <linux/dma-mapping.h>

#include <linux/param.h>

#include <linux/string.h>

#include <linux/mm.h>

#include <linux/interrupt.h>

#include <linux/irq.h>

#include <linux/module.h>

#include <asm/mpc8xx.h>

#include <asm/page.h>

#include <asm/pgtable.h>

#include <asm/8xx_immap.h>

#include <asm/commproc.h>

#include <asm/io.h>

#include <asm/tlbflush.h>

#include <asm/rheap.h>

#include <asm/prom.h>

#include <asm/fs_pd.h>

#define CPM_MAP_SIZE    (0x4000)

static void m8xx_cpm_dpinit(void);

static	uint	host_buffer;	/* One page of host buffer */

static	uint	host_end;	/* end + 1 */

cpm8xx_t	*cpmp;		/* Pointer to comm processor space */

cpic8xx_t	*cpic_reg;

static struct device_node *cpm_pic_node;

static struct irq_host *cpm_pic_host;

static void cpm_mask_irq(unsigned int irq)

{

	unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;

	clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));

}

static void cpm_unmask_irq(unsigned int irq)

{

	unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;

	setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));

}

static void cpm_end_irq(unsigned int irq)

{

	unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;

	out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec));

}

static struct irq_chip cpm_pic = {

	.typename = " CPM PIC ",

	.mask = cpm_mask_irq,

	.unmask = cpm_unmask_irq,

	.eoi = cpm_end_irq,

};

int cpm_get_irq(void)

{

	int cpm_vec;

	/* Get the vector by setting the ACK bit and then reading

	 * the register.

	 */

	out_be16(&cpic_reg->cpic_civr, 1);

	cpm_vec = in_be16(&cpic_reg->cpic_civr);

	cpm_vec >>= 11;

	return irq_linear_revmap(cpm_pic_host, cpm_vec);

}

static int cpm_pic_host_match(struct irq_host *h, struct device_node *node)

{

	return cpm_pic_node == node;

}

static int cpm_pic_host_map(struct irq_host *h, unsigned int virq,

			  irq_hw_number_t hw)

{

	pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw);

	get_irq_desc(virq)->status |= IRQ_LEVEL;

	set_irq_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);

	return 0;

}

/* The CPM can generate the error interrupt when there is a race condition

 * between generating and masking interrupts.  All we have to do is ACK it

 * and return.  This is a no-op function so we don't need any special

 * tests in the interrupt handler.

 */

static	irqreturn_t cpm_error_interrupt(int irq, void *dev)

{

	return IRQ_HANDLED;

}

static struct irqaction cpm_error_irqaction = {

	.handler = cpm_error_interrupt,

	.mask = CPU_MASK_NONE,

	.name = "error",

};

static struct irq_host_ops cpm_pic_host_ops = {

	.match = cpm_pic_host_match,

	.map = cpm_pic_host_map,

};

unsigned int cpm_pic_init(void)

{

	struct device_node *np = NULL;

	struct resource res;

	unsigned int sirq = NO_IRQ, hwirq, eirq;

	int ret;

	pr_debug("cpm_pic_init\n");

	np = of_find_compatible_node(NULL, "cpm-pic", "CPM");

	if (np == NULL) {

		printk(KERN_ERR "CPM PIC init: can not find cpm-pic node\n");

		return sirq;

	}

	ret = of_address_to_resource(np, 0, &res);

	if (ret)

		goto end;

	cpic_reg = (void *)ioremap(res.start, res.end - res.start + 1);

	if (cpic_reg == NULL)

		goto end;

	sirq = irq_of_parse_and_map(np, 0);

	if (sirq == NO_IRQ)

		goto end;

	/* Initialize the CPM interrupt controller. */

	hwirq = (unsigned int)irq_map[sirq].hwirq;

	out_be32(&cpic_reg->cpic_cicr,

	    (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |

		((hwirq/2) << 13) | CICR_HP_MASK);

	out_be32(&cpic_reg->cpic_cimr, 0);

	cpm_pic_node = of_node_get(np);

	cpm_pic_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, 64, &cpm_pic_host_ops, 64);

	if (cpm_pic_host == NULL) {

		printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");

		sirq = NO_IRQ;

		goto end;

	}

	of_node_put(np);

	/* Install our own error handler. */

	np = of_find_node_by_type(NULL, "cpm");

	if (np == NULL) {

		printk(KERN_ERR "CPM PIC init: can not find cpm node\n");

		goto end;

	}

	eirq= irq_of_parse_and_map(np, 0);

	if (eirq == NO_IRQ)

		goto end;

	if (setup_irq(eirq, &cpm_error_irqaction))

		printk(KERN_ERR "Could not allocate CPM error IRQ!");

	setbits32(&cpic_reg->cpic_cicr, CICR_IEN);

end:

	of_node_put(np);

	return sirq;

}

void cpm_reset(void)

{

	cpm8xx_t	*commproc;

	sysconf8xx_t    *siu_conf;

	commproc = (cpm8xx_t *)ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);

#ifdef CONFIG_UCODE_PATCH

	/* Perform a reset.

	*/

	out_be16(&commproc->cp_cpcr,  CPM_CR_RST | CPM_CR_FLG);

	/* Wait for it.

	*/

	while (in_be16(&commproc->cp_cpcr) & CPM_CR_FLG);

	cpm_load_patch(commproc);

#endif

	/* Set SDMA Bus Request priority 5.

	 * On 860T, this also enables FEC priority 6.  I am not sure

	 * this is what we realy want for some applications, but the

	 * manual recommends it.

	 * Bit 25, FAM can also be set to use FEC aggressive mode (860T).

	 */

	siu_conf = (sysconf8xx_t*)immr_map(im_siu_conf);

	out_be32(&siu_conf->sc_sdcr, 1);

	immr_unmap(siu_conf);

	/* Reclaim the DP memory for our use. */

	m8xx_cpm_dpinit();

	/* Tell everyone where the comm processor resides.

	*/

	cpmp = commproc;

}

/* We used to do this earlier, but have to postpone as long as possible

 * to ensure the kernel VM is now running.

 */

static void

alloc_host_memory(void)

{

	dma_addr_t	physaddr;

	/* Set the host page for allocation.

	*/

	host_buffer = (uint)dma_alloc_coherent(NULL, PAGE_SIZE, &physaddr,

			GFP_KERNEL);

	host_end = host_buffer + PAGE_SIZE;

}

/* We also own one page of host buffer space for the allocation of

 * UART "fifos" and the like.

 */

uint

m8xx_cpm_hostalloc(uint size)

{

	uint	retloc;

	if (host_buffer == 0)

		alloc_host_memory();

	if ((host_buffer + size) >= host_end)

		return(0);

	retloc = host_buffer;

	host_buffer += size;

	return(retloc);

}

/* Set a baud rate generator.  This needs lots of work.  There are

 * four BRGs, any of which can be wired to any channel.

 * The internal baud rate clock is the system clock divided by 16.

 * This assumes the baudrate is 16x oversampled by the uart.

 */

#define BRG_INT_CLK		(get_brgfreq())

#define BRG_UART_CLK		(BRG_INT_CLK/16)

#define BRG_UART_CLK_DIV16	(BRG_UART_CLK/16)

void

cpm_setbrg(uint brg, uint rate)

{

	volatile uint	*bp;

	/* This is good enough to get SMCs running.....

	*/

	bp = (uint *)&cpmp->cp_brgc1;

	bp += brg;

	/* The BRG has a 12-bit counter.  For really slow baud rates (or

	 * really fast processors), we may have to further divide by 16.

	 */

	if (((BRG_UART_CLK / rate) - 1) < 4096)

		*bp = (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN;

	else

		*bp = (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) |

						CPM_BRG_EN | CPM_BRG_DIV16;

}

/*

 * dpalloc / dpfree bits.

 */

static spinlock_t cpm_dpmem_lock;

/*

 * 16 blocks should be enough to satisfy all requests

 * until the memory subsystem goes up...

 */

static rh_block_t cpm_boot_dpmem_rh_block[16];

static rh_info_t cpm_dpmem_info;

#define CPM_DPMEM_ALIGNMENT	8

static u8* dpram_vbase;

static uint dpram_pbase;

void m8xx_cpm_dpinit(void)

{

	spin_lock_init(&cpm_dpmem_lock);

	dpram_vbase = immr_map_size(im_cpm.cp_dpmem, CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE);

	dpram_pbase = (uint)&((immap_t *)IMAP_ADDR)->im_cpm.cp_dpmem;

	/* Initialize the info header */

	rh_init(&cpm_dpmem_info, CPM_DPMEM_ALIGNMENT,

			sizeof(cpm_boot_dpmem_rh_block) /

			sizeof(cpm_boot_dpmem_rh_block[0]),

			cpm_boot_dpmem_rh_block);

	/*

	 * Attach the usable dpmem area.

	 * XXX: This is actually crap.  CPM_DATAONLY_BASE and

	 * CPM_DATAONLY_SIZE are a subset of the available dparm.  It varies

	 * with the processor and the microcode patches applied / activated.

	 * But the following should be at least safe.

	 */

	rh_attach_region(&cpm_dpmem_info, (void *)CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE);

}

/*

 * Allocate the requested size worth of DP memory.

 * This function returns an offset into the DPRAM area.

 * Use cpm_dpram_addr() to get the virtual address of the area.

 */

uint cpm_dpalloc(uint size, uint align)

{

	void *start;

	unsigned long flags;

	spin_lock_irqsave(&cpm_dpmem_lock, flags);

	cpm_dpmem_info.alignment = align;

	start = rh_alloc(&cpm_dpmem_info, size, "commproc");

	spin_unlock_irqrestore(&cpm_dpmem_lock, flags);

	return (uint)start;

}

EXPORT_SYMBOL(cpm_dpalloc);

int cpm_dpfree(uint offset)

{

	int ret;

	unsigned long flags;

	spin_lock_irqsave(&cpm_dpmem_lock, flags);

	ret = rh_free(&cpm_dpmem_info, (void *)offset);

	spin_unlock_irqrestore(&cpm_dpmem_lock, flags);

	return ret;

}

EXPORT_SYMBOL(cpm_dpfree);

uint cpm_dpalloc_fixed(uint offset, uint size, uint align)

{

	void *start;

	unsigned long flags;

	spin_lock_irqsave(&cpm_dpmem_lock, flags);

	cpm_dpmem_info.alignment = align;

	start = rh_alloc_fixed(&cpm_dpmem_info, (void *)offset, size, "commproc");

	spin_unlock_irqrestore(&cpm_dpmem_lock, flags);

	return (uint)start;

}

EXPORT_SYMBOL(cpm_dpalloc_fixed);

void cpm_dpdump(void)

{

	rh_dump(&cpm_dpmem_info);

}

EXPORT_SYMBOL(cpm_dpdump);

void *cpm_dpram_addr(uint offset)

{

	return (void *)(dpram_vbase + offset);

}

EXPORT_SYMBOL(cpm_dpram_addr);

uint cpm_dpram_phys(u8* addr)

{

	return (dpram_pbase + (uint)(addr - dpram_vbase));

}

EXPORT_SYMBOL(cpm_dpram_addr);

/* Microcode patches for the CPM as supplied by Motorola.

 * This is the one for IIC/SPI.  There is a newer one that

 * also relocates SMC2, but this would require additional changes

 * to uart.c, so I am holding off on that for a moment.

 */

#include <linux/errno.h>

#include <linux/sched.h>

#include <linux/kernel.h>

#include <linux/param.h>

#include <linux/string.h>

#include <linux/mm.h>

#include <linux/interrupt.h>

#include <asm/irq.h>

#include <asm/mpc8xx.h>

#include <asm/page.h>

#include <asm/pgtable.h>

#include <asm/8xx_immap.h>

#include <asm/commproc.h>

/*

 * I2C/SPI relocation patch arrays.

 */

#ifdef CONFIG_I2C_SPI_UCODE_PATCH

uint patch_2000[] = {

	0x7FFFEFD9,

	0x3FFD0000,

	0x7FFB49F7,

	0x7FF90000,

	0x5FEFADF7,

	0x5F89ADF7,

	0x5FEFAFF7,

	0x5F89AFF7,

	0x3A9CFBC8,

	0xE7C0EDF0,

	0x77C1E1BB,

	0xF4DC7F1D,

	0xABAD932F,

	0x4E08FDCF,

	0x6E0FAFF8,

	0x7CCF76CF,

	0xFD1FF9CF,

	0xABF88DC6,

	0xAB5679F7,

	0xB0937383,

	0xDFCE79F7,

	0xB091E6BB,

	0xE5BBE74F,

	0xB3FA6F0F,

	0x6FFB76CE,

	0xEE0DF9CF,

	0x2BFBEFEF,

	0xCFEEF9CF,

	0x76CEAD24,

	0x90B2DF9A,

	0x7FDDD0BF,

	0x4BF847FD,

	0x7CCF76CE,

	0xCFEF7E1F,

	0x7F1D7DFD,

	0xF0B6EF71,

	0x7FC177C1,

	0xFBC86079,

	0xE722FBC8,

	0x5FFFDFFF,

	0x5FB2FFFB,

	0xFBC8F3C8,

	0x94A67F01,

	0x7F1D5F39,

	0xAFE85F5E,

	0xFFDFDF96,

	0xCB9FAF7D,

	0x5FC1AFED,

	0x8C1C5FC1,

	0xAFDD5FC3,

	0xDF9A7EFD,

	0xB0B25FB2,

	0xFFFEABAD,

	0x5FB2FFFE,

	0x5FCE600B,

	0xE6BB600B,

	0x5FCEDFC6,

	0x27FBEFDF,

	0x5FC8CFDE,

	0x3A9CE7C0,

	0xEDF0F3C8,

	0x7F0154CD,

	0x7F1D2D3D,

	0x363A7570,

	0x7E0AF1CE,

	0x37EF2E68,

	0x7FEE10EC,

	0xADF8EFDE,

	0xCFEAE52F,

	0x7D0FE12B,

	0xF1CE5F65,

	0x7E0A4DF8,

	0xCFEA5F72,

	0x7D0BEFEE,

	0xCFEA5F74,

	0xE522EFDE,

	0x5F74CFDA,

	0x0B627385,

	0xDF627E0A,

	0x30D8145B,

	0xBFFFF3C8,

	0x5FFFDFFF,

	0xA7F85F5E,

	0xBFFE7F7D,

	0x10D31450,

	0x5F36BFFF,

	0xAF785F5E,

	0xBFFDA7F8,

	0x5F36BFFE,

	0x77FD30C0,

	0x4E08FDCF,

	0xE5FF6E0F,

	0xAFF87E1F,

	0x7E0FFD1F,

	0xF1CF5F1B,

	0xABF80D5E,

	0x5F5EFFEF,

	0x79F730A2,

	0xAFDD5F34,

	0x47F85F34,

	0xAFED7FDD,

	0x50B24978,

	0x47FD7F1D,

	0x7DFD70AD,

	0xEF717EC1,

	0x6BA47F01,

	0x2D267EFD,

	0x30DE5F5E,

	0xFFFD5F5E,

	0xFFEF5F5E,

	0xFFDF0CA0,

	0xAFED0A9E,

	0xAFDD0C3A,

	0x5F3AAFBD,

	0x7FBDB082,

	0x5F8247F8

};

uint patch_2f00[] = {

	0x3E303430,

	0x34343737,

	0xABF7BF9B,

	0x994B4FBD,

	0xBD599493,

	0x349FFF37,

	0xFB9B177D,

	0xD9936956,

	0xBBFDD697,

	0xBDD2FD11,

	0x31DB9BB3,

	0x63139637,

	0x93733693,

	0x193137F7,

	0x331737AF,

	0x7BB9B999,

	0xBB197957,

	0x7FDFD3D5,

	0x73B773F7,

	0x37933B99,

	0x1D115316,

	0x99315315,

	0x31694BF4,

	0xFBDBD359,

	0x31497353,

	0x76956D69,

	0x7B9D9693,

	0x13131979,

	0x79376935

};

#endif

/*

 * I2C/SPI/SMC1 relocation patch arrays.

 */

#ifdef CONFIG_I2C_SPI_SMC1_UCODE_PATCH

uint patch_2000[] = {

	0x3fff0000,

	0x3ffd0000,

	0x3ffb0000,

	0x3ff90000,

	0x5f13eff8,

	0x5eb5eff8,

	0x5f88adf7,

	0x5fefadf7,

	0x3a9cfbc8,

	0x77cae1bb,

	0xf4de7fad,

	0xabae9330,

	0x4e08fdcf,

	0x6e0faff8,

	0x7ccf76cf,

	0xfdaff9cf,

	0xabf88dc8,

	0xab5879f7,

	0xb0925d8d,

	0xdfd079f7,

	0xb090e6bb,

	0xe5bbe74f,

	0x9e046f0f,

	0x6ffb76ce,

	0xee0cf9cf,

	0x2bfbefef,

	0xcfeef9cf,

	0x76cead23,

	0x90b3df99,

	0x7fddd0c1,

	0x4bf847fd,

	0x7ccf76ce,

	0xcfef77ca,

	0x7eaf7fad,

	0x7dfdf0b7,

	0xef7a7fca,

	0x77cafbc8,

	0x6079e722,

	0xfbc85fff,

	0xdfff5fb3,

	0xfffbfbc8,

	0xf3c894a5,

	0xe7c9edf9,

	0x7f9a7fad,

	0x5f36afe8,

	0x5f5bffdf,

	0xdf95cb9e,

	0xaf7d5fc3,

	0xafed8c1b,

	0x5fc3afdd,

	0x5fc5df99,

	0x7efdb0b3,

	0x5fb3fffe,

	0xabae5fb3,

	0xfffe5fd0,

	0x600be6bb,

	0x600b5fd0,

	0xdfc827fb,

	0xefdf5fca,

	0xcfde3a9c,

	0xe7c9edf9,

	0xf3c87f9e,

	0x54ca7fed,

	0x2d3a3637,

	0x756f7e9a,

	0xf1ce37ef,

	0x2e677fee,

	0x10ebadf8,

	0xefdecfea,

	0xe52f7d9f,

	0xe12bf1ce,

	0x5f647e9a,

	0x4df8cfea,

	0x5f717d9b,

	0xefeecfea,

	0x5f73e522,

	0xefde5f73,

	0xcfda0b61,

	0x5d8fdf61,

	0xe7c9edf9,

	0x7e9a30d5,

	0x1458bfff,

	0xf3c85fff,

	0xdfffa7f8,

	0x5f5bbffe,

	0x7f7d10d0,

	0x144d5f33,

	0xbfffaf78,

	0x5f5bbffd,

	0xa7f85f33,

	0xbffe77fd,

	0x30bd4e08,

	0xfdcfe5ff,

	0x6e0faff8,

	0x7eef7e9f,

	0xfdeff1cf,

	0x5f17abf8,

	0x0d5b5f5b,

	0xffef79f7,

	0x309eafdd,

	0x5f3147f8,

	0x5f31afed,

	0x7fdd50af,

	0x497847fd,

	0x7f9e7fed,

	0x7dfd70a9,

	0xef7e7ece,

	0x6ba07f9e,

	0x2d227efd,

	0x30db5f5b,

	0xfffd5f5b,

	0xffef5f5b,

	0xffdf0c9c,

	0xafed0a9a,

	0xafdd0c37,

	0x5f37afbd,

	0x7fbdb081,

	0x5f8147f8,

	0x3a11e710,

	0xedf0ccdd,

	0xf3186d0a,

	0x7f0e5f06,

	0x7fedbb38,

	0x3afe7468,

	0x7fedf4fc,

	0x8ffbb951,

	0xb85f77fd,

	0xb0df5ddd,

	0xdefe7fed,

	0x90e1e74d,

	0x6f0dcbf7,

	0xe7decfed,

	0xcb74cfed,

	0xcfeddf6d,

	0x91714f74,

	0x5dd2deef,

	0x9e04e7df,

	0xefbb6ffb,

	0xe7ef7f0e,

	0x9e097fed,

	0xebdbeffa,

	0xeb54affb,

	0x7fea90d7,

	0x7e0cf0c3,

	0xbffff318,

	0x5fffdfff,

	0xac59efea,

	0x7fce1ee5,

	0xe2ff5ee1,

	0xaffbe2ff,

	0x5ee3affb,

	0xf9cc7d0f,

	0xaef8770f,

	0x7d0fb0c6,

	0xeffbbfff,

	0xcfef5ede,

	0x7d0fbfff,

	0x5ede4cf8,

	0x7fddd0bf,

	0x49f847fd,

	0x7efdf0bb,

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