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Commit f1dc71b8 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add pcie1~3 support for sa8195 virtual machine"

parents d15f5695 c8b5b0eb

arch/arm64/boot/dts/qcom/sa8195-vm-pcie.dtsi

+1061 −1

File changed.

Preview size limit exceeded, changes collapsed.

arch/arm64/boot/dts/qcom/sa8195-vm.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -62,6 +62,18 @@ 
			regulator-name = "pcie_0_gdsc";

		};



		pcie_1_gdsc: pcie_1_gdsc {

			regulator-name = "pcie_1_gdsc";

		};



		pcie_2_gdsc: pcie_2_gdsc {

			regulator-name = "pcie_2_gdsc";

		};



		pcie_3_gdsc: pcie_3_gdsc {

			regulator-name = "pcie_3_gdsc";

		};



		L2A: pm8195_1_l2: regulator-pm8195-1-l2 {

			regulator-name = "ldoa2";

			regulator-min-microvolt = <1800000>;

drivers/clk/qcom/virtio_clk_sa8195p.c

+30 −0
Original line number Diff line number Diff line
@@ -66,8 +66,32 @@ static const char * const sa8195p_gcc_virtio_clocks[] = { 
	[GCC_PCIE_0_SLV_AXI_CLK] = "gcc_pcie_0_slv_axi_clk",

	[GCC_PCIE_0_CLKREF_CLK] = "gcc_pcie_0_clkref_en",

	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = "gcc_pcie_0_slv_q2a_axi_clk",

	[GCC_PCIE_1_PIPE_CLK] = "gcc_pcie_1_pipe_clk",

	[GCC_PCIE_1_AUX_CLK] = "gcc_pcie_1_aux_clk",

	[GCC_PCIE_1_CFG_AHB_CLK] = "gcc_pcie_1_cfg_ahb_clk",

	[GCC_PCIE_1_MSTR_AXI_CLK] = "gcc_pcie_1_mstr_axi_clk",

	[GCC_PCIE_1_SLV_AXI_CLK] = "gcc_pcie_1_slv_axi_clk",

	[GCC_PCIE_1_CLKREF_CLK] = "gcc_pcie_1_clkref_en",

	[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = "gcc_pcie_1_slv_q2a_axi_clk",

	[GCC_PCIE_2_PIPE_CLK] = "gcc_pcie_2_pipe_clk",

	[GCC_PCIE_2_AUX_CLK] = "gcc_pcie_2_aux_clk",

	[GCC_PCIE_2_CFG_AHB_CLK] = "gcc_pcie_2_cfg_ahb_clk",

	[GCC_PCIE_2_MSTR_AXI_CLK] = "gcc_pcie_2_mstr_axi_clk",

	[GCC_PCIE_2_SLV_AXI_CLK] = "gcc_pcie_2_slv_axi_clk",

	[GCC_PCIE_2_CLKREF_CLK] = "gcc_pcie_2_clkref_en",

	[GCC_PCIE_2_SLV_Q2A_AXI_CLK] = "gcc_pcie_2_slv_q2a_axi_clk",

	[GCC_PCIE_3_PIPE_CLK] = "gcc_pcie_3_pipe_clk",

	[GCC_PCIE_3_AUX_CLK] = "gcc_pcie_3_aux_clk",

	[GCC_PCIE_3_CFG_AHB_CLK] = "gcc_pcie_3_cfg_ahb_clk",

	[GCC_PCIE_3_MSTR_AXI_CLK] = "gcc_pcie_3_mstr_axi_clk",

	[GCC_PCIE_3_SLV_AXI_CLK] = "gcc_pcie_3_slv_axi_clk",

	[GCC_PCIE_3_CLKREF_CLK] = "gcc_pcie_3_clkref_en",

	[GCC_PCIE_3_SLV_Q2A_AXI_CLK] = "gcc_pcie_3_slv_q2a_axi_clk",

	[GCC_AGGRE_NOC_PCIE_TBU_CLK] = "gcc_aggre_noc_pcie_tbu_clk",

	[GCC_PCIE0_PHY_REFGEN_CLK] = "gcc_pcie0_phy_refgen_clk",

	[GCC_PCIE1_PHY_REFGEN_CLK] = "gcc_pcie1_phy_refgen_clk",

	[GCC_PCIE2_PHY_REFGEN_CLK] = "gcc_pcie2_phy_refgen_clk",

	[GCC_PCIE3_PHY_REFGEN_CLK] = "gcc_pcie3_phy_refgen_clk",

	[GCC_PCIE_PHY_AUX_CLK] = "gcc_pcie_phy_aux_clk",

	[GCC_SDCC2_AHB_CLK] = "gcc_sdcc2_ahb_clk",

	[GCC_SDCC2_APPS_CLK] = "gcc_sdcc2_apps_clk",
@@ -81,6 +105,12 @@ static const char * const sa8195p_gcc_virtio_resets[] = { 
	[GCC_USB30_SEC_BCR] = "gcc_usb30_sec_master_clk",

	[GCC_PCIE_0_BCR] = "gcc_pcie_0_mstr_axi_clk",

	[GCC_PCIE_0_PHY_BCR] = "gcc_pcie_0_phy_bcr",

	[GCC_PCIE_1_BCR] = "gcc_pcie_1_mstr_axi_clk",

	[GCC_PCIE_1_PHY_BCR] = "gcc_pcie_1_phy_bcr",

	[GCC_PCIE_2_BCR] = "gcc_pcie_2_mstr_axi_clk",

	[GCC_PCIE_2_PHY_BCR] = "gcc_pcie_2_phy_bcr",

	[GCC_PCIE_3_BCR] = "gcc_pcie_3_mstr_axi_clk",

	[GCC_PCIE_3_PHY_BCR] = "gcc_pcie_3_phy_bcr",

};



const struct clk_virtio_desc clk_virtio_sa8195p_gcc = {