Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f093f182 authored by Colin Xu's avatar Colin Xu Committed by Zhenyu Wang
Browse files

drm/i915/gvt: Enable cmd_parser support for BXT. 



Handle BXT cmd_parser as SKL/KBL.

v2: All supported platforms share the same routines.
    Remove the platform check by now and let is_supported_device()
    be the gate keeper.

Signed-off-by: default avatarColin Xu <colin.xu@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent a94cf2e0

drivers/gpu/drm/i915/gvt/cmd_parser.c

+14 −25
Original line number Diff line number Diff line
@@ -1257,7 +1257,9 @@ static int gen8_check_mi_display_flip(struct parser_exec_state *s, 
	if (!info->async_flip)

		return 0;



	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {

	if (IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv)

		|| IS_BROXTON(dev_priv)) {

		stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);

		tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &

				GENMASK(12, 10)) >> 10;
@@ -1285,7 +1287,9 @@ static int gen8_update_plane_mmio_from_mi_display_flip( 


	set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),

		      info->surf_val << 12);

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {

	if (IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv)

		|| IS_BROXTON(dev_priv)) {

		set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),

			      info->stride_val);

		set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
@@ -1309,7 +1313,9 @@ static int decode_mi_display_flip(struct parser_exec_state *s, 


	if (IS_BROADWELL(dev_priv))

		return gen8_decode_mi_display_flip(s, info);

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))

	if (IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv)

		|| IS_BROXTON(dev_priv))

		return skl_decode_mi_display_flip(s, info);



	return -ENODEV;
@@ -1318,26 +1324,14 @@ static int decode_mi_display_flip(struct parser_exec_state *s, 
static int check_mi_display_flip(struct parser_exec_state *s,

		struct mi_display_flip_command_info *info)

{

	struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;



	if (IS_BROADWELL(dev_priv)

		|| IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv))

	return gen8_check_mi_display_flip(s, info);

	return -ENODEV;

}



static int update_plane_mmio_from_mi_display_flip(

		struct parser_exec_state *s,

		struct mi_display_flip_command_info *info)

{

	struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;



	if (IS_BROADWELL(dev_priv)

		|| IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv))

	return gen8_update_plane_mmio_from_mi_display_flip(s, info);

	return -ENODEV;

}



static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
@@ -1616,15 +1610,10 @@ static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm, 
 */

static int batch_buffer_needs_scan(struct parser_exec_state *s)

{

	struct intel_gvt *gvt = s->vgpu->gvt;



	if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)

		|| IS_KABYLAKE(gvt->dev_priv)) {

		/* BDW decides privilege based on address space */

	/* Decide privilege based on address space */

	if (cmd_val(s, 0) & (1 << 8) &&

			!(s->vgpu->scan_nonprivbb & (1 << s->ring_id)))

		return 0;

	}

	return 1;

}