Merge "clk: qcom: gcc-sdm855: Update the GCC clock driver for SDM855" (ef7ccf73) · Commits · e / devices / android_kernel_xiaomi_nabu

drivers/clk/qcom/gcc-sdm855.c

+76 −95

Original line number	Diff line number	Diff line
		@@ -101,73 +101,73 @@ static const char * const gcc_parent_names_1[] = {

		static const struct parent_map gcc_parent_map_2[] = {
		{ P_BI_TCXO, 0 },
		{ P_GPLL0_OUT_MAIN, 1 },
		{ P_GPLL2_OUT_MAIN, 2 },
		{ P_GPLL5_OUT_MAIN, 3 },
		{ P_GPLL1_OUT_MAIN, 4 },
		{ P_GPLL4_OUT_MAIN, 5 },
		{ P_GPLL0_OUT_EVEN, 6 },
		{ P_SLEEP_CLK, 5 },
		{ P_CORE_BI_PLL_TEST_SE, 7 },
		};

		static const char * const gcc_parent_names_2[] = {
		"bi_tcxo",
		"gpll0",
		"gpll2",
		"gpll5",
		"gpll1",
		"gpll4",
		"gpll0_out_even",
		"sleep_clk",
		"core_bi_pll_test_se",
		};

		static const struct parent_map gcc_parent_map_3[] = {
		{ P_BI_TCXO, 0 },
		{ P_SLEEP_CLK, 5 },
		{ P_GPLL0_OUT_MAIN, 1 },
		{ P_CORE_BI_PLL_TEST_SE, 7 },
		};

		static const char * const gcc_parent_names_3[] = {
		"bi_tcxo",
		"sleep_clk",
		"gpll0",
		"core_bi_pll_test_se",
		};

		static const struct parent_map gcc_parent_map_4[] = {
		{ P_BI_TCXO, 0 },
		{ P_GPLL0_OUT_MAIN, 1 },
		{ P_GPLL1_OUT_MAIN, 4 },
		{ P_GPLL0_OUT_EVEN, 6 },
		{ P_CORE_BI_PLL_TEST_SE, 7 },
		};

		static const char * const gcc_parent_names_4[] = {
		"bi_tcxo",
		"gpll0",
		"gpll1",
		"gpll0_out_even",
		"core_bi_pll_test_se",
		};

		static const struct parent_map gcc_parent_map_5[] = {
		{ P_BI_TCXO, 0 },
		{ P_GPLL0_OUT_MAIN, 1 },
		{ P_GPLL1_OUT_MAIN, 4 },
		{ P_GPLL0_OUT_EVEN, 6 },
		{ P_CORE_BI_PLL_TEST_SE, 7 },
		};

		static const char * const gcc_parent_names_5[] = {
		"bi_tcxo",
		"gpll0",
		"gpll1",
		"gpll0_out_even",
		"core_bi_pll_test_se",
		};

		static const struct parent_map gcc_parent_map_6[] = {
		{ P_BI_TCXO, 0 },
		{ P_GPLL0_OUT_MAIN, 1 },
		{ P_GPLL2_OUT_MAIN, 2 },
		{ P_GPLL5_OUT_MAIN, 3 },
		{ P_GPLL1_OUT_MAIN, 4 },
		{ P_GPLL4_OUT_MAIN, 5 },
		{ P_GPLL0_OUT_EVEN, 6 },
		{ P_CORE_BI_PLL_TEST_SE, 7 },
		};

		static const char * const gcc_parent_names_6[] = {
		"bi_tcxo",
		"gpll0",
		"gpll2",
		"gpll5",
		"gpll1",
		"gpll4",
		"gpll0_out_even",
		"core_bi_pll_test_se",
		};

		@@ -385,6 +385,30 @@ static struct clk_alpha_pll gpll7 = {
		},
		};

		static struct clk_alpha_pll gpll9 = {
		.offset = 0x1c000,
		.vco_table = trion_vco,
		.num_vco = ARRAY_SIZE(trion_vco),
		.type = TRION_PLL,
		.clkr = {
		.enable_reg = 0x52000,
		.enable_mask = BIT(9),
		.hw.init = &(struct clk_init_data){
		.name = "gpll9",
		.parent_names = (const char *[]){ "bi_tcxo" },
		.num_parents = 1,
		.ops = &clk_trion_fixed_pll_ops,
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_MIN] = 615000000,
		[VDD_LOW] = 1066000000,
		[VDD_LOW_L1] = 1600000000,
		[VDD_NOMINAL] = 2000000000},
		},
		},
		};

		static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
		F(19200000, P_BI_TCXO, 1, 0, 0),
		F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
		@@ -555,11 +579,11 @@ static struct clk_rcg2 gcc_npu_axi_clk_src = {
		.cmd_rcgr = 0x4d014,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = gcc_parent_map_2,
		.parent_map = gcc_parent_map_6,
		.freq_tbl = ftbl_gcc_npu_axi_clk_src,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_npu_axi_clk_src",
		.parent_names = gcc_parent_names_2,
		.parent_names = gcc_parent_names_6,
		.num_parents = 8,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_ops,
		@@ -585,11 +609,11 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
		.cmd_rcgr = 0x6b02c,
		.mnd_width = 16,
		.hid_width = 5,
		.parent_map = gcc_parent_map_3,
		.parent_map = gcc_parent_map_2,
		.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_pcie_0_aux_clk_src",
		.parent_names = gcc_parent_names_3,
		.parent_names = gcc_parent_names_2,
		.num_parents = 3,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_ops,
		@@ -605,11 +629,11 @@ static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
		.cmd_rcgr = 0x8d02c,
		.mnd_width = 16,
		.hid_width = 5,
		.parent_map = gcc_parent_map_3,
		.parent_map = gcc_parent_map_2,
		.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_pcie_1_aux_clk_src",
		.parent_names = gcc_parent_names_3,
		.parent_names = gcc_parent_names_2,
		.num_parents = 3,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_ops,
		@@ -913,11 +937,11 @@ static struct clk_rcg2 gcc_qupv3_wrap1_core_2x_clk_src = {
		.cmd_rcgr = 0x18018,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = gcc_parent_map_5,
		.parent_map = gcc_parent_map_4,
		.freq_tbl = ftbl_gcc_qupv3_wrap1_core_2x_clk_src,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_qupv3_wrap1_core_2x_clk_src",
		.parent_names = gcc_parent_names_5,
		.parent_names = gcc_parent_names_4,
		.num_parents = 5,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_ops,
		@@ -1203,7 +1227,7 @@ static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
		F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
		F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
		F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
		F(201500000, P_GPLL4_OUT_MAIN, 4, 0, 0),
		F(201600000, P_GPLL9_OUT_MAIN, 4, 0, 0),
		{ }
		};

		@@ -1355,12 +1379,12 @@ static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
		.cmd_rcgr = 0x75094,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = gcc_parent_map_6,
		.parent_map = gcc_parent_map_5,
		.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
		.flags = FORCE_ENABLE_RCG,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_ufs_card_phy_aux_clk_src",
		.parent_names = gcc_parent_names_6,
		.parent_names = gcc_parent_names_5,
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_ops,
		@@ -1459,12 +1483,12 @@ static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
		.cmd_rcgr = 0x77094,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = gcc_parent_map_6,
		.parent_map = gcc_parent_map_5,
		.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
		.flags = FORCE_ENABLE_RCG,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_ufs_phy_phy_aux_clk_src",
		.parent_names = gcc_parent_names_6,
		.parent_names = gcc_parent_names_5,
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_ops,
		@@ -1601,11 +1625,11 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
		.cmd_rcgr = 0xf060,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = gcc_parent_map_3,
		.parent_map = gcc_parent_map_2,
		.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_usb3_prim_phy_aux_clk_src",
		.parent_names = gcc_parent_names_3,
		.parent_names = gcc_parent_names_2,
		.num_parents = 3,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_ops,
		@@ -1620,11 +1644,11 @@ static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
		.cmd_rcgr = 0x10060,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = gcc_parent_map_3,
		.parent_map = gcc_parent_map_2,
		.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_usb3_sec_phy_aux_clk_src",
		.parent_names = gcc_parent_names_3,
		.parent_names = gcc_parent_names_2,
		.num_parents = 3,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_ops,
		@@ -1835,47 +1859,6 @@ static struct clk_branch gcc_camera_xo_clk = {
		},
		};

		static struct clk_branch gcc_ce1_ahb_clk = {
		.halt_reg = 0x4100c,
		.halt_check = BRANCH_HALT_VOTED,
		.hwcg_reg = 0x4100c,
		.hwcg_bit = 1,
		.clkr = {
		.enable_reg = 0x52004,
		.enable_mask = BIT(3),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_ce1_ahb_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_ce1_axi_clk = {
		.halt_reg = 0x41008,
		.halt_check = BRANCH_HALT_VOTED,
		.clkr = {
		.enable_reg = 0x52004,
		.enable_mask = BIT(4),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_ce1_axi_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_ce1_clk = {
		.halt_reg = 0x41004,
		.halt_check = BRANCH_HALT_VOTED,
		.clkr = {
		.enable_reg = 0x52004,
		.enable_mask = BIT(5),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_ce1_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
		.halt_reg = 0xf078,
		.halt_check = BRANCH_HALT,
		@@ -1975,7 +1958,7 @@ static struct clk_branch gcc_cpuss_rbcpr_clk = {

		static struct clk_branch gcc_ddrss_gpu_axi_clk = {
		.halt_reg = 0x71154,
		.halt_check = BRANCH_VOTED,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x71154,
		.enable_mask = BIT(0),
		@@ -2225,7 +2208,7 @@ static struct clk_branch gcc_gpu_iref_clk = {

		static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
		.halt_reg = 0x7100c,
		.halt_check = BRANCH_VOTED,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x7100c,
		.enable_mask = BIT(0),
		@@ -4176,9 +4159,6 @@ static struct clk_regmap *gcc_sdm855_clocks[] = {
		[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
		[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
		[GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
		[GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
		[GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
		[GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
		[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
		[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
		[GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
		@@ -4387,6 +4367,7 @@ static struct clk_regmap *gcc_sdm855_clocks[] = {
		[GPLL1] = &gpll1.clkr,
		[GPLL4] = &gpll4.clkr,
		[GPLL7] = &gpll7.clkr,
		[GPLL9] = &gpll9.clkr,
		};

		static const struct qcom_reset_map gcc_sdm855_resets[] = {

include/dt-bindings/clock/qcom,gcc-sdm855.h

+200 −202

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2017, The Linux Foundation. All rights reserved.
		* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -27,207 +27,205 @@
		#define GCC_CAMERA_HF_AXI_CLK 9
		#define GCC_CAMERA_SF_AXI_CLK 10
		#define GCC_CAMERA_XO_CLK 11
		#define GCC_CE1_AHB_CLK 12
		#define GCC_CE1_AXI_CLK 13
		#define GCC_CE1_CLK 14
		#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 15
		#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 16
		#define GCC_CPUSS_AHB_CLK 17
		#define GCC_CPUSS_AHB_CLK_SRC 18
		#define GCC_CPUSS_DVM_BUS_CLK 19
		#define GCC_CPUSS_GNOC_CLK 20
		#define GCC_CPUSS_RBCPR_CLK 21
		#define GCC_DDRSS_GPU_AXI_CLK 22
		#define GCC_DISP_AHB_CLK 23
		#define GCC_DISP_HF_AXI_CLK 24
		#define GCC_DISP_SF_AXI_CLK 25
		#define GCC_DISP_XO_CLK 26
		#define GCC_EMAC_AXI_CLK 27
		#define GCC_EMAC_PTP_CLK 28
		#define GCC_EMAC_PTP_CLK_SRC 29
		#define GCC_EMAC_RGMII_CLK 30
		#define GCC_EMAC_RGMII_CLK_SRC 31
		#define GCC_EMAC_SLV_AHB_CLK 32
		#define GCC_GP1_CLK 33
		#define GCC_GP1_CLK_SRC 34
		#define GCC_GP2_CLK 35
		#define GCC_GP2_CLK_SRC 36
		#define GCC_GP3_CLK 37
		#define GCC_GP3_CLK_SRC 38
		#define GCC_GPU_CFG_AHB_CLK 39
		#define GCC_GPU_GPLL0_CLK_SRC 40
		#define GCC_GPU_GPLL0_DIV_CLK_SRC 41
		#define GCC_GPU_IREF_CLK 42
		#define GCC_GPU_MEMNOC_GFX_CLK 43
		#define GCC_GPU_SNOC_DVM_GFX_CLK 44
		#define GCC_NPU_AT_CLK 45
		#define GCC_NPU_AXI_CLK 46
		#define GCC_NPU_AXI_CLK_SRC 47
		#define GCC_NPU_CFG_AHB_CLK 48
		#define GCC_NPU_GPLL0_CLK_SRC 49
		#define GCC_NPU_GPLL0_DIV_CLK_SRC 50
		#define GCC_NPU_TRIG_CLK 51
		#define GCC_PCIE0_PHY_REFGEN_CLK 52
		#define GCC_PCIE1_PHY_REFGEN_CLK 53
		#define GCC_PCIE_0_AUX_CLK 54
		#define GCC_PCIE_0_AUX_CLK_SRC 55
		#define GCC_PCIE_0_CFG_AHB_CLK 56
		#define GCC_PCIE_0_CLKREF_CLK 57
		#define GCC_PCIE_0_MSTR_AXI_CLK 58
		#define GCC_PCIE_0_PIPE_CLK 59
		#define GCC_PCIE_0_SLV_AXI_CLK 60
		#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 61
		#define GCC_PCIE_1_AUX_CLK 62
		#define GCC_PCIE_1_AUX_CLK_SRC 63
		#define GCC_PCIE_1_CFG_AHB_CLK 64
		#define GCC_PCIE_1_CLKREF_CLK 65
		#define GCC_PCIE_1_MSTR_AXI_CLK 66
		#define GCC_PCIE_1_PIPE_CLK 67
		#define GCC_PCIE_1_SLV_AXI_CLK 68
		#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 69
		#define GCC_PCIE_PHY_AUX_CLK 70
		#define GCC_PCIE_PHY_REFGEN_CLK_SRC 71
		#define GCC_PDM2_CLK 72
		#define GCC_PDM2_CLK_SRC 73
		#define GCC_PDM_AHB_CLK 74
		#define GCC_PDM_XO4_CLK 75
		#define GCC_PRNG_AHB_CLK 76
		#define GCC_QMIP_CAMERA_NRT_AHB_CLK 77
		#define GCC_QMIP_CAMERA_RT_AHB_CLK 78
		#define GCC_QMIP_DISP_AHB_CLK 79
		#define GCC_QMIP_VIDEO_CVP_AHB_CLK 80
		#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 81
		#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 82
		#define GCC_QSPI_CORE_CLK 83
		#define GCC_QSPI_CORE_CLK_SRC 84
		#define GCC_QUPV3_WRAP0_CORE_2X_CLK 85
		#define GCC_QUPV3_WRAP0_CORE_CLK 86
		#define GCC_QUPV3_WRAP0_S0_CLK 87
		#define GCC_QUPV3_WRAP0_S0_CLK_SRC 88
		#define GCC_QUPV3_WRAP0_S1_CLK 89
		#define GCC_QUPV3_WRAP0_S1_CLK_SRC 90
		#define GCC_QUPV3_WRAP0_S2_CLK 91
		#define GCC_QUPV3_WRAP0_S2_CLK_SRC 92
		#define GCC_QUPV3_WRAP0_S3_CLK 93
		#define GCC_QUPV3_WRAP0_S3_CLK_SRC 94
		#define GCC_QUPV3_WRAP0_S4_CLK 95
		#define GCC_QUPV3_WRAP0_S4_CLK_SRC 96
		#define GCC_QUPV3_WRAP0_S5_CLK 97
		#define GCC_QUPV3_WRAP0_S5_CLK_SRC 98
		#define GCC_QUPV3_WRAP0_S6_CLK 99
		#define GCC_QUPV3_WRAP0_S6_CLK_SRC 100
		#define GCC_QUPV3_WRAP0_S7_CLK 101
		#define GCC_QUPV3_WRAP0_S7_CLK_SRC 102
		#define GCC_QUPV3_WRAP1_CORE_2X_CLK 103
		#define GCC_QUPV3_WRAP1_CORE_2X_CLK_SRC 104
		#define GCC_QUPV3_WRAP1_CORE_CLK 105
		#define GCC_QUPV3_WRAP1_S0_CLK 106
		#define GCC_QUPV3_WRAP1_S0_CLK_SRC 107
		#define GCC_QUPV3_WRAP1_S1_CLK 108
		#define GCC_QUPV3_WRAP1_S1_CLK_SRC 109
		#define GCC_QUPV3_WRAP1_S2_CLK 110
		#define GCC_QUPV3_WRAP1_S2_CLK_SRC 111
		#define GCC_QUPV3_WRAP1_S3_CLK 112
		#define GCC_QUPV3_WRAP1_S3_CLK_SRC 113
		#define GCC_QUPV3_WRAP1_S4_CLK 114
		#define GCC_QUPV3_WRAP1_S4_CLK_SRC 115
		#define GCC_QUPV3_WRAP1_S5_CLK 116
		#define GCC_QUPV3_WRAP1_S5_CLK_SRC 117
		#define GCC_QUPV3_WRAP2_CORE_2X_CLK 118
		#define GCC_QUPV3_WRAP2_CORE_CLK 119
		#define GCC_QUPV3_WRAP2_S0_CLK 120
		#define GCC_QUPV3_WRAP2_S0_CLK_SRC 121
		#define GCC_QUPV3_WRAP2_S1_CLK 122
		#define GCC_QUPV3_WRAP2_S1_CLK_SRC 123
		#define GCC_QUPV3_WRAP2_S2_CLK 124
		#define GCC_QUPV3_WRAP2_S2_CLK_SRC 125
		#define GCC_QUPV3_WRAP2_S3_CLK 126
		#define GCC_QUPV3_WRAP2_S3_CLK_SRC 127
		#define GCC_QUPV3_WRAP2_S4_CLK 128
		#define GCC_QUPV3_WRAP2_S4_CLK_SRC 129
		#define GCC_QUPV3_WRAP2_S5_CLK 130
		#define GCC_QUPV3_WRAP2_S5_CLK_SRC 131
		#define GCC_QUPV3_WRAP_0_M_AHB_CLK 132
		#define GCC_QUPV3_WRAP_0_S_AHB_CLK 133
		#define GCC_QUPV3_WRAP_1_M_AHB_CLK 134
		#define GCC_QUPV3_WRAP_1_S_AHB_CLK 135
		#define GCC_QUPV3_WRAP_2_M_AHB_CLK 136
		#define GCC_QUPV3_WRAP_2_S_AHB_CLK 137
		#define GCC_SDCC2_AHB_CLK 138
		#define GCC_SDCC2_APPS_CLK 139
		#define GCC_SDCC2_APPS_CLK_SRC 140
		#define GCC_SDCC4_AHB_CLK 141
		#define GCC_SDCC4_APPS_CLK 142
		#define GCC_SDCC4_APPS_CLK_SRC 143
		#define GCC_SYS_NOC_CPUSS_AHB_CLK 144
		#define GCC_TSIF_AHB_CLK 145
		#define GCC_TSIF_INACTIVITY_TIMERS_CLK 146
		#define GCC_TSIF_REF_CLK 147
		#define GCC_TSIF_REF_CLK_SRC 148
		#define GCC_UFS_CARD_AHB_CLK 149
		#define GCC_UFS_CARD_AXI_CLK 150
		#define GCC_UFS_CARD_AXI_CLK_SRC 151
		#define GCC_UFS_CARD_AXI_HW_CTL_CLK 152
		#define GCC_UFS_CARD_CLKREF_CLK 153
		#define GCC_UFS_CARD_ICE_CORE_CLK 154
		#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 155
		#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 156
		#define GCC_UFS_CARD_PHY_AUX_CLK 157
		#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 158
		#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 159
		#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 160
		#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 161
		#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 162
		#define GCC_UFS_CARD_UNIPRO_CORE_CLK 163
		#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 164
		#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 165
		#define GCC_UFS_MEM_CLKREF_CLK 166
		#define GCC_UFS_PHY_AHB_CLK 167
		#define GCC_UFS_PHY_AXI_CLK 168
		#define GCC_UFS_PHY_AXI_CLK_SRC 169
		#define GCC_UFS_PHY_AXI_HW_CTL_CLK 170
		#define GCC_UFS_PHY_ICE_CORE_CLK 171
		#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 172
		#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 173
		#define GCC_UFS_PHY_PHY_AUX_CLK 174
		#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 175
		#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 176
		#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 177
		#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 178
		#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 179
		#define GCC_UFS_PHY_UNIPRO_CORE_CLK 180
		#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 181
		#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 182
		#define GCC_USB30_PRIM_MASTER_CLK 183
		#define GCC_USB30_PRIM_MASTER_CLK_SRC 184
		#define GCC_USB30_PRIM_MOCK_UTMI_CLK 185
		#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 186
		#define GCC_USB30_PRIM_SLEEP_CLK 187
		#define GCC_USB30_SEC_MASTER_CLK 188
		#define GCC_USB30_SEC_MASTER_CLK_SRC 189
		#define GCC_USB30_SEC_MOCK_UTMI_CLK 190
		#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 191
		#define GCC_USB30_SEC_SLEEP_CLK 192
		#define GCC_USB3_PRIM_CLKREF_CLK 193
		#define GCC_USB3_PRIM_PHY_AUX_CLK 194
		#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 195
		#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 196
		#define GCC_USB3_PRIM_PHY_PIPE_CLK 197
		#define GCC_USB3_SEC_CLKREF_CLK 198
		#define GCC_USB3_SEC_PHY_AUX_CLK 199
		#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 200
		#define GCC_USB3_SEC_PHY_COM_AUX_CLK 201
		#define GCC_USB3_SEC_PHY_PIPE_CLK 202
		#define GCC_VIDEO_AHB_CLK 203
		#define GCC_VIDEO_AXI0_CLK 204
		#define GCC_VIDEO_AXI1_CLK 205
		#define GCC_VIDEO_AXIC_CLK 206
		#define GCC_VIDEO_XO_CLK 207
		#define GPLL0 208
		#define GPLL0_OUT_EVEN 209
		#define GPLL1 210
		#define GPLL4 211
		#define GPLL7 212
		#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12
		#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13
		#define GCC_CPUSS_AHB_CLK 14
		#define GCC_CPUSS_AHB_CLK_SRC 15
		#define GCC_CPUSS_DVM_BUS_CLK 16
		#define GCC_CPUSS_GNOC_CLK 17
		#define GCC_CPUSS_RBCPR_CLK 18
		#define GCC_DDRSS_GPU_AXI_CLK 19
		#define GCC_DISP_AHB_CLK 20
		#define GCC_DISP_HF_AXI_CLK 21
		#define GCC_DISP_SF_AXI_CLK 22
		#define GCC_DISP_XO_CLK 23
		#define GCC_EMAC_AXI_CLK 24
		#define GCC_EMAC_PTP_CLK 25
		#define GCC_EMAC_PTP_CLK_SRC 26
		#define GCC_EMAC_RGMII_CLK 27
		#define GCC_EMAC_RGMII_CLK_SRC 28
		#define GCC_EMAC_SLV_AHB_CLK 29
		#define GCC_GP1_CLK 30
		#define GCC_GP1_CLK_SRC 31
		#define GCC_GP2_CLK 32
		#define GCC_GP2_CLK_SRC 33
		#define GCC_GP3_CLK 34
		#define GCC_GP3_CLK_SRC 35
		#define GCC_GPU_CFG_AHB_CLK 36
		#define GCC_GPU_GPLL0_CLK_SRC 37
		#define GCC_GPU_GPLL0_DIV_CLK_SRC 38
		#define GCC_GPU_IREF_CLK 39
		#define GCC_GPU_MEMNOC_GFX_CLK 40
		#define GCC_GPU_SNOC_DVM_GFX_CLK 41
		#define GCC_NPU_AT_CLK 42
		#define GCC_NPU_AXI_CLK 43
		#define GCC_NPU_AXI_CLK_SRC 44
		#define GCC_NPU_CFG_AHB_CLK 45
		#define GCC_NPU_GPLL0_CLK_SRC 46
		#define GCC_NPU_GPLL0_DIV_CLK_SRC 47
		#define GCC_NPU_TRIG_CLK 48
		#define GCC_PCIE0_PHY_REFGEN_CLK 49
		#define GCC_PCIE1_PHY_REFGEN_CLK 50
		#define GCC_PCIE_0_AUX_CLK 51
		#define GCC_PCIE_0_AUX_CLK_SRC 52
		#define GCC_PCIE_0_CFG_AHB_CLK 53
		#define GCC_PCIE_0_CLKREF_CLK 54
		#define GCC_PCIE_0_MSTR_AXI_CLK 55
		#define GCC_PCIE_0_PIPE_CLK 56
		#define GCC_PCIE_0_SLV_AXI_CLK 57
		#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 58
		#define GCC_PCIE_1_AUX_CLK 59
		#define GCC_PCIE_1_AUX_CLK_SRC 60
		#define GCC_PCIE_1_CFG_AHB_CLK 61
		#define GCC_PCIE_1_CLKREF_CLK 62
		#define GCC_PCIE_1_MSTR_AXI_CLK 63
		#define GCC_PCIE_1_PIPE_CLK 64
		#define GCC_PCIE_1_SLV_AXI_CLK 65
		#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 66
		#define GCC_PCIE_PHY_AUX_CLK 67
		#define GCC_PCIE_PHY_REFGEN_CLK_SRC 68
		#define GCC_PDM2_CLK 69
		#define GCC_PDM2_CLK_SRC 70
		#define GCC_PDM_AHB_CLK 71
		#define GCC_PDM_XO4_CLK 72
		#define GCC_PRNG_AHB_CLK 73
		#define GCC_QMIP_CAMERA_NRT_AHB_CLK 74
		#define GCC_QMIP_CAMERA_RT_AHB_CLK 75
		#define GCC_QMIP_DISP_AHB_CLK 76
		#define GCC_QMIP_VIDEO_CVP_AHB_CLK 77
		#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 78
		#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 79
		#define GCC_QSPI_CORE_CLK 80
		#define GCC_QSPI_CORE_CLK_SRC 81
		#define GCC_QUPV3_WRAP0_CORE_2X_CLK 82
		#define GCC_QUPV3_WRAP0_CORE_CLK 83
		#define GCC_QUPV3_WRAP0_S0_CLK 84
		#define GCC_QUPV3_WRAP0_S0_CLK_SRC 85
		#define GCC_QUPV3_WRAP0_S1_CLK 86
		#define GCC_QUPV3_WRAP0_S1_CLK_SRC 87
		#define GCC_QUPV3_WRAP0_S2_CLK 88
		#define GCC_QUPV3_WRAP0_S2_CLK_SRC 89
		#define GCC_QUPV3_WRAP0_S3_CLK 90
		#define GCC_QUPV3_WRAP0_S3_CLK_SRC 91
		#define GCC_QUPV3_WRAP0_S4_CLK 92
		#define GCC_QUPV3_WRAP0_S4_CLK_SRC 93
		#define GCC_QUPV3_WRAP0_S5_CLK 94
		#define GCC_QUPV3_WRAP0_S5_CLK_SRC 95
		#define GCC_QUPV3_WRAP0_S6_CLK 96
		#define GCC_QUPV3_WRAP0_S6_CLK_SRC 97
		#define GCC_QUPV3_WRAP0_S7_CLK 98
		#define GCC_QUPV3_WRAP0_S7_CLK_SRC 99
		#define GCC_QUPV3_WRAP1_CORE_2X_CLK 100
		#define GCC_QUPV3_WRAP1_CORE_2X_CLK_SRC 101
		#define GCC_QUPV3_WRAP1_CORE_CLK 102
		#define GCC_QUPV3_WRAP1_S0_CLK 103
		#define GCC_QUPV3_WRAP1_S0_CLK_SRC 104
		#define GCC_QUPV3_WRAP1_S1_CLK 105
		#define GCC_QUPV3_WRAP1_S1_CLK_SRC 106
		#define GCC_QUPV3_WRAP1_S2_CLK 107
		#define GCC_QUPV3_WRAP1_S2_CLK_SRC 108
		#define GCC_QUPV3_WRAP1_S3_CLK 109
		#define GCC_QUPV3_WRAP1_S3_CLK_SRC 110
		#define GCC_QUPV3_WRAP1_S4_CLK 111
		#define GCC_QUPV3_WRAP1_S4_CLK_SRC 112
		#define GCC_QUPV3_WRAP1_S5_CLK 113
		#define GCC_QUPV3_WRAP1_S5_CLK_SRC 114
		#define GCC_QUPV3_WRAP2_CORE_2X_CLK 115
		#define GCC_QUPV3_WRAP2_CORE_CLK 116
		#define GCC_QUPV3_WRAP2_S0_CLK 117
		#define GCC_QUPV3_WRAP2_S0_CLK_SRC 118
		#define GCC_QUPV3_WRAP2_S1_CLK 119
		#define GCC_QUPV3_WRAP2_S1_CLK_SRC 120
		#define GCC_QUPV3_WRAP2_S2_CLK 121
		#define GCC_QUPV3_WRAP2_S2_CLK_SRC 122
		#define GCC_QUPV3_WRAP2_S3_CLK 123
		#define GCC_QUPV3_WRAP2_S3_CLK_SRC 124
		#define GCC_QUPV3_WRAP2_S4_CLK 125
		#define GCC_QUPV3_WRAP2_S4_CLK_SRC 126
		#define GCC_QUPV3_WRAP2_S5_CLK 127
		#define GCC_QUPV3_WRAP2_S5_CLK_SRC 128
		#define GCC_QUPV3_WRAP_0_M_AHB_CLK 129
		#define GCC_QUPV3_WRAP_0_S_AHB_CLK 130
		#define GCC_QUPV3_WRAP_1_M_AHB_CLK 131
		#define GCC_QUPV3_WRAP_1_S_AHB_CLK 132
		#define GCC_QUPV3_WRAP_2_M_AHB_CLK 133
		#define GCC_QUPV3_WRAP_2_S_AHB_CLK 134
		#define GCC_SDCC2_AHB_CLK 135
		#define GCC_SDCC2_APPS_CLK 136
		#define GCC_SDCC2_APPS_CLK_SRC 137
		#define GCC_SDCC4_AHB_CLK 138
		#define GCC_SDCC4_APPS_CLK 139
		#define GCC_SDCC4_APPS_CLK_SRC 140
		#define GCC_SYS_NOC_CPUSS_AHB_CLK 141
		#define GCC_TSIF_AHB_CLK 142
		#define GCC_TSIF_INACTIVITY_TIMERS_CLK 143
		#define GCC_TSIF_REF_CLK 144
		#define GCC_TSIF_REF_CLK_SRC 145
		#define GCC_UFS_CARD_AHB_CLK 146
		#define GCC_UFS_CARD_AXI_CLK 147
		#define GCC_UFS_CARD_AXI_CLK_SRC 148
		#define GCC_UFS_CARD_AXI_HW_CTL_CLK 149
		#define GCC_UFS_CARD_CLKREF_CLK 150
		#define GCC_UFS_CARD_ICE_CORE_CLK 151
		#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 152
		#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 153
		#define GCC_UFS_CARD_PHY_AUX_CLK 154
		#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 155
		#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 156
		#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 157
		#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 158
		#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 159
		#define GCC_UFS_CARD_UNIPRO_CORE_CLK 160
		#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 161
		#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 162
		#define GCC_UFS_MEM_CLKREF_CLK 163
		#define GCC_UFS_PHY_AHB_CLK 164
		#define GCC_UFS_PHY_AXI_CLK 165
		#define GCC_UFS_PHY_AXI_CLK_SRC 166
		#define GCC_UFS_PHY_AXI_HW_CTL_CLK 167
		#define GCC_UFS_PHY_ICE_CORE_CLK 168
		#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 169
		#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 170
		#define GCC_UFS_PHY_PHY_AUX_CLK 171
		#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 172
		#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 173
		#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 174
		#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 175
		#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 176
		#define GCC_UFS_PHY_UNIPRO_CORE_CLK 177
		#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 178
		#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 179
		#define GCC_USB30_PRIM_MASTER_CLK 180
		#define GCC_USB30_PRIM_MASTER_CLK_SRC 181
		#define GCC_USB30_PRIM_MOCK_UTMI_CLK 182
		#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 183
		#define GCC_USB30_PRIM_SLEEP_CLK 184
		#define GCC_USB30_SEC_MASTER_CLK 185
		#define GCC_USB30_SEC_MASTER_CLK_SRC 186
		#define GCC_USB30_SEC_MOCK_UTMI_CLK 187
		#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 188
		#define GCC_USB30_SEC_SLEEP_CLK 189
		#define GCC_USB3_PRIM_CLKREF_CLK 190
		#define GCC_USB3_PRIM_PHY_AUX_CLK 191
		#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 192
		#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 193
		#define GCC_USB3_PRIM_PHY_PIPE_CLK 194
		#define GCC_USB3_SEC_CLKREF_CLK 195
		#define GCC_USB3_SEC_PHY_AUX_CLK 196
		#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 197
		#define GCC_USB3_SEC_PHY_COM_AUX_CLK 198
		#define GCC_USB3_SEC_PHY_PIPE_CLK 199
		#define GCC_VIDEO_AHB_CLK 200
		#define GCC_VIDEO_AXI0_CLK 201
		#define GCC_VIDEO_AXI1_CLK 202
		#define GCC_VIDEO_AXIC_CLK 203
		#define GCC_VIDEO_XO_CLK 204
		#define GPLL0 205
		#define GPLL0_OUT_EVEN 206
		#define GPLL1 207
		#define GPLL4 208
		#define GPLL7 209
		#define GPLL9 210

		/* Reset clocks */
		#define GCC_EMAC_BCR 0