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Commit ef7cca02 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: camera: sensor: Adjust csiphy skew filter setting"

parents 887a2486 7d5f3ac2

drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_3_5_hwreg.h

+1 −2
Original line number Diff line number Diff line
@@ -14,7 +14,6 @@ 
#define MSM_CSIPHY_3_5_HWREG_H



#define ULPM_WAKE_UP_TIMER_MODE                   2

#define GLITCH_ELIMINATION_NUM                    0x12 /* bit [6:4] */



#include <sensor/csiphy/msm_csiphy.h>
@@ -47,7 +46,7 @@ static struct csiphy_reg_3ph_parms_t csiphy_v3_5_3ph = { 
	{0x138, 0x0},

	{0x13C, 0x10},

	{0x140, 0x1},

	{0x144, GLITCH_ELIMINATION_NUM},

	{0x144, 0x32},

	{0x148, 0xFE},

	{0x14C, 0x1},

	{0x154, 0x0},

drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c

+15 −5
Original line number Diff line number Diff line
@@ -59,6 +59,7 @@ 
#define SNPS_INTERPHY_OFFSET                      0x800

#define SET_THE_BIT(x)                            (0x1 << x)

#define SNPS_MAX_DATA_RATE_PER_LANE               2500000000ULL

#define GBPS                                      1000000000



#undef CDBG

#define CDBG(fmt, args...) pr_debug(fmt, ##args)
@@ -769,11 +770,20 @@ static int msm_csiphy_3phase_lane_config( 
				.mipi_csiphy_3ph_lnn_ctrl51.addr +

				0x200*i);

		}

		if ((csiphy_dev->hw_version == CSIPHY_VERSION_V35) &&

			((csiphy_params->data_rate /

			csiphy_params->lane_cnt) > 2 * GBPS)) {

			msm_camera_io_w(0x40,

				csiphybase +

				csiphy_dev->ctrl_reg->csiphy_3ph_reg

				.mipi_csiphy_3ph_lnn_ctrl25.addr + 0x200*i);

		} else {

			msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg

				.mipi_csiphy_3ph_lnn_ctrl25.data,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg

				csiphybase +

				csiphy_dev->ctrl_reg->csiphy_3ph_reg

				.mipi_csiphy_3ph_lnn_ctrl25.addr + 0x200*i);



		}

		lane_mask >>= 1;

		i++;

	}