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Commit ef5b812a authored by Ray Jui's avatar Ray Jui Committed by Florian Fainelli
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ARM: dts: Put Cygnus core components under core bus 



Put all Cygnus core components into "core" node of type "simple-bus" in
bcm-cygnus.dtsi

Signed-off-by: default avatarRay Jui <rjui@broadcom.com>
Reviewed-by: default avatarScott Branden <sbranden@broadcom.com>
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
parent 5b159b62

arch/arm/boot/dts/bcm-cygnus.dtsi

+30 −24
Original line number Diff line number Diff line
@@ -58,6 +58,36 @@ 


	/include/ "bcm-cygnus-clock.dtsi"



	core {

		compatible = "simple-bus";

		ranges = <0x00000000 0x19000000 0x1000000>;

		#address-cells = <1>;

		#size-cells = <1>;



		timer@20200 {

			compatible = "arm,cortex-a9-global-timer";

			reg = <0x20200 0x100>;

			interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&periph_clk>;

		};



		gic: interrupt-controller@21000 {

			compatible = "arm,cortex-a9-gic";

			#interrupt-cells = <3>;

			#address-cells = <0>;

			interrupt-controller;

			reg = <0x21000 0x1000>,

			      <0x20100 0x100>;

		};



		L2: l2-cache {

			compatible = "arm,pl310-cache";

			reg = <0x22000 0x1000>;

			cache-unified;

			cache-level = <2>;

		};

	};



	pinctrl: pinctrl@0x0301d0c8 {

		compatible = "brcm,cygnus-pinmux";

		reg = <0x0301d0c8 0x30>,
@@ -227,28 +257,4 @@ 


		brcm,nand-has-wp;

	};



	gic: interrupt-controller@19021000 {

		compatible = "arm,cortex-a9-gic";

		#interrupt-cells = <3>;

		#address-cells = <0>;

		interrupt-controller;

		reg = <0x19021000 0x1000>,

		      <0x19020100 0x100>;

	};



	L2: l2-cache {

		compatible = "arm,pl310-cache";

		reg = <0x19022000 0x1000>;

		cache-unified;

		cache-level = <2>;

	};



	timer@19020200 {

		compatible = "arm,cortex-a9-global-timer";

		reg = <0x19020200 0x100>;

		interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&periph_clk>;

	};



};