Loading drivers/power/supply/qcom/qpnp-smb5.c +2 −10 Original line number Diff line number Diff line Loading @@ -293,6 +293,7 @@ static int smb5_chg_config_init(struct smb5 *chip) #define MICRO_1P5A 1500000 #define MICRO_P1A 100000 #define MICRO_1PA 1000000 #define MICRO_3PA 3000000 #define OTG_DEFAULT_DEGLITCH_TIME_MS 50 #define DEFAULT_WD_BARK_TIME 64 static int smb5_parse_dt(struct smb5 *chip) Loading Loading @@ -349,7 +350,7 @@ static int smb5_parse_dt(struct smb5 *chip) "qcom,otg-cl-ua", &chg->otg_cl_ua); if (rc < 0) chg->otg_cl_ua = (chip->chg.smb_version == PMI632_SUBTYPE) ? MICRO_1PA : MICRO_1P5A; MICRO_1PA : MICRO_3PA; rc = of_property_read_u32(node, "qcom,chg-term-src", &chip->dt.term_current_src); Loading Loading @@ -2088,15 +2089,6 @@ static int smb5_init_hw(struct smb5 *chip) } } /* set the Source (OTG) mode current limit */ rc = smblib_masked_write(chg, DCDC_OTG_CURRENT_LIMIT_CFG_REG, OTG_CURRENT_LIMIT_MASK, OTG_CURRENT_LIMIT_3000_MA); if (rc < 0) { dev_err(chg->dev, "Couldn't configure DCDC_OTG_CURRENT_LIMIT_CFG rc=%d\n", rc); return rc; } if (chg->sw_jeita_enabled) { rc = smblib_disable_hw_jeita(chg, true); if (rc < 0) { Loading drivers/power/supply/qcom/smb5-reg.h +0 −9 Original line number Diff line number Diff line Loading @@ -140,15 +140,6 @@ enum { #define DCDC_FSW_SEL_REG (DCDC_BASE + 0x50) #define DCDC_OTG_CURRENT_LIMIT_CFG_REG (DCDC_BASE + 0x52) #define OTG_CURRENT_LIMIT_MASK GENMASK(2, 0) enum { OTG_CURRENT_LIMIT_500_MA, OTG_CURRENT_LIMIT_1000_MA, OTG_CURRENT_LIMIT_1500_MA, OTG_CURRENT_LIMIT_2000_MA, OTG_CURRENT_LIMIT_2500_MA, OTG_CURRENT_LIMIT_3000_MA }; #define DCDC_OTG_CFG_REG (DCDC_BASE + 0x53) #define OTG_EN_SRC_CFG_BIT BIT(1) Loading Loading
drivers/power/supply/qcom/qpnp-smb5.c +2 −10 Original line number Diff line number Diff line Loading @@ -293,6 +293,7 @@ static int smb5_chg_config_init(struct smb5 *chip) #define MICRO_1P5A 1500000 #define MICRO_P1A 100000 #define MICRO_1PA 1000000 #define MICRO_3PA 3000000 #define OTG_DEFAULT_DEGLITCH_TIME_MS 50 #define DEFAULT_WD_BARK_TIME 64 static int smb5_parse_dt(struct smb5 *chip) Loading Loading @@ -349,7 +350,7 @@ static int smb5_parse_dt(struct smb5 *chip) "qcom,otg-cl-ua", &chg->otg_cl_ua); if (rc < 0) chg->otg_cl_ua = (chip->chg.smb_version == PMI632_SUBTYPE) ? MICRO_1PA : MICRO_1P5A; MICRO_1PA : MICRO_3PA; rc = of_property_read_u32(node, "qcom,chg-term-src", &chip->dt.term_current_src); Loading Loading @@ -2088,15 +2089,6 @@ static int smb5_init_hw(struct smb5 *chip) } } /* set the Source (OTG) mode current limit */ rc = smblib_masked_write(chg, DCDC_OTG_CURRENT_LIMIT_CFG_REG, OTG_CURRENT_LIMIT_MASK, OTG_CURRENT_LIMIT_3000_MA); if (rc < 0) { dev_err(chg->dev, "Couldn't configure DCDC_OTG_CURRENT_LIMIT_CFG rc=%d\n", rc); return rc; } if (chg->sw_jeita_enabled) { rc = smblib_disable_hw_jeita(chg, true); if (rc < 0) { Loading
drivers/power/supply/qcom/smb5-reg.h +0 −9 Original line number Diff line number Diff line Loading @@ -140,15 +140,6 @@ enum { #define DCDC_FSW_SEL_REG (DCDC_BASE + 0x50) #define DCDC_OTG_CURRENT_LIMIT_CFG_REG (DCDC_BASE + 0x52) #define OTG_CURRENT_LIMIT_MASK GENMASK(2, 0) enum { OTG_CURRENT_LIMIT_500_MA, OTG_CURRENT_LIMIT_1000_MA, OTG_CURRENT_LIMIT_1500_MA, OTG_CURRENT_LIMIT_2000_MA, OTG_CURRENT_LIMIT_2500_MA, OTG_CURRENT_LIMIT_3000_MA }; #define DCDC_OTG_CFG_REG (DCDC_BASE + 0x53) #define OTG_EN_SRC_CFG_BIT BIT(1) Loading