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Commit ef0f30ab authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "power: qpnp-fg-gen4: Set default values for {dis}charging Ki coefficients"

parents 407a7f77 5601bfb4

drivers/power/supply/qcom/fg-core.h

+4 −0
Original line number Diff line number Diff line
@@ -202,9 +202,13 @@ enum fg_sram_param_id { 
	FG_SRAM_KI_COEFF_LOW_DISCHG,

	FG_SRAM_KI_COEFF_MED_DISCHG,

	FG_SRAM_KI_COEFF_HI_DISCHG,

	FG_SRAM_KI_COEFF_LO_MED_DCHG_THR,

	FG_SRAM_KI_COEFF_MED_HI_DCHG_THR,

	FG_SRAM_KI_COEFF_LOW_CHG,

	FG_SRAM_KI_COEFF_MED_CHG,

	FG_SRAM_KI_COEFF_HI_CHG,

	FG_SRAM_KI_COEFF_LO_MED_CHG_THR,

	FG_SRAM_KI_COEFF_MED_HI_CHG_THR,

	FG_SRAM_KI_COEFF_FULL_SOC,

	FG_SRAM_KI_COEFF_CUTOFF,

	FG_SRAM_ESR_TIGHT_FILTER,

drivers/power/supply/qcom/qpnp-fg-gen4.c

+238 −100
Original line number Diff line number Diff line
@@ -92,12 +92,20 @@ 
#define KI_COEFF_MED_DISCHG_OFFSET	0

#define KI_COEFF_HI_DISCHG_WORD		26

#define KI_COEFF_HI_DISCHG_OFFSET	1

#define KI_COEFF_LO_MED_DCHG_THR_WORD	27

#define KI_COEFF_LO_MED_DCHG_THR_OFFSET	0

#define KI_COEFF_MED_HI_DCHG_THR_WORD	27

#define KI_COEFF_MED_HI_DCHG_THR_OFFSET	1

#define KI_COEFF_LOW_CHG_WORD		28

#define KI_COEFF_LOW_CHG_OFFSET		0

#define KI_COEFF_MED_CHG_WORD		28

#define KI_COEFF_MED_CHG_OFFSET		1

#define KI_COEFF_HI_CHG_WORD		29

#define KI_COEFF_HI_CHG_OFFSET		0

#define KI_COEFF_LO_MED_CHG_THR_WORD	29

#define KI_COEFF_LO_MED_CHG_THR_OFFSET	1

#define KI_COEFF_MED_HI_CHG_THR_WORD	30

#define KI_COEFF_MED_HI_CHG_THR_OFFSET	0

#define DELTA_BSOC_THR_WORD		30

#define DELTA_BSOC_THR_OFFSET		1

#define SLOPE_LIMIT_WORD		32
@@ -235,12 +243,16 @@ struct fg_dt_props { 
	int	ki_coeff_low_chg;

	int	ki_coeff_med_chg;

	int	ki_coeff_hi_chg;

	int	ki_coeff_lo_med_chg_thr_ma;

	int	ki_coeff_med_hi_chg_thr_ma;

	int	ki_coeff_cutoff_gain;

	int	ki_coeff_full_soc_dischg[2];

	int	ki_coeff_soc[KI_COEFF_SOC_LEVELS];

	int	ki_coeff_low_dischg[KI_COEFF_SOC_LEVELS];

	int	ki_coeff_med_dischg[KI_COEFF_SOC_LEVELS];

	int	ki_coeff_hi_dischg[KI_COEFF_SOC_LEVELS];

	int	ki_coeff_lo_med_dchg_thr_ma;

	int	ki_coeff_med_hi_dchg_thr_ma;

	int	slope_limit_coeffs[SLOPE_LIMIT_NUM_COEFFS];

};
@@ -529,12 +541,24 @@ static struct fg_sram_param pm8150b_v2_sram_params[] = { 
	PARAM(KI_COEFF_HI_DISCHG, KI_COEFF_HI_DISCHG_WORD,

		KI_COEFF_HI_DISCHG_OFFSET, 1, 1000, 61035, 0,

		fg_encode_default, NULL),

	PARAM(KI_COEFF_LO_MED_DCHG_THR, KI_COEFF_LO_MED_DCHG_THR_WORD,

		KI_COEFF_LO_MED_DCHG_THR_OFFSET, 1, 1000, 15625, 0,

		fg_encode_default, NULL),

	PARAM(KI_COEFF_MED_HI_DCHG_THR, KI_COEFF_MED_HI_DCHG_THR_WORD,

		KI_COEFF_MED_HI_DCHG_THR_OFFSET, 1, 1000, 15625, 0,

		fg_encode_default, NULL),

	PARAM(KI_COEFF_LOW_CHG, KI_COEFF_LOW_CHG_WORD, KI_COEFF_LOW_CHG_OFFSET,

		1, 1000, 61035, 0, fg_encode_default, NULL),

	PARAM(KI_COEFF_MED_CHG, KI_COEFF_MED_CHG_WORD, KI_COEFF_MED_CHG_OFFSET,

		1, 1000, 61035, 0, fg_encode_default, NULL),

	PARAM(KI_COEFF_HI_CHG, KI_COEFF_HI_CHG_WORD, KI_COEFF_HI_CHG_OFFSET, 1,

		1000, 61035, 0, fg_encode_default, NULL),

	PARAM(KI_COEFF_LO_MED_CHG_THR, KI_COEFF_LO_MED_CHG_THR_WORD,

		KI_COEFF_LO_MED_CHG_THR_OFFSET, 1, 1000, 15625, 0,

		fg_encode_default, NULL),

	PARAM(KI_COEFF_MED_HI_CHG_THR, KI_COEFF_MED_HI_CHG_THR_WORD,

		KI_COEFF_MED_HI_CHG_THR_OFFSET, 1, 1000, 15625, 0,

		fg_encode_default, NULL),

	PARAM(SLOPE_LIMIT, SLOPE_LIMIT_WORD, SLOPE_LIMIT_OFFSET, 1, 8192,

		1000000, 0, fg_encode_default, NULL),

	PARAM(BATT_TEMP_COLD, BATT_TEMP_CONFIG_WORD, BATT_TEMP_COLD_OFFSET, 1,
@@ -1400,8 +1424,8 @@ static void fg_gen4_update_rslow_coeff(struct fg_dev *fg, int batt_temp) 
	}

}



#define KI_COEFF_FULL_SOC_NORM_DEFAULT		733

#define KI_COEFF_FULL_SOC_LOW_DEFAULT		184

#define KI_COEFF_FULL_SOC_NORM_DEFAULT	2442

#define KI_COEFF_FULL_SOC_LOW_DEFAULT	2442

static int fg_gen4_adjust_ki_coeff_full_soc(struct fg_gen4_chip *chip,

						int batt_temp)

{
@@ -1409,15 +1433,13 @@ static int fg_gen4_adjust_ki_coeff_full_soc(struct fg_gen4_chip *chip, 
	int rc, ki_coeff_full_soc_norm, ki_coeff_full_soc_low;

	u8 val;



	if (batt_temp < 0) {

	if ((batt_temp < 0) ||

		(fg->charge_status == POWER_SUPPLY_STATUS_DISCHARGING)) {

		ki_coeff_full_soc_norm = 0;

		ki_coeff_full_soc_low = 0;

	} else if (fg->charge_status == POWER_SUPPLY_STATUS_DISCHARGING) {

	} else if (fg->charge_status == POWER_SUPPLY_STATUS_CHARGING) {

		ki_coeff_full_soc_norm = chip->dt.ki_coeff_full_soc_dischg[0];

		ki_coeff_full_soc_low = chip->dt.ki_coeff_full_soc_dischg[1];

	} else {

		ki_coeff_full_soc_norm = KI_COEFF_FULL_SOC_NORM_DEFAULT;

		ki_coeff_full_soc_low = KI_COEFF_FULL_SOC_LOW_DEFAULT;

	}



	if (chip->ki_coeff_full_soc[0] == ki_coeff_full_soc_norm &&
@@ -1449,38 +1471,13 @@ static int fg_gen4_adjust_ki_coeff_full_soc(struct fg_gen4_chip *chip, 
	return 0;

}



#define KI_COEFF_LOW_DISCHG_DEFAULT	428

#define KI_COEFF_MED_DISCHG_DEFAULT	245

#define KI_COEFF_HI_DISCHG_DEFAULT	123

static int fg_gen4_adjust_ki_coeff_dischg(struct fg_dev *fg)

static int fg_gen4_set_ki_coeff_dischg(struct fg_dev *fg, int ki_coeff_low,

		int ki_coeff_med, int ki_coeff_hi)

{

	struct fg_gen4_chip *chip = container_of(fg, struct fg_gen4_chip, fg);

	int rc, i, msoc;

	int ki_coeff_low = KI_COEFF_LOW_DISCHG_DEFAULT;

	int ki_coeff_med = KI_COEFF_MED_DISCHG_DEFAULT;

	int ki_coeff_hi = KI_COEFF_HI_DISCHG_DEFAULT;

	int rc;

	u8 val;



	if (!chip->ki_coeff_dischg_en)

		return 0;



	rc = fg_gen4_get_prop_capacity(fg, &msoc);

	if (rc < 0) {

		pr_err("Error in getting capacity, rc=%d\n", rc);

		return rc;

	}



	if (fg->charge_status == POWER_SUPPLY_STATUS_DISCHARGING) {

		for (i = KI_COEFF_SOC_LEVELS - 1; i >= 0; i--) {

			if (msoc < chip->dt.ki_coeff_soc[i]) {

				ki_coeff_low = chip->dt.ki_coeff_low_dischg[i];

				ki_coeff_med = chip->dt.ki_coeff_med_dischg[i];

				ki_coeff_hi = chip->dt.ki_coeff_hi_dischg[i];

			}

		}

	}



	if (ki_coeff_low > 0) {

	if (ki_coeff_low >= 0) {

		fg_encode(fg->sp, FG_SRAM_KI_COEFF_LOW_DISCHG, ki_coeff_low,

			&val);

		rc = fg_sram_write(fg,
@@ -1495,7 +1492,7 @@ static int fg_gen4_adjust_ki_coeff_dischg(struct fg_dev *fg) 
		fg_dbg(fg, FG_STATUS, "Wrote ki_coeff_low %d\n", ki_coeff_low);

	}



	if (ki_coeff_med > 0) {

	if (ki_coeff_med >= 0) {

		fg_encode(fg->sp, FG_SRAM_KI_COEFF_MED_DISCHG, ki_coeff_med,

			&val);

		rc = fg_sram_write(fg,
@@ -1510,7 +1507,7 @@ static int fg_gen4_adjust_ki_coeff_dischg(struct fg_dev *fg) 
		fg_dbg(fg, FG_STATUS, "Wrote ki_coeff_med %d\n", ki_coeff_med);

	}



	if (ki_coeff_hi > 0) {

	if (ki_coeff_hi >= 0) {

		fg_encode(fg->sp, FG_SRAM_KI_COEFF_HI_DISCHG, ki_coeff_hi,

			&val);

		rc = fg_sram_write(fg,
@@ -1528,6 +1525,44 @@ static int fg_gen4_adjust_ki_coeff_dischg(struct fg_dev *fg) 
	return 0;

}



#define KI_COEFF_LOW_DISCHG_DEFAULT	122

#define KI_COEFF_MED_DISCHG_DEFAULT	62

#define KI_COEFF_HI_DISCHG_DEFAULT	0

static int fg_gen4_adjust_ki_coeff_dischg(struct fg_dev *fg)

{

	struct fg_gen4_chip *chip = container_of(fg, struct fg_gen4_chip, fg);

	int rc, i, msoc;

	int ki_coeff_low = KI_COEFF_LOW_DISCHG_DEFAULT;

	int ki_coeff_med = KI_COEFF_MED_DISCHG_DEFAULT;

	int ki_coeff_hi = KI_COEFF_HI_DISCHG_DEFAULT;



	if (!chip->ki_coeff_dischg_en)

		return 0;



	rc = fg_gen4_get_prop_capacity(fg, &msoc);

	if (rc < 0) {

		pr_err("Error in getting capacity, rc=%d\n", rc);

		return rc;

	}



	if (fg->charge_status == POWER_SUPPLY_STATUS_DISCHARGING) {

		for (i = KI_COEFF_SOC_LEVELS - 1; i >= 0; i--) {

			if (msoc < chip->dt.ki_coeff_soc[i]) {

				ki_coeff_low = chip->dt.ki_coeff_low_dischg[i];

				ki_coeff_med = chip->dt.ki_coeff_med_dischg[i];

				ki_coeff_hi = chip->dt.ki_coeff_hi_dischg[i];

			}

		}

	}



	rc = fg_gen4_set_ki_coeff_dischg(fg,

			ki_coeff_low, ki_coeff_med, ki_coeff_hi);

	if (rc < 0)

		return rc;



	return 0;

}



static int fg_gen4_slope_limit_config(struct fg_gen4_chip *chip, int batt_temp)

{

	struct fg_dev *fg = &chip->fg;
@@ -4940,12 +4975,145 @@ static int fg_gen4_batt_temp_config(struct fg_gen4_chip *chip) 
	return rc;

}



static int fg_gen4_init_ki_coeffts(struct fg_gen4_chip *chip)

{

	int rc;

	u8 val;

	struct fg_dev *fg = &chip->fg;



	if (chip->dt.ki_coeff_low_chg != -EINVAL) {

		fg_encode(fg->sp, FG_SRAM_KI_COEFF_LOW_CHG,

			chip->dt.ki_coeff_low_chg, &val);

		rc = fg_sram_write(fg,

			fg->sp[FG_SRAM_KI_COEFF_LOW_CHG].addr_word,

			fg->sp[FG_SRAM_KI_COEFF_LOW_CHG].addr_byte, &val,

			fg->sp[FG_SRAM_KI_COEFF_LOW_CHG].len,

			FG_IMA_DEFAULT);

		if (rc < 0) {

			pr_err("Error in writing ki_coeff_low_chg, rc=%d\n",

				rc);

			return rc;

		}

	}



	if (chip->dt.ki_coeff_med_chg != -EINVAL) {

		fg_encode(fg->sp, FG_SRAM_KI_COEFF_MED_CHG,

			chip->dt.ki_coeff_med_chg, &val);

		rc = fg_sram_write(fg,

			fg->sp[FG_SRAM_KI_COEFF_MED_CHG].addr_word,

			fg->sp[FG_SRAM_KI_COEFF_MED_CHG].addr_byte, &val,

			fg->sp[FG_SRAM_KI_COEFF_MED_CHG].len,

			FG_IMA_DEFAULT);

		if (rc < 0) {

			pr_err("Error in writing ki_coeff_med_chg, rc=%d\n",

				rc);

			return rc;

		}

	}



	if (chip->dt.ki_coeff_hi_chg != -EINVAL) {

		fg_encode(fg->sp, FG_SRAM_KI_COEFF_HI_CHG,

			chip->dt.ki_coeff_hi_chg, &val);

		rc = fg_sram_write(fg,

			fg->sp[FG_SRAM_KI_COEFF_HI_CHG].addr_word,

			fg->sp[FG_SRAM_KI_COEFF_HI_CHG].addr_byte, &val,

			fg->sp[FG_SRAM_KI_COEFF_HI_CHG].len,

			FG_IMA_DEFAULT);

		if (rc < 0) {

			pr_err("Error in writing ki_coeff_hi_chg, rc=%d\n", rc);

			return rc;

		}

	}



	if (chip->dt.ki_coeff_lo_med_chg_thr_ma != -EINVAL) {

		fg_encode(fg->sp, FG_SRAM_KI_COEFF_LO_MED_CHG_THR,

			chip->dt.ki_coeff_lo_med_chg_thr_ma, &val);

		rc = fg_sram_write(fg,

			fg->sp[FG_SRAM_KI_COEFF_LO_MED_CHG_THR].addr_word,

			fg->sp[FG_SRAM_KI_COEFF_LO_MED_CHG_THR].addr_byte,

			&val, fg->sp[FG_SRAM_KI_COEFF_LO_MED_CHG_THR].len,

			FG_IMA_DEFAULT);

		if (rc < 0) {

			pr_err("Error in writing ki_coeff_lo_med_chg_thr_ma, rc=%d\n",

				rc);

			return rc;

		}

	}



	if (chip->dt.ki_coeff_med_hi_chg_thr_ma != -EINVAL) {

		fg_encode(fg->sp, FG_SRAM_KI_COEFF_MED_HI_CHG_THR,

			chip->dt.ki_coeff_med_hi_chg_thr_ma, &val);

		rc = fg_sram_write(fg,

			fg->sp[FG_SRAM_KI_COEFF_MED_HI_CHG_THR].addr_word,

			fg->sp[FG_SRAM_KI_COEFF_MED_HI_CHG_THR].addr_byte, &val,

			fg->sp[FG_SRAM_KI_COEFF_MED_HI_CHG_THR].len,

			FG_IMA_DEFAULT);

		if (rc < 0) {

			pr_err("Error in writing ki_coeff_med_hi_chg_thr_ma, rc=%d\n",

				rc);

			return rc;

		}

	}



	if (chip->dt.ki_coeff_lo_med_dchg_thr_ma != -EINVAL) {

		fg_encode(fg->sp, FG_SRAM_KI_COEFF_LO_MED_DCHG_THR,

			chip->dt.ki_coeff_lo_med_dchg_thr_ma, &val);

		rc = fg_sram_write(fg,

			fg->sp[FG_SRAM_KI_COEFF_LO_MED_DCHG_THR].addr_word,

			fg->sp[FG_SRAM_KI_COEFF_LO_MED_DCHG_THR].addr_byte,

			&val, fg->sp[FG_SRAM_KI_COEFF_LO_MED_DCHG_THR].len,

			FG_IMA_DEFAULT);

		if (rc < 0) {

			pr_err("Error in writing ki_coeff_lo_med_dchg_thr_ma, rc=%d\n",

				rc);

			return rc;

		}

	}



	if (chip->dt.ki_coeff_med_hi_dchg_thr_ma != -EINVAL) {

		fg_encode(fg->sp, FG_SRAM_KI_COEFF_MED_HI_DCHG_THR,

			chip->dt.ki_coeff_med_hi_dchg_thr_ma, &val);

		rc = fg_sram_write(fg,

			fg->sp[FG_SRAM_KI_COEFF_MED_HI_DCHG_THR].addr_word,

			fg->sp[FG_SRAM_KI_COEFF_MED_HI_DCHG_THR].addr_byte,

			&val, fg->sp[FG_SRAM_KI_COEFF_MED_HI_DCHG_THR].len,

			FG_IMA_DEFAULT);

		if (rc < 0) {

			pr_err("Error in writing ki_coeff_med_hi_dchg_thr_ma, rc=%d\n",

				rc);

			return rc;

		}

	}



	if (chip->dt.ki_coeff_cutoff_gain != -EINVAL) {

		fg_encode(fg->sp, FG_SRAM_KI_COEFF_CUTOFF,

			  chip->dt.ki_coeff_cutoff_gain, &val);

		rc = fg_sram_write(fg,

			fg->sp[FG_SRAM_KI_COEFF_CUTOFF].addr_word,

			fg->sp[FG_SRAM_KI_COEFF_CUTOFF].addr_byte, &val,

			fg->sp[FG_SRAM_KI_COEFF_CUTOFF].len,

			FG_IMA_DEFAULT);

		if (rc < 0) {

			pr_err("Error in writing ki_coeff_cutoff_gain, rc=%d\n",

				rc);

			return rc;

		}

	}



	rc = fg_gen4_set_ki_coeff_dischg(fg, KI_COEFF_LOW_DISCHG_DEFAULT,

		KI_COEFF_MED_DISCHG_DEFAULT, KI_COEFF_HI_DISCHG_DEFAULT);

	if (rc < 0)

		return rc;



	return 0;

}



#define VBATT_TAU_DEFAULT	3

static int fg_gen4_hw_init(struct fg_gen4_chip *chip)

{

	struct fg_dev *fg = &chip->fg;

	int rc;

	u8 buf[4], val;

	int rc;



	rc = fg_read(fg, ADC_RR_INT_RT_STS(fg), &val, 1);

	if (rc < 0) {
@@ -5080,64 +5248,9 @@ static int fg_gen4_hw_init(struct fg_gen4_chip *chip) 
		}

	}



	if (chip->dt.ki_coeff_low_chg != -EINVAL) {

		fg_encode(fg->sp, FG_SRAM_KI_COEFF_LOW_CHG,

			chip->dt.ki_coeff_low_chg, &val);

		rc = fg_sram_write(fg,

			fg->sp[FG_SRAM_KI_COEFF_LOW_CHG].addr_word,

			fg->sp[FG_SRAM_KI_COEFF_LOW_CHG].addr_byte, &val,

			fg->sp[FG_SRAM_KI_COEFF_LOW_CHG].len,

			FG_IMA_DEFAULT);

		if (rc < 0) {

			pr_err("Error in writing ki_coeff_low_chg, rc=%d\n",

				rc);

			return rc;

		}

	}



	if (chip->dt.ki_coeff_med_chg != -EINVAL) {

		fg_encode(fg->sp, FG_SRAM_KI_COEFF_MED_CHG,

			chip->dt.ki_coeff_med_chg, &val);

		rc = fg_sram_write(fg,

			fg->sp[FG_SRAM_KI_COEFF_MED_CHG].addr_word,

			fg->sp[FG_SRAM_KI_COEFF_MED_CHG].addr_byte, &val,

			fg->sp[FG_SRAM_KI_COEFF_MED_CHG].len,

			FG_IMA_DEFAULT);

		if (rc < 0) {

			pr_err("Error in writing ki_coeff_med_chg, rc=%d\n",

				rc);

			return rc;

		}

	}



	if (chip->dt.ki_coeff_hi_chg != -EINVAL) {

		fg_encode(fg->sp, FG_SRAM_KI_COEFF_HI_CHG,

			chip->dt.ki_coeff_hi_chg, &val);

		rc = fg_sram_write(fg,

			fg->sp[FG_SRAM_KI_COEFF_HI_CHG].addr_word,

			fg->sp[FG_SRAM_KI_COEFF_HI_CHG].addr_byte, &val,

			fg->sp[FG_SRAM_KI_COEFF_HI_CHG].len,

			FG_IMA_DEFAULT);

		if (rc < 0) {

			pr_err("Error in writing ki_coeff_hi_chg, rc=%d\n", rc);

			return rc;

		}

	}



	if (chip->dt.ki_coeff_cutoff_gain != -EINVAL) {

		fg_encode(fg->sp, FG_SRAM_KI_COEFF_CUTOFF,

			  chip->dt.ki_coeff_cutoff_gain, &val);

		rc = fg_sram_write(fg,

			fg->sp[FG_SRAM_KI_COEFF_CUTOFF].addr_word,

			fg->sp[FG_SRAM_KI_COEFF_CUTOFF].addr_byte, &val,

			fg->sp[FG_SRAM_KI_COEFF_CUTOFF].len,

			FG_IMA_DEFAULT);

		if (rc < 0) {

			pr_err("Error in writing ki_coeff_cutoff_gain, rc=%d\n",

				rc);

	rc = fg_gen4_init_ki_coeffts(chip);

	if (rc < 0)

		return rc;

		}

	}



	rc = fg_gen4_esr_calib_config(chip);

	if (rc < 0)
@@ -5199,6 +5312,9 @@ static int fg_parse_ki_coefficients(struct fg_dev *fg) 
	struct device_node *node = fg->dev->of_node;

	int rc, i;



	chip->dt.ki_coeff_full_soc_dischg[0] = KI_COEFF_FULL_SOC_NORM_DEFAULT;

	chip->dt.ki_coeff_full_soc_dischg[1] = KI_COEFF_FULL_SOC_LOW_DEFAULT;



	if (of_find_property(node, "qcom,ki-coeff-full-dischg", NULL)) {

		rc = fg_parse_dt_property_u32_array(node,

			"qcom,ki-coeff-full-dischg",
@@ -5215,22 +5331,44 @@ static int fg_parse_ki_coefficients(struct fg_dev *fg) 
		}

	}



	chip->dt.ki_coeff_low_chg = -EINVAL;

	chip->dt.ki_coeff_low_chg = 183;

	of_property_read_u32(node, "qcom,ki-coeff-low-chg",

		&chip->dt.ki_coeff_low_chg);



	chip->dt.ki_coeff_med_chg = -EINVAL;

	chip->dt.ki_coeff_med_chg = 62;

	of_property_read_u32(node, "qcom,ki-coeff-med-chg",

		&chip->dt.ki_coeff_med_chg);



	chip->dt.ki_coeff_hi_chg = -EINVAL;

	chip->dt.ki_coeff_hi_chg = 0;

	of_property_read_u32(node, "qcom,ki-coeff-hi-chg",

		&chip->dt.ki_coeff_hi_chg);



	chip->dt.ki_coeff_lo_med_chg_thr_ma = 1000;

	of_property_read_u32(node, "qcom,ki-coeff-chg-low-med-thresh-ma",

		&chip->dt.ki_coeff_lo_med_chg_thr_ma);



	chip->dt.ki_coeff_med_hi_chg_thr_ma = 1500;

	of_property_read_u32(node, "qcom,ki-coeff-chg-med-hi-thresh-ma",

		&chip->dt.ki_coeff_med_hi_chg_thr_ma);



	chip->dt.ki_coeff_lo_med_dchg_thr_ma = 50;

	of_property_read_u32(node, "qcom,ki-coeff-dischg-low-med-thresh-ma",

		&chip->dt.ki_coeff_lo_med_dchg_thr_ma);



	chip->dt.ki_coeff_med_hi_dchg_thr_ma = 100;

	of_property_read_u32(node, "qcom,ki-coeff-dischg-med-hi-thresh-ma",

		&chip->dt.ki_coeff_med_hi_dchg_thr_ma);



	chip->dt.ki_coeff_cutoff_gain = -EINVAL;

	of_property_read_u32(node, "qcom,ki-coeff-cutoff",

		&chip->dt.ki_coeff_cutoff_gain);



	for (i = 0; i < KI_COEFF_SOC_LEVELS; i++) {

		chip->dt.ki_coeff_low_dischg[i] = KI_COEFF_LOW_DISCHG_DEFAULT;

		chip->dt.ki_coeff_med_dischg[i] = KI_COEFF_MED_DISCHG_DEFAULT;

		chip->dt.ki_coeff_hi_dischg[i] = KI_COEFF_HI_DISCHG_DEFAULT;

	}



	if (!of_find_property(node, "qcom,ki-coeff-soc-dischg", NULL) ||

		(!of_find_property(node, "qcom,ki-coeff-low-dischg", NULL) &&

		!of_find_property(node, "qcom,ki-coeff-med-dischg", NULL) &&