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Commit ef0c4b11 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: make DisplayPort PLL modules configurable"

parents c4349179 19742543

drivers/clk/qcom/mdss/Kconfig

+8 −0
Original line number Diff line number Diff line
@@ -7,3 +7,11 @@ config QCOM_MDSS_PLL 
	It provides support for DSI, eDP and HDMI interface pll programming on MDSS

	hardware. It also handles the pll specific resources and turn them on/off when

	mdss pll client tries to enable/disable pll clocks.



config QCOM_MDSS_DP_PLL

	bool "MDSS DisplayPort PLL programming"

	depends on QCOM_MDSS_PLL

	default n

	help

	This flag enables the modules for DisplayPort (DP) PLL programming and is

	required for all targets that support DP.

drivers/clk/qcom/mdss/Makefile

+6 −5
Original line number Diff line number Diff line
@@ -3,13 +3,14 @@ 
obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-pll-util.o

obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-pll.o

obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dsi-pll-10nm.o

obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dp-pll-10nm.o

obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dp-pll-10nm-util.o

obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dsi-pll-7nm.o

obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dp-pll-7nm.o

obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dp-pll-7nm-util.o

obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dsi-pll-28lpm.o

obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dsi-pll-28nm-util.o

obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dsi-pll-14nm.o

obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dsi-pll-14nm-util.o

obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dp-pll-14nm.o
 


obj-$(CONFIG_QCOM_MDSS_DP_PLL) += mdss-dp-pll-7nm.o \

	mdss-dp-pll-7nm-util.o \

	mdss-dp-pll-10nm.o \

	mdss-dp-pll-10nm-util.o \

	mdss-dp-pll-14nm.o \

drivers/clk/qcom/mdss/mdss-dp-pll.h

+20 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.

 */



#ifndef __MDSS_DP_PLL_H
@@ -19,6 +19,7 @@ static inline struct dp_pll_vco_clk *to_dp_vco_hw(struct clk_hw *hw) 
	return container_of(hw, struct dp_pll_vco_clk, hw);

}



#ifdef CONFIG_QCOM_MDSS_DP_PLL

int dp_pll_clock_register_14nm(struct platform_device *pdev,

				struct mdss_pll_resources *pll_res);
@@ -27,5 +28,23 @@ int dp_pll_clock_register_10nm(struct platform_device *pdev, 


int dp_pll_clock_register_7nm(struct platform_device *pdev,

				struct mdss_pll_resources *pll_res);

#else

static inline int dp_pll_clock_register_14nm(struct platform_device *pdev,

				struct mdss_pll_resources *pll_res)

{

	return 0;

}



static inline int dp_pll_clock_register_10nm(struct platform_device *pdev,

				struct mdss_pll_resources *pll_res)

{

	return 0;

}



static inline int dp_pll_clock_register_7nm(struct platform_device *pdev,

				struct mdss_pll_resources *pll_res)

{

	return 0;

}

#endif

#endif /* __MDSS_DP_PLL_H */