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Commit eeb1efbc authored by Marc Zyngier's avatar Marc Zyngier
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arm64: cpu_errata: Add capability to advertise Cortex-A73 erratum 858921 



In order to work around Cortex-A73 erratum 858921 in a subsequent
patch, add the required capability that advertise the erratum.

As the configuration option it depends on is not present yet,
this has no immediate effect.

Acked-by: default avatarThomas Gleixner <tglx@linutronix.de>
Acked-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent 06f1494f

Documentation/arm64/silicon-errata.txt

+1 −0
Original line number Diff line number Diff line
@@ -54,6 +54,7 @@ stable kernels. 
| ARM            | Cortex-A57      | #852523         | N/A                         |

| ARM            | Cortex-A57      | #834220         | ARM64_ERRATUM_834220        |

| ARM            | Cortex-A72      | #853709         | N/A                         |

| ARM            | Cortex-A73      | #858921         | ARM64_ERRATUM_858921        |

| ARM            | MMU-500         | #841119,#826419 | N/A                         |

|                |                 |                 |                             |

| Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375        |

arch/arm64/include/asm/cpucaps.h

+2 −1
Original line number Diff line number Diff line
@@ -37,7 +37,8 @@ 
#define ARM64_HAS_NO_FPSIMD			16

#define ARM64_WORKAROUND_REPEAT_TLBI		17

#define ARM64_WORKAROUND_QCOM_FALKOR_E1003	18

#define ARM64_WORKAROUND_858921			19



#define ARM64_NCAPS				19

#define ARM64_NCAPS				20



#endif /* __ASM_CPUCAPS_H */

arch/arm64/kernel/cpu_errata.c

+8 −0
Original line number Diff line number Diff line
@@ -157,6 +157,14 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
			   MIDR_CPU_VAR_REV(0, 0),

			   MIDR_CPU_VAR_REV(0, 0)),

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_858921

	{

	/* Cortex-A73 all versions */

		.desc = "ARM erratum 858921",

		.capability = ARM64_WORKAROUND_858921,

		MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),

	},

#endif

	{

	}