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Commit ee0ebe81 authored by Lars-Peter Clausen's avatar Lars-Peter Clausen Committed by Mark Brown
Browse files

spi: cadence: Fix 3-to-8 mux mode 



In 3-to-8 mux mode for the CS pins we need to set the PERI_SEL bit in the
control register. Currently the driver never sets this bit even when
configured for 3-to-8 mux mode. This patch adds code which sets the bit
during device initialization when necessary.

Signed-off-by: default avatarLars-Peter Clausen <lars@metafoo.de>
Acked-by: default avatarHarini Katakam <harinik@xilinx.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent f114040e

drivers/spi/spi-cadence.c

+7 −2
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ 
#define CDNS_SPI_CR_CPHA_MASK		0x00000004 /* Clock Phase Control */

#define CDNS_SPI_CR_CPOL_MASK		0x00000002 /* Clock Polarity Control */

#define CDNS_SPI_CR_SSCTRL_MASK		0x00003C00 /* Slave Select Mask */

#define CDNS_SPI_CR_PERI_SEL_MASK	0x00000200 /* Peripheral Select Decode */

#define CDNS_SPI_CR_BAUD_DIV_MASK	0x00000038 /* Baud Rate Divisor Mask */

#define CDNS_SPI_CR_MSTREN_MASK		0x00000001 /* Master Enable Mask */

#define CDNS_SPI_CR_MANSTRTEN_MASK	0x00008000 /* Manual TX Enable Mask */
@@ -148,6 +149,11 @@ static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val) 
 */

static void cdns_spi_init_hw(struct cdns_spi *xspi)

{

	u32 ctrl_reg = CDNS_SPI_CR_DEFAULT_MASK;



	if (xspi->is_decoded_cs)

		ctrl_reg |= CDNS_SPI_CR_PERI_SEL_MASK;



	cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,

		       CDNS_SPI_ER_DISABLE_MASK);

	cdns_spi_write(xspi, CDNS_SPI_IDR_OFFSET,
@@ -160,8 +166,7 @@ static void cdns_spi_init_hw(struct cdns_spi *xspi) 


	cdns_spi_write(xspi, CDNS_SPI_ISR_OFFSET,

		       CDNS_SPI_IXR_ALL_MASK);

	cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET,

		       CDNS_SPI_CR_DEFAULT_MASK);

	cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, ctrl_reg);

	cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,

		       CDNS_SPI_ER_ENABLE_MASK);

}