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Commit ed8d60f4 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915: Check DDI max lanes after applying BXT workaround 



In commit bfb9faab8 we added a workaround for some BXT BIOS that fail to
properly initialize the DDI_A_4_LANES bit of the control register (4
lanes is the only valid configuration on BXT since there is no DDI E to
share with).  A recent patch added some additional checks on this
register bit before the workaround gets applied; this breaks eDP on BXT
in some settings.  Some minor code shuffling is all we need to restore
the workaround.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Fixes: 7cd87cb80 ("drm/i915: Check max number of lanes when registering DDI ports")
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1454022577-834-1-git-send-email-matthew.d.roper@intel.com


Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
parent e1ea0754

drivers/gpu/drm/i915/intel_ddi.c

+3 −1
Original line number Diff line number Diff line
@@ -3281,7 +3281,6 @@ void intel_ddi_init(struct drm_device *dev, enum port port) 
	intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &

					  (DDI_BUF_PORT_REVERSAL |

					   DDI_A_4_LANES);

	intel_dig_port->max_lanes = max_lanes;



	/*

	 * Bspec says that DDI_A_4_LANES is the only supported configuration
@@ -3294,9 +3293,12 @@ void intel_ddi_init(struct drm_device *dev, enum port port) 
		if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {

			DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");

			intel_dig_port->saved_port_bits |= DDI_A_4_LANES;

			max_lanes = 4;

		}

	}



	intel_dig_port->max_lanes = max_lanes;



	intel_encoder->type = INTEL_OUTPUT_UNKNOWN;

	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);

	intel_encoder->cloneable = 0;