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Commit ed73c2e2 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: qcom: Enable phy regulators for atoll"

parents f41f0b2d 33ca61ef

Documentation/devicetree/bindings/media/video/msm-cam-csiphy.txt

+2 −1
Original line number Diff line number Diff line
@@ -15,7 +15,8 @@ First Level Node - CSIPHY device 
  Value type: <string>

  Definition: Should be "qcom,csiphy-v1.0",

	"qcom,csiphy-v1.1", "qcom,csiphy-v1.2",

	"qcom,csiphy-v2.0", "qcom,csiphy".

	"qcom,csiphy-v1.2.2", "qcom,csiphy-v2.0",

        "qcom,csiphy".



- cell-index: csiphy hardware core index

  Usage: required

arch/arm64/boot/dts/qcom/atoll-camera.dtsi

+372 −0
Original line number Diff line number Diff line
@@ -17,6 +17,378 @@ 
		status = "ok";

	};



	cam_csiphy0: qcom,csiphy@ac65000 {

		cell-index = <0>;

		compatible = "qcom,csiphy-v1.2.2", "qcom,csiphy";

		reg = <0x0ac65000 0x1000>;

		reg-names = "csiphy";

		reg-cam-base = <0x65000>;

		interrupts = <0 477 0>;

		interrupt-names = "csiphy";

		regulator-names = "gdscr", "refgen",

			"mipi-csi-vdd1", "mipi-csi-vdd2";

		gdscr-supply = <&titan_top_gdsc>;

		refgen-supply = <&refgen>;

		mipi-csi-vdd1-supply = <&L4A>;

		mipi-csi-vdd2-supply = <&L3C>;

		rgltr-cntrl-support;

		rgltr-min-voltage = <0 0 900000 1200000>;

		rgltr-max-voltage = <0 0 900000 1200000>;

		rgltr-load-current = <0 0 80000 80000>;

		clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,

			<&clock_camcc CAM_CC_SOC_AHB_CLK>,

			<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,

			<&clock_camcc CAM_CC_CPAS_AHB_CLK>,

			<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,

			<&clock_camcc CAM_CC_CSIPHY0_CLK>,

			<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,

			<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>;

		clock-names = "camnoc_axi_clk",

			"soc_ahb_clk",

			"slow_ahb_src_clk",

			"cpas_ahb_clk",

			"cphy_rx_clk_src",

			"csiphy0_clk",

			"csi0phytimer_clk_src",

			"csi0phytimer_clk";

		src-clock-name = "csi0phytimer_clk_src";

		clock-cntl-level = "svs", "svs_l1", "turbo";

		clock-rates =

			<0 0 0 0 270000000 0 300000000 0>,

			<0 0 0 0 360000000 0 300000000 0>,

			<0 0 0 0 360000000 0 300000000 0>;

		status = "ok";

	};



	cam_csiphy1: qcom,csiphy@ac66000{

		cell-index = <1>;

		compatible = "qcom,csiphy-v1.2.2", "qcom,csiphy";

		reg = <0xac66000 0x1000>;

		reg-names = "csiphy";

		reg-cam-base = <0x66000>;

		interrupts = <0 478 0>;

		interrupt-names = "csiphy";

		regulator-names = "gdscr", "refgen",

			"mipi-csi-vdd1", "mipi-csi-vdd2";

		gdscr-supply = <&titan_top_gdsc>;

		refgen-supply = <&refgen>;

		mipi-csi-vdd1-supply = <&L4A>;

		mipi-csi-vdd2-supply = <&L3C>;

		rgltr-cntrl-support;

		rgltr-min-voltage = <0 0 900000 1200000>;

		rgltr-max-voltage = <0 0 900000 1200000>;

		rgltr-load-current = <0 0 80000 80000>;

		clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,

			<&clock_camcc CAM_CC_SOC_AHB_CLK>,

			<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,

			<&clock_camcc CAM_CC_CPAS_AHB_CLK>,

			<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,

			<&clock_camcc CAM_CC_CSIPHY1_CLK>,

			<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,

			<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>;

		clock-names = "camnoc_axi_clk",

			"soc_ahb_clk",

			"slow_ahb_src_clk",

			"cpas_ahb_clk",

			"cphy_rx_clk_src",

			"csiphy1_clk",

			"csi1phytimer_clk_src",

			"csi1phytimer_clk";

		src-clock-name = "csi1phytimer_clk_src";

		clock-cntl-level = "svs", "svs_l1", "turbo";

		clock-rates =

			<0 0 0 0 270000000 0 300000000 0>,

			<0 0 0 0 360000000 0 300000000 0>,

			<0 0 0 0 360000000 0 300000000 0>;

		status = "ok";

	};



	cam_csiphy2: qcom,csiphy@ac67000 {

		cell-index = <2>;

		compatible = "qcom,csiphy-v1.2.2", "qcom,csiphy";

		reg = <0xac67000 0x1000>;

		reg-names = "csiphy";

		reg-cam-base = <0x67000>;

		interrupts = <0 479 0>;

		interrupt-names = "csiphy";

		regulator-names = "gdscr", "refgen",

			"mipi-csi-vdd1", "mipi-csi-vdd2";

		gdscr-supply = <&titan_top_gdsc>;

		refgen-supply = <&refgen>;

		mipi-csi-vdd1-supply = <&L4A>;

		mipi-csi-vdd2-supply = <&L3C>;

		rgltr-cntrl-support;

		rgltr-min-voltage = <0 0 900000 1200000>;

		rgltr-max-voltage = <0 0 900000 1200000>;

		rgltr-load-current = <0 0 80000 80000>;

		clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,

			<&clock_camcc CAM_CC_SOC_AHB_CLK>,

			<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,

			<&clock_camcc CAM_CC_CPAS_AHB_CLK>,

			<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,

			<&clock_camcc CAM_CC_CSIPHY2_CLK>,

			<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,

			<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>;

		clock-names = "camnoc_axi_clk",

			"soc_ahb_clk",

			"slow_ahb_src_clk",

			"cpas_ahb_clk",

			"cphy_rx_clk_src",

			"csiphy2_clk",

			"csi2phytimer_clk_src",

			"csi2phytimer_clk";

		src-clock-name = "csi2phytimer_clk_src";

		clock-cntl-level = "svs", "svs_l1", "turbo";

		clock-rates =

			<0 0 0 0 270000000 0 300000000 0>,

			<0 0 0 0 360000000 0 300000000 0>,

			<0 0 0 0 360000000 0 300000000 0>;

		status = "ok";

	};



	cam_csiphy3: qcom,csiphy@ac68000 {

		cell-index = <2>;

		compatible = "qcom,csiphy-v1.2.2", "qcom,csiphy";

		reg = <0xac68000 0x1000>;

		reg-names = "csiphy";

		reg-cam-base = <0x68000>;

		interrupts = <0 461 0>;

		interrupt-names = "csiphy";

		regulator-names = "gdscr", "refgen",

			"mipi-csi-vdd1", "mipi-csi-vdd2";

		gdscr-supply = <&titan_top_gdsc>;

		refgen-supply = <&refgen>;

		mipi-csi-vdd1-supply = <&L4A>;

		mipi-csi-vdd2-supply = <&L3C>;

		rgltr-cntrl-support;

		rgltr-min-voltage = <0 0 900000 1200000>;

		rgltr-max-voltage = <0 0 900000 1200000>;

		rgltr-load-current = <0 0 80000 80000>;

		clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,

			<&clock_camcc CAM_CC_SOC_AHB_CLK>,

			<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,

			<&clock_camcc CAM_CC_CPAS_AHB_CLK>,

			<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,

			<&clock_camcc CAM_CC_CSIPHY3_CLK>,

			<&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,

			<&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>;

		clock-names = "camnoc_axi_clk",

			"soc_ahb_clk",

			"slow_ahb_src_clk",

			"cpas_ahb_clk",

			"cphy_rx_clk_src",

			"csiphy3_clk",

			"csi3phytimer_clk_src",

			"csi3phytimer_clk";

		src-clock-name = "csi3phytimer_clk_src";

		clock-cntl-level = "svs", "svs_l1", "turbo";

		clock-rates =

			<0 0 0 0 270000000 0 300000000 0>,

			<0 0 0 0 360000000 0 300000000 0>,

			<0 0 0 0 360000000 0 300000000 0>;

		status = "ok";

	};



	cam_cci0: qcom,cci@ac4a000 {

		cell-index = <0>;

		compatible = "qcom,cci";

		reg = <0xac4a000 0x1000>;

		reg-names = "cci";

		reg-cam-base = <0x4a000>;

		interrupt-names = "cci";

		interrupts = <0 468 0>;

		status = "ok";

		gdscr-supply = <&titan_top_gdsc>;

		regulator-names = "gdscr";

		clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,

			<&clock_camcc CAM_CC_SOC_AHB_CLK>,

			<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,

			<&clock_camcc CAM_CC_CPAS_AHB_CLK>,

			<&clock_camcc CAM_CC_CCI_0_CLK>,

			<&clock_camcc CAM_CC_CCI_0_CLK_SRC>;

		clock-names = "camnoc_axi_clk",

			"soc_ahb_clk",

			"slow_ahb_src_clk",

			"cpas_ahb_clk",

			"cci_clk",

			"cci_clk_src";

		src-clock-name = "cci_clk_src";

		clock-cntl-level = "lowsvs";

		clock-rates = <0 0 0 0 0 37500000>;

		pinctrl-names = "cam_default", "cam_suspend";

		pinctrl-0 = <&cci0_active &cci1_active>;

		pinctrl-1 = <&cci0_suspend &cci1_suspend>;

		gpios = <&tlmm 17 0>,

			<&tlmm 18 0>,

			<&tlmm 19 0>,

			<&tlmm 20 0>;

		gpio-req-tbl-num = <0 1 2 3>;

		gpio-req-tbl-flags = <1 1 1 1>;

		gpio-req-tbl-label = "CCI_I2C_DATA0",

					"CCI_I2C_CLK0",

					"CCI_I2C_DATA1",

					"CCI_I2C_CLK1";



		i2c_freq_100Khz: qcom,i2c_standard_mode {

			hw-thigh = <201>;

			hw-tlow = <174>;

			hw-tsu-sto = <204>;

			hw-tsu-sta = <231>;

			hw-thd-dat = <22>;

			hw-thd-sta = <162>;

			hw-tbuf = <227>;

			hw-scl-stretch-en = <0>;

			hw-trdhld = <6>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};



		i2c_freq_400Khz: qcom,i2c_fast_mode {

			hw-thigh = <38>;

			hw-tlow = <56>;

			hw-tsu-sto = <40>;

			hw-tsu-sta = <40>;

			hw-thd-dat = <22>;

			hw-thd-sta = <35>;

			hw-tbuf = <62>;

			hw-scl-stretch-en = <0>;

			hw-trdhld = <6>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};



		i2c_freq_custom: qcom,i2c_custom_mode {

			hw-thigh = <38>;

			hw-tlow = <56>;

			hw-tsu-sto = <40>;

			hw-tsu-sta = <40>;

			hw-thd-dat = <22>;

			hw-thd-sta = <35>;

			hw-tbuf = <62>;

			hw-scl-stretch-en = <1>;

			hw-trdhld = <6>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};



		i2c_freq_1Mhz: qcom,i2c_fast_plus_mode {

			hw-thigh = <16>;

			hw-tlow = <22>;

			hw-tsu-sto = <17>;

			hw-tsu-sta = <18>;

			hw-thd-dat = <16>;

			hw-thd-sta = <15>;

			hw-tbuf = <24>;

			hw-scl-stretch-en = <0>;

			hw-trdhld = <3>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};

	};



	cam_cci1: qcom,cci@ac4b000 {

		cell-index = <1>;

		compatible = "qcom,cci";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0xac4b000 0x1000>;

		reg-names = "cci";

		reg-cam-base = <0x4b000>;

		interrupt-names = "cci";

		interrupts = <0 462 0>;

		status = "ok";

		gdscr-supply = <&titan_top_gdsc>;

		regulator-names = "gdscr";

		clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,

			<&clock_camcc CAM_CC_SOC_AHB_CLK>,

			<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,

			<&clock_camcc CAM_CC_CPAS_AHB_CLK>,

			<&clock_camcc CAM_CC_CCI_1_CLK>,

			<&clock_camcc CAM_CC_CCI_1_CLK_SRC>;

		clock-names = "camnoc_axi_clk",

			"soc_ahb_clk",

			"slow_ahb_src_clk",

			"cpas_ahb_clk",

			"cci_clk",

			"cci_clk_src";

		src-clock-name = "cci_clk_src";

		clock-cntl-level = "lowsvs";

		clock-rates = <0 0 0 0 0 37500000>;

		pinctrl-names = "cam_default", "cam_suspend";

		pinctrl-0 = <&cci2_active>;

		pinctrl-1 = <&cci2_suspend>;

		gpios = <&tlmm 27 0>,

			<&tlmm 28 0>;

		gpio-req-tbl-num = <0 1>;

		gpio-req-tbl-flags = <1 1>;

		gpio-req-tbl-label = "CCI_I2C_DATA2",

					"CCI_I2C_CLK2";



		i2c_freq_100Khz_cci1: qcom,i2c_standard_mode {

			hw-thigh = <201>;

			hw-tlow = <174>;

			hw-tsu-sto = <204>;

			hw-tsu-sta = <231>;

			hw-thd-dat = <22>;

			hw-thd-sta = <162>;

			hw-tbuf = <227>;

			hw-scl-stretch-en = <0>;

			hw-trdhld = <6>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};



		i2c_freq_400Khz_cci1: qcom,i2c_fast_mode {

			hw-thigh = <38>;

			hw-tlow = <56>;

			hw-tsu-sto = <40>;

			hw-tsu-sta = <40>;

			hw-thd-dat = <22>;

			hw-thd-sta = <35>;

			hw-tbuf = <62>;

			hw-scl-stretch-en = <0>;

			hw-trdhld = <6>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};



		i2c_freq_custom_cci1: qcom,i2c_custom_mode {

			hw-thigh = <38>;

			hw-tlow = <56>;

			hw-tsu-sto = <40>;

			hw-tsu-sta = <40>;

			hw-thd-dat = <22>;

			hw-thd-sta = <35>;

			hw-tbuf = <62>;

			hw-scl-stretch-en = <1>;

			hw-trdhld = <6>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};



		i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode {

			hw-thigh = <16>;

			hw-tlow = <22>;

			hw-tsu-sto = <17>;

			hw-tsu-sta = <18>;

			hw-thd-dat = <16>;

			hw-thd-sta = <15>;

			hw-tbuf = <24>;

			hw-scl-stretch-en = <0>;

			hw-trdhld = <3>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};

	};



	qcom,cam_smmu {

		compatible = "qcom,msm-cam-smmu";

		status = "ok";