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Commit ecb50f0a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull irq core updates from Thomas Gleixner:
 "This is the first (boring) part of irq updates:

   - support for big endian I/O accessors in the generic irq chip

   - cleanup of brcmstb/bcm7120 drivers so they can be reused for non
     ARM SoCs

   - the usual pile of fixes and updates for the various ARM irq chips"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (25 commits)
  irqchip: dw-apb-ictl: Add PM support
  irqchip: dw-apb-ictl: Enable IRQ_GC_MASK_CACHE_PER_TYPE
  irqchip: dw-apb-ictl: Always use use {readl|writel}_relaxed
  ARM: orion: convert the irq_reg_{readl,writel} calls to the new API
  irqchip: atmel-aic: Add missing entry for rm9200 irq fixups
  irqchip: atmel-aic: Rename at91sam9_aic_irq_fixup for naming consistency
  irqchip: atmel-aic: Add specific irq fixup function for sam9g45 and sam9rl
  irqchip: atmel-aic: Add irq fixups for at91sam926x SoCs
  irqchip: atmel-aic: Add irq fixup for RTT block
  irqchip: brcmstb-l2: Convert driver to use irq_reg_{readl,writel}
  irqchip: bcm7120-l2: Convert driver to use irq_reg_{readl,writel}
  irqchip: bcm7120-l2: Decouple driver from brcmstb-l2
  irqchip: bcm7120-l2: Extend driver to support 64+ bit controllers
  irqchip: bcm7120-l2: Use gc->mask_cache to simplify suspend/resume functions
  irqchip: bcm7120-l2: Fix missing nibble in gc->unused mask
  irqchip: bcm7120-l2: Make sure all register accesses use base+offset
  irqchip: bcm7120-l2, brcmstb-l2: Remove ARM Kconfig dependency
  irqchip: bcm7120-l2: Eliminate bad IRQ check
  irqchip: brcmstb-l2: Eliminate dependency on ARM code
  genirq: Generic chip: Add big endian I/O accessors
  ...
parents a157508c 1655b053

Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt

+18 −8
Original line number Diff line number Diff line
@@ -13,7 +13,12 @@ Such an interrupt controller has the following hardware design: 
  or if they will output an interrupt signal at this 2nd level interrupt

  controller, in particular for UARTs



- not all 32-bits within the interrupt controller actually map to an interrupt

- typically has one 32-bit enable word and one 32-bit status word, but on

  some hardware may have more than one enable/status pair



- no atomic set/clear operations



- not all bits within the interrupt controller actually map to an interrupt



The typical hardware layout for this controller is represented below:
@@ -48,7 +53,9 @@ The typical hardware layout for this controller is represented below: 
Required properties:



- compatible: should be "brcm,bcm7120-l2-intc"

- reg: specifies the base physical address and size of the registers

- reg: specifies the base physical address and size of the registers;

  multiple pairs may be specified, with the first pair handling IRQ offsets

  0..31 and the second pair handling 32..63

- interrupt-controller: identifies the node as an interrupt controller

- #interrupt-cells: specifies the number of cells needed to encode an interrupt

  source, should be 1.
@@ -59,18 +66,21 @@ Required properties: 
- brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts

  are wired to this 2nd level interrupt controller, and how they match their

  respective interrupt parents. Should match exactly the number of interrupts

  specified in the 'interrupts' property.

  specified in the 'interrupts' property, multiplied by the number of

  enable/status register pairs implemented by this controller.  For

  multiple parent IRQs with multiple enable/status words, this looks like:

  <irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...>



Optional properties:



- brcm,irq-can-wake: if present, this means the L2 controller can be used as a

  wakeup source for system suspend/resume.



- brcm,int-fwd-mask: if present, a 32-bits bit mask to configure for the

  interrupts which have a mux gate, typically UARTs. Setting these bits will

  make their respective interrupts outputs bypass this 2nd level interrupt

  controller completely, it completely transparent for the interrupt controller

  parent

- brcm,int-fwd-mask: if present, a bit mask to configure the interrupts which

  have a mux gate, typically UARTs. Setting these bits will make their

  respective interrupt outputs bypass this 2nd level interrupt controller

  completely; it is completely transparent for the interrupt controller

  parent. This should have one 32-bit word per enable/status pair.



Example:

arch/arm/mach-bcm/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -143,6 +143,7 @@ config ARCH_BRCMSTB 
	select HAVE_ARM_ARCH_TIMER

	select BRCMSTB_GISB_ARB

	select BRCMSTB_L2_IRQ

	select BCM7120_L2_IRQ

	help

	  Say Y if you intend to run the kernel on a Broadcom ARM-based STB

	  chipset.

arch/arm/plat-orion/gpio.c

+4 −4
Original line number Diff line number Diff line
@@ -505,9 +505,9 @@ static void orion_gpio_unmask_irq(struct irq_data *d) 
	u32 mask = d->mask;



	irq_gc_lock(gc);

	reg_val = irq_reg_readl(gc->reg_base + ct->regs.mask);

	reg_val = irq_reg_readl(gc, ct->regs.mask);

	reg_val |= mask;

	irq_reg_writel(reg_val, gc->reg_base + ct->regs.mask);

	irq_reg_writel(gc, reg_val, ct->regs.mask);

	irq_gc_unlock(gc);

}
@@ -519,9 +519,9 @@ static void orion_gpio_mask_irq(struct irq_data *d) 
	u32 reg_val;



	irq_gc_lock(gc);

	reg_val = irq_reg_readl(gc->reg_base + ct->regs.mask);

	reg_val = irq_reg_readl(gc, ct->regs.mask);

	reg_val &= ~mask;

	irq_reg_writel(reg_val, gc->reg_base + ct->regs.mask);

	irq_reg_writel(gc, reg_val, ct->regs.mask);

	irq_gc_unlock(gc);

}

drivers/irqchip/Kconfig

+6 −1
Original line number Diff line number Diff line
@@ -48,14 +48,19 @@ config ATMEL_AIC5_IRQ 
	select MULTI_IRQ_HANDLER

	select SPARSE_IRQ



config BCM7120_L2_IRQ

	bool

	select GENERIC_IRQ_CHIP

	select IRQ_DOMAIN



config BRCMSTB_L2_IRQ

	bool

	depends on ARM

	select GENERIC_IRQ_CHIP

	select IRQ_DOMAIN



config DW_APB_ICTL

	bool

	select GENERIC_IRQ_CHIP

	select IRQ_DOMAIN



config IMGPDC_IRQ

drivers/irqchip/Makefile

+2 −2
Original line number Diff line number Diff line
@@ -35,6 +35,6 @@ obj-$(CONFIG_TB10X_IRQC) += irq-tb10x.o 
obj-$(CONFIG_XTENSA)			+= irq-xtensa-pic.o

obj-$(CONFIG_XTENSA_MX)			+= irq-xtensa-mx.o

obj-$(CONFIG_IRQ_CROSSBAR)		+= irq-crossbar.o

obj-$(CONFIG_BRCMSTB_L2_IRQ)		+= irq-brcmstb-l2.o \

					   irq-bcm7120-l2.o

obj-$(CONFIG_BCM7120_L2_IRQ)		+= irq-bcm7120-l2.o

obj-$(CONFIG_BRCMSTB_L2_IRQ)		+= irq-brcmstb-l2.o

obj-$(CONFIG_KEYSTONE_IRQ)		+= irq-keystone.o