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Commit ec8d33c4 authored by Archit Saxena's avatar Archit Saxena
Browse files

ARM: dts: msm: Add pil nodes to sdm429 



Add pil nodes for sdm429 bringup.

Change-Id: I3d92564ec751eb317cebe68daf8cd875d352f794
Signed-off-by: default avatarArchit Saxena <archsaxe@codeaurora.org>
parent 6bddfdd3

arch/arm64/boot/dts/qcom/sdm429.dtsi

+162 −5
Original line number Original line Diff line number Diff line
@@ -16,6 +16,7 @@ 
#include <dt-bindings/clock/qcom,gcc-sdm429w.h>

#include <dt-bindings/clock/qcom,gcc-sdm429w.h>

#include <dt-bindings/clock/qcom,rpmcc.h>

#include <dt-bindings/clock/qcom,rpmcc.h>

#include <dt-bindings/clock/mdss-12nm-pll-clk.h>

#include <dt-bindings/clock/mdss-12nm-pll-clk.h>

#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>





/ {

/ {

	model = "Qualcomm Technologies, Inc. SDM429";

	model = "Qualcomm Technologies, Inc. SDM429";
@@ -505,6 +506,162 @@ 
		};

		};

	};

	};





	qcom,lpass@c000000 {

		compatible = "qcom,pil-tz-generic";

		reg = <0xc000000 0x00100>;



		vdd_cx-supply = <&pm660_s2_level>;

		qcom,proxy-reg-names = "vdd_cx";

		qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;



		clocks = <&rpmcc CXO_SMD_PIL_LPASS_CLK>,

			<&gcc GCC_CRYPTO_CLK>,

			<&gcc GCC_CRYPTO_AHB_CLK>,

			<&gcc GCC_CRYPTO_AXI_CLK>,

			<&gcc CRYPTO_CLK_SRC>;



		qcom,scm_core_clk_src-freq = <80000000>;

		clock-names = "xo", "scm_core_clk", "scm_iface_clk",

			"scm_bus_clk", "scm_core_clk_src";

		qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk",

			"scm_bus_clk", "scm_core_clk_src";



		qcom,pas-id = <1>;

		qcom,mas-crypto = <&mas_crypto>;

		qcom,complete-ramdump;

		qcom,proxy-timeout-ms = <10000>;

		qcom,smem-id = <423>;

		qcom,sysmon-id = <1>;

		qcom,ssctl-instance-id = <0x14>;

		qcom,firmware-name = "adsp";



		/* GPIO inputs from lpass */

		interrupts-extended = <&intc 0 293 1>,

				<&adsp_smp2p_in 0 0>,

				<&adsp_smp2p_in 2 0>,

				<&adsp_smp2p_in 1 0>,

				<&adsp_smp2p_in 3 0>;



		interrupt-names = "qcom,wdog",

				"qcom,err-fatal",

				"qcom,proxy-unvote",

				"qcom,err-ready",

				"qcom,stop-ack";

		/* GPIO output to lpass */

		qcom,smem-states = <&adsp_smp2p_out 0>;

		qcom,smem-state-names = "qcom,force-stop";

		memory-region = <&adsp_fw_mem>;

	};



	qcom,pronto@a21b000 {

		compatible = "qcom,pil-tz-generic";

		reg = <0x0a21b000 0x3000>;



		vdd_pronto_pll-supply = <&pm660_l12>;

		qcom,proxy-reg-names = "vdd_pronto_pll";

		qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;



		clocks = <&rpmcc CXO_SMD_PIL_PRONTO_CLK>,

			<&gcc GCC_CRYPTO_CLK>,

			<&gcc GCC_CRYPTO_AHB_CLK>,

			<&gcc GCC_CRYPTO_AXI_CLK>,

			<&gcc CRYPTO_CLK_SRC>;

		clock-names = "xo", "scm_core_clk", "scm_iface_clk",

				"scm_bus_clk", "scm_core_clk_src";

		qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk",

					"scm_bus_clk", "scm_core_clk_src";

		qcom,pas-id = <6>;

		qcom,mas-crypto = <&mas_crypto>;

		qcom,proxy-timeout-ms = <10000>;

		qcom,smem-id = <422>;

		qcom,sysmon-id = <6>;

		qcom,ssctl-instance-id = <0x13>;

		qcom,firmware-name = "wcnss";



		/* GPIO inputs from wcnss */

		interrupts-extended = <&intc 0 149 1>,

				<&wcnss_smp2p_in 0 0>,

				<&wcnss_smp2p_in 2 0>,

				<&wcnss_smp2p_in 1 0>,

				<&wcnss_smp2p_in 3 0>,

				<&wcnss_smp2p_in 7 0>;



		interrupt-names = "qcom,wdog",

				"qcom,err-fatal",

				"qcom,proxy-unvote",

				"qcom,err-ready",

				"qcom,stop-ack",

				"qcom,shutdown-ack";



		/* GPIO output to wcnss */

		qcom,smem-states = <&wcnss_smp2p_out 0>;

		qcom,smem-state-names = "qcom,force-stop";

		memory-region = <&wcnss_fw_mem>;

	};



	pil_modem: qcom,mss@4080000 {

		compatible = "qcom,pil-q6v55-mss";

		reg =   <0x4080000 0x100>,

			<0x0194f000 0x010>,

			<0x01950000 0x008>,

			<0x01951000 0x008>,

			<0x04020000 0x040>,

			<0x01871000 0x004>;

		reg-names = "qdsp6_base", "halt_q6", "halt_modem",

			"halt_nc", "rmb_base", "restart_reg",

			"cxip_lm_vote_clear";



		clocks = <&rpmcc CXO_SMD_PIL_MSS_CLK>,

			<&gcc GCC_MSS_CFG_AHB_CLK>,

			<&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,

			<&gcc GCC_BOOT_ROM_AHB_CLK>;

		clock-names = "xo", "iface_clk", "bus_clk", "mem_clk";

		qcom,proxy-clock-names = "xo";

		qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk";



		vdd_mss-supply = <&S6A>;

		vdd_cx-supply = <&pm660_s1_level_ao>;

		vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>;

		vdd_mx-supply = <&pm660_s2_level_ao>;

		vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>;

		vdd_pll-supply = <&L12A>;

		qcom,vdd_pll = <1800000>;

		vdd_mss-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>;



		qcom,pas-id = <5>;

		qcom,pil-mss-memsetup;

		qcom,firmware-name = "modem";

		qcom,pil-self-auth;

		qcom,sequential-fw-load;

		qcom,override-acc-1 = <0x80800000>;

		qcom,sysmon-id = <0>;

		qcom,ssctl-instance-id = <0x12>;

		memory-region = <&modem_mem>;

		qcom,qdsp6v56-1-8-inrush-current;

		qcom,reset-clk;



		/* Inputs from mss */

		interrupts-extended = <&intc 0 24 1>,

				<&modem_smp2p_in 0 0>,

				<&modem_smp2p_in 2 0>,

				<&modem_smp2p_in 1 0>,

				<&modem_smp2p_in 3 0>,

				<&modem_smp2p_in 7 0>;



		interrupt-names = "qcom,wdog",

			"qcom,err-fatal",

			"qcom,proxy-unvote",

			"qcom,err-ready",

			"qcom,stop-ack",

			"qcom,shutdown-ack";



		/* Outputs to mss */

		qcom,smem-states = <&modem_smp2p_out 0>;

		qcom,smem-state-names = "qcom,force-stop";



		status = "ok";

	};



	rpm_bus: qcom,rpm-smd { };

	rpm_bus: qcom,rpm-smd { };





	usb_otg: usb@78db000 {

	usb_otg: usb@78db000 {