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Commit e9ed2c0a authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: qcom: Adding I2S parameters to HS-I2S node on SA8155"

parents 8429014f 36e4735d

arch/arm64/boot/dts/qcom/sa6155-adp-air.dtsi

+12 −2
Original line number Diff line number Diff line
@@ -64,8 +64,8 @@ 
		clock-names = "core_clk", "wr0_mem_clk",

			      "wr1_mem_clk", "wr2_mem_clk",

			      "csr_hclk";

		bit-clock-hz = <20000000>;

		interrupt-interval-ms = <10>;

		number-of-rate-detectors = <2>;

		rate-detector-interfaces = <0 1>;



		sdr0: qcom,hs0_i2s {

			compatible = "qcom,hsi2s-interface";
@@ -80,6 +80,11 @@ 
			iommus = <&apps_smmu 0x035C 0x0>;

			qcom,smmu-s1-bypass;

			qcom,iova-mapping = <0x0 0xFFFFFFFF>;

			bit-clock-hz = <12288000>;

			data-buffer-ms = <10>;

			bit-depth = <32>;

			spkr-channel-count = <2>;

			mic-channel-count = <2>;

		};



		sdr1: qcom,hs1_i2s {
@@ -95,6 +100,11 @@ 
			iommus = <&apps_smmu 0x035D 0x0>;

			qcom,smmu-s1-bypass;

			qcom,iova-mapping = <0x0 0xFFFFFFFF>;

			bit-clock-hz = <12288000>;

			data-buffer-ms = <10>;

			bit-depth = <32>;

			spkr-channel-count = <2>;

			mic-channel-count = <2>;

		};

	};

arch/arm64/boot/dts/qcom/sa6155-adp-star.dtsi

+12 −2
Original line number Diff line number Diff line
@@ -57,8 +57,8 @@ 
		clock-names = "core_clk", "wr0_mem_clk",

			      "wr1_mem_clk", "wr2_mem_clk",

			      "csr_hclk";

		bit-clock-hz = <20000000>;

		interrupt-interval-ms = <10>;

		number-of-rate-detectors = <2>;

		rate-detector-interfaces = <0 1>;



		sdr0: qcom,hs0_i2s {

			compatible = "qcom,hsi2s-interface";
@@ -73,6 +73,11 @@ 
			iommus = <&apps_smmu 0x035C 0x0>;

			qcom,smmu-s1-bypass;

			qcom,iova-mapping = <0x0 0xFFFFFFFF>;

			bit-clock-hz = <12288000>;

			data-buffer-ms = <10>;

			bit-depth = <32>;

			spkr-channel-count = <2>;

			mic-channel-count = <2>;

		};



		sdr1: qcom,hs1_i2s {
@@ -88,6 +93,11 @@ 
			iommus = <&apps_smmu 0x035D 0x0>;

			qcom,smmu-s1-bypass;

			qcom,iova-mapping = <0x0 0xFFFFFFFF>;

			bit-clock-hz = <12288000>;

			data-buffer-ms = <10>;

			bit-depth = <32>;

			spkr-channel-count = <2>;

			mic-channel-count = <2>;

		};

	};

arch/arm64/boot/dts/qcom/sa8155.dtsi

+17 −2
Original line number Diff line number Diff line
@@ -506,8 +506,8 @@ 
		      <0x17080000 0xE000>;

		reg-names = "lpa_if", "lpass_tcsr";

		interrupts = <GIC_SPI 267 0>;

		bit-clock-hz = <20000000>;

		interrupt-interval-ms = <10>;

		number-of-rate-detectors = <2>;

		rate-detector-interfaces = <0 1>;



		sdr0: qcom,hs0_i2s {

			compatible = "qcom,hsi2s-interface";
@@ -522,6 +522,11 @@ 
			iommus = <&apps_smmu 0x1B5C 0x0>;

			qcom,smmu-s1-bypass;

			qcom,iova-mapping = <0x0 0xFFFFFFFF>;

			bit-clock-hz = <12288000>;

			data-buffer-ms = <10>;

			bit-depth = <32>;

			spkr-channel-count = <2>;

			mic-channel-count = <2>;

		};



		sdr1: qcom,hs1_i2s {
@@ -537,6 +542,11 @@ 
			iommus = <&apps_smmu 0x1B5D 0x0>;

			qcom,smmu-s1-bypass;

			qcom,iova-mapping = <0x0 0xFFFFFFFF>;

			bit-clock-hz = <12288000>;

			data-buffer-ms = <10>;

			bit-depth = <32>;

			spkr-channel-count = <2>;

			mic-channel-count = <2>;

		};



		sdr2: qcom,hs2_i2s {
@@ -552,6 +562,11 @@ 
			iommus = <&apps_smmu 0x1B5E 0x0>;

			qcom,smmu-s1-bypass;

			qcom,iova-mapping = <0x0 0xFFFFFFFF>;

			bit-clock-hz = <12288000>;

			data-buffer-ms = <10>;

			bit-depth = <32>;

			spkr-channel-count = <2>;

			mic-channel-count = <2>;

		};

	};