Loading drivers/clk/qcom/debugcc-sm8150.c +3 −0 Original line number Diff line number Diff line Loading @@ -118,6 +118,7 @@ static const char *const debug_mux_parent_names[] = { "disp_cc_mdss_rscc_vsync_clk", "disp_cc_mdss_vsync_clk", "disp_cc_xo_clk", "measure_only_cdsp_clk", "measure_only_snoc_clk", "measure_only_cnoc_clk", "measure_only_mccc_clk", Loading Loading @@ -465,6 +466,8 @@ static struct clk_debug_mux gcc_debug_mux = { 0x14, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, { "disp_cc_xo_clk", 0x56, 1, DISP_CC, 0x36, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, { "measure_only_cdsp_clk", 0xDB, 2, GCC, 0xDB, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, { "measure_only_snoc_clk", 0x7, 1, GCC, 0x7, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 }, { "measure_only_cnoc_clk", 0x19, 1, GCC, Loading drivers/clk/qcom/gcc-sm8150.c +9 −0 Original line number Diff line number Diff line Loading @@ -177,6 +177,14 @@ static const char * const gcc_parent_names_7[] = { "core_bi_pll_test_se", }; static struct clk_dummy measure_only_cdsp_clk = { .rrate = 1000, .hw.init = &(struct clk_init_data){ .name = "measure_only_cdsp_clk", .ops = &clk_dummy_ops, }, }; static struct clk_dummy measure_only_snoc_clk = { .rrate = 1000, .hw.init = &(struct clk_init_data){ Loading Loading @@ -3899,6 +3907,7 @@ static struct clk_branch gcc_video_xo_clk = { }; struct clk_hw *gcc_sm8150_hws[] = { [MEASURE_ONLY_CDSP_CLK] = &measure_only_cdsp_clk.hw, [MEASURE_ONLY_SNOC_CLK] = &measure_only_snoc_clk.hw, [MEASURE_ONLY_CNOC_CLK] = &measure_only_cnoc_clk.hw, [MEASURE_ONLY_MCCC_CLK] = &measure_only_mccc_clk.hw, Loading include/dt-bindings/clock/qcom,gcc-sm8150.h +1 −0 Original line number Diff line number Diff line Loading @@ -254,5 +254,6 @@ #define MEASURE_ONLY_MCCC_CLK 2 #define MEASURE_ONLY_IPA_2X_CLK 3 #define MMCX_CLK 4 #define MEASURE_ONLY_CDSP_CLK 5 #endif Loading
drivers/clk/qcom/debugcc-sm8150.c +3 −0 Original line number Diff line number Diff line Loading @@ -118,6 +118,7 @@ static const char *const debug_mux_parent_names[] = { "disp_cc_mdss_rscc_vsync_clk", "disp_cc_mdss_vsync_clk", "disp_cc_xo_clk", "measure_only_cdsp_clk", "measure_only_snoc_clk", "measure_only_cnoc_clk", "measure_only_mccc_clk", Loading Loading @@ -465,6 +466,8 @@ static struct clk_debug_mux gcc_debug_mux = { 0x14, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, { "disp_cc_xo_clk", 0x56, 1, DISP_CC, 0x36, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, { "measure_only_cdsp_clk", 0xDB, 2, GCC, 0xDB, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, { "measure_only_snoc_clk", 0x7, 1, GCC, 0x7, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 }, { "measure_only_cnoc_clk", 0x19, 1, GCC, Loading
drivers/clk/qcom/gcc-sm8150.c +9 −0 Original line number Diff line number Diff line Loading @@ -177,6 +177,14 @@ static const char * const gcc_parent_names_7[] = { "core_bi_pll_test_se", }; static struct clk_dummy measure_only_cdsp_clk = { .rrate = 1000, .hw.init = &(struct clk_init_data){ .name = "measure_only_cdsp_clk", .ops = &clk_dummy_ops, }, }; static struct clk_dummy measure_only_snoc_clk = { .rrate = 1000, .hw.init = &(struct clk_init_data){ Loading Loading @@ -3899,6 +3907,7 @@ static struct clk_branch gcc_video_xo_clk = { }; struct clk_hw *gcc_sm8150_hws[] = { [MEASURE_ONLY_CDSP_CLK] = &measure_only_cdsp_clk.hw, [MEASURE_ONLY_SNOC_CLK] = &measure_only_snoc_clk.hw, [MEASURE_ONLY_CNOC_CLK] = &measure_only_cnoc_clk.hw, [MEASURE_ONLY_MCCC_CLK] = &measure_only_mccc_clk.hw, Loading
include/dt-bindings/clock/qcom,gcc-sm8150.h +1 −0 Original line number Diff line number Diff line Loading @@ -254,5 +254,6 @@ #define MEASURE_ONLY_MCCC_CLK 2 #define MEASURE_ONLY_IPA_2X_CLK 3 #define MMCX_CLK 4 #define MEASURE_ONLY_CDSP_CLK 5 #endif