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Commit e8263793 authored by Thor Thayer's avatar Thor Thayer Committed by Borislav Petkov
Browse files

EDAC, altera: Add Arria10 DMA support 



Add Altera Arria10 DMA FIFO memory support.

Signed-off-by: default avatarThor Thayer <tthayer@opensource.altera.com>
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1468512408-5156-7-git-send-email-tthayer@opensource.altera.com


Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
parent c6882fb2

drivers/edac/Kconfig

+7 −0
Original line number Original line Diff line number Diff line
@@ -405,6 +405,13 @@ config EDAC_ALTERA_NAND 
	  Support for error detection and correction on the

	  Support for error detection and correction on the

	  Altera NAND FIFO Memory for Altera SoCs.

	  Altera NAND FIFO Memory for Altera SoCs.





config EDAC_ALTERA_DMA

	bool "Altera DMA FIFO ECC"

	depends on EDAC_ALTERA=y && PL330_DMA=y

	help

	  Support for error detection and correction on the

	  Altera DMA FIFO Memory for Altera SoCs.



config EDAC_SYNOPSYS

config EDAC_SYNOPSYS

	tristate "Synopsys DDR Memory Controller"

	tristate "Synopsys DDR Memory Controller"

	depends on EDAC_MM_EDAC && ARCH_ZYNQ

	depends on EDAC_MM_EDAC && ARCH_ZYNQ

drivers/edac/altera_edac.c

+32 −1
Original line number Original line Diff line number Diff line
@@ -1312,6 +1312,33 @@ early_initcall(socfpga_init_nand_ecc); 




#endif	/* CONFIG_EDAC_ALTERA_NAND */

#endif	/* CONFIG_EDAC_ALTERA_NAND */





/********************** DMA Device Functions **********************/



#ifdef CONFIG_EDAC_ALTERA_DMA



static const struct edac_device_prv_data a10_dmaecc_data = {

	.setup = altr_check_ecc_deps,

	.ce_clear_mask = ALTR_A10_ECC_SERRPENA,

	.ue_clear_mask = ALTR_A10_ECC_DERRPENA,

	.dbgfs_name = "altr_trigger",

	.ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,

	.ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,

	.ce_set_mask = ALTR_A10_ECC_TSERRA,

	.ue_set_mask = ALTR_A10_ECC_TDERRA,

	.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,

	.ecc_irq_handler = altr_edac_a10_ecc_irq,

	.inject_fops = &altr_edac_a10_device_inject_fops,

};



static int __init socfpga_init_dma_ecc(void)

{

	return altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc");

}



early_initcall(socfpga_init_dma_ecc);



#endif	/* CONFIG_EDAC_ALTERA_DMA */



/********************* Arria10 EDAC Device Functions *************************/

/********************* Arria10 EDAC Device Functions *************************/

static const struct of_device_id altr_edac_a10_device_of_match[] = {

static const struct of_device_id altr_edac_a10_device_of_match[] = {

#ifdef CONFIG_EDAC_ALTERA_L2C

#ifdef CONFIG_EDAC_ALTERA_L2C
@@ -1327,6 +1354,9 @@ static const struct of_device_id altr_edac_a10_device_of_match[] = { 
#endif

#endif

#ifdef CONFIG_EDAC_ALTERA_NAND

#ifdef CONFIG_EDAC_ALTERA_NAND

	{ .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data },

	{ .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data },

#endif

#ifdef CONFIG_EDAC_ALTERA_DMA

	{ .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data },

#endif

#endif

	{},

	{},

};

};
@@ -1618,7 +1648,8 @@ static int altr_edac_a10_probe(struct platform_device *pdev) 
		if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc") || 

		if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc") || 

		    of_device_is_compatible(child, "altr,socfpga-a10-ocram-ecc") ||

		    of_device_is_compatible(child, "altr,socfpga-a10-ocram-ecc") ||

		    of_device_is_compatible(child, "altr,socfpga-eth-mac-ecc") ||

		    of_device_is_compatible(child, "altr,socfpga-eth-mac-ecc") ||

		    of_device_is_compatible(child, "altr,socfpga-nand-ecc"))

		    of_device_is_compatible(child, "altr,socfpga-nand-ecc") ||

		    of_device_is_compatible(child, "altr,socfpga-dma-ecc"))





			altr_edac_a10_device_add(edac, child);

			altr_edac_a10_device_add(edac, child);