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Commit e8247f0b authored by Anant Goel's avatar Anant Goel Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Use PM8195 regulators for SA8195P ADP STAR 



The SA8195P ADP STAR platform uses sa8195-pmic regulators
and GPIO definitions. Provide updated regulators for the
devices and subsystems which run on the SA8195P ADP STAR
platform.

Change-Id: I7dc59e2f6922028b2490925239859c39246e7c72
Signed-off-by: default avatarAnant Goel <anantg@codeaurora.org>
parent fa423953

arch/arm64/boot/dts/qcom/sa8195-pmic.dtsi

+8 −32
Original line number Diff line number Diff line
@@ -75,41 +75,17 @@ 
	/delete-property/ vdda33-supply;

};



&mdss_dsi0 {

	vdda-1p2-supply = <&pm8195_1_l9>;

};



&mdss_dsi1 {

	vdda-1p2-supply = <&pm8195_1_l9>;

};



&mdss_dsi_phy0 {

	vdda-0p9-supply = <&pm8195_3_l5>;

};



&mdss_dsi_phy1 {

	vdda-0p9-supply = <&pm8195_3_l5>;

};



&clock_cpucc {

	lmh_dcvs1: qcom,limits-dcvs@18350800 {

&lmh_dcvs1 {

	isens_vref_0p8-supply = <&pm8195_3_l5>;

	isens-vref-0p8-settings = <880000 880000 20000>;

	isens_vref_1p8-supply = <&pm8195_1_l12>;

	isens-vref-1p8-settings = <1800000 1800000 20000>;

};

};





&soc {

	qcom,lpass@17300000 {

		vdd_cx-supply = <&VDD_CX_LEVEL>;

	};

	clock_camcc: qcom,camcc@ad00000 {

&clock_camcc {

	vdd_mx-supply = <&VDD_MX_LEVEL>;

	vdd_mm-supply = <&VDD_MMCX_LEVEL>;

};

};



&gpu_gx_gdsc {

	parent-supply = <&VDD_MMCX_LEVEL>;

arch/arm64/boot/dts/qcom/sa8195p.dtsi

+119 −0
Original line number Diff line number Diff line
@@ -12,6 +12,10 @@ 


#include "sdmshrike-v2.dtsi"

#include "sa8155-audio.dtsi"

#include "sa8195-pmic.dtsi"

#include "sm8150-camera.dtsi"

#include "sm8150-v2-camera.dtsi"

#include "sa8155-camera-sensor.dtsi"



/ {

	model = "Qualcomm Technologies, Inc. SA8195P";
@@ -106,3 +110,118 @@ 
		};

	};

};



&ufsphy_mem {

	compatible = "qcom,ufs-phy-qmp-v4";

	vdda-phy-supply = <&pm8195_3_l5>;

	vdda-pll-supply = <&pm8195_1_l9>;

	vdda-phy-max-microamp = <138000>;

	vdda-pll-max-microamp = <65100>;



	status = "ok";

};



&ufshc_mem {

	vdd-hba-supply = <&ufs_phy_gdsc>;

	vdd-hba-fixed-regulator;

	vcc-supply = <&pm8195_3_l10>;

	vcc-voltage-level = <2894000 2904000>;

	vcc-low-voltage-sup;

	vccq-supply = <&pm8195_1_l11>;

	vccq2-supply = <&pm8195_3_l7>;

	vcc-max-microamp = <750000>;

	vccq-max-microamp = <750000>;

	vccq2-max-microamp = <750000>;



	status= "ok";

};



&usb2_phy0 {

	vdd-supply = <&pm8195_3_l5>;

	vdda18-supply = <&pm8195_1_l12>;

	vdda33-supply = <&pm8195_3_l16>;

};



&usb2_phy1 {

	vdd-supply = <&pm8195_3_l5>;

	vdda18-supply = <&pm8195_1_l12>;

	vdda33-supply = <&pm8195_3_l16>;

	status = "ok";

};



&mdss_dsi_phy0 {

	vdda-0p9-supply = <&pm8195_3_l5>;

};



&mdss_dsi_phy1 {

	vdda-0p9-supply = <&pm8195_3_l5>;

};



&mdss_dsi0 {

	vdda-1p2-supply = <&pm8195_1_l9>;

};



&mdss_dsi1 {

	vdda-1p2-supply = <&pm8195_1_l9>;

};



&sde_dp {

	vdda-1p2-supply = <&pm8195_1_l9>;

	vdda-0p9-supply = <&pm8195_3_l5>;

};



&pil_lpass {

	vdd_cx-supply = <&VDD_CX_LEVEL>;

	status = "ok";

};



&clock_scc {

	vdd_scc_cx-supply = <&pm8195_3_l8_level>;

	status = "ok";

};



&cam_csiphy0 {

	mipi-csi-vdd-supply = <&pm8195_1_l9>;

};



&cam_csiphy1 {

	mipi-csi-vdd-supply = <&pm8195_1_l9>;

};



&cam_csiphy2 {

	mipi-csi-vdd-supply = <&pm8195_1_l9>;

};



&cam_csiphy3 {

	mipi-csi-vdd-supply = <&pm8195_1_l9>;

};



&cam_cci0 {

	qcom,cam-sensor@0 {

		cam_vio-supply = <&pm8195_s4>;

		cam_bob-supply = <&pm8195_s4>;

		cam_vana-supply = <&pm8195_s4>;

		cam_vdig-supply = <&pm8195_s4>;

	};



	qcom,cam-sensor@1 {

		cam_vio-supply = <&pm8195_s4>;

		cam_bob-supply = <&pm8195_s4>;

		cam_vana-supply = <&pm8195_s4>;

		cam_vdig-supply = <&pm8195_s4>;

	};



	qcom,cam-sensor@2 {

		cam_vio-supply = <&pm8195_s4>;

		cam_bob-supply = <&pm8195_s4>;

		cam_vana-supply = <&pm8195_s4>;

		cam_vdig-supply = <&pm8195_s4>;

	};



	qcom,cam-sensor@3 {

		cam_vio-supply = <&pm8195_s4>;

		cam_bob-supply = <&pm8195_s4>;

		cam_vana-supply = <&pm8195_s4>;

		cam_vdig-supply = <&pm8195_s4>;

	};

};