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Commit e72bdf8f authored by Da Hoon Pyun's avatar Da Hoon Pyun
Browse files

ARM: dts: msm: Disable npudsp_npu_ddr_bw for atoll 



This change is to disable npudsp ddr bw for the atoll platform.

Change-Id: I35c37dfaaf3a7c8112d713739f6004c51a8ebda1
Signed-off-by: default avatarDa Hoon Pyun <dpyun@codeaurora.org>
parent 71de7168

arch/arm64/boot/dts/qcom/atoll-npu.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -60,8 +60,8 @@ 
		qcom,proxy-reg-names ="vdd", "vdd_cx";

		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;

		#cooling-cells = <2>;

		qcom,npubw-devs = <&npu_npu_ddr_bw>, <&npudsp_npu_ddr_bw>;

		qcom,npubw-dev-names = "ddr_bw", "dsp_ddr_bw";

		qcom,npubw-devs = <&npu_npu_ddr_bw>;

		qcom,npubw-dev-names = "ddr_bw";

		qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>;

		qcom,npu-pwrlevels {

			#address-cells = <1>;

arch/arm64/boot/dts/qcom/atoll.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -3319,7 +3319,7 @@ 
		governor = "performance";

		qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>;

		operating-points-v2 = <&suspendable_ddr_bw_opp_table>;

		status = "ok";

		status = "disabled";

	};



	npudsp_npu_ddr_bwmon: qcom,npudsp-npu-ddr-bwmon@70300 {
@@ -3337,7 +3337,7 @@ 
		qcom,hw-timer-hz = <19200000>;

		qcom,target-dev = <&npudsp_npu_ddr_bw>;

		qcom,count-unit = <0x10000>;

		status = "ok";

		status = "disabled";

	};



	keepalive_opp_table: keepalive-opp-table {