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Unverified Commit e5633e2d authored by Michael Bestas's avatar Michael Bestas
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Merge tag 'LA.UM.9.1.r1-14700-SMxxx0.QSSI13.0' of... 

Merge tag 'LA.UM.9.1.r1-14700-SMxxx0.QSSI13.0' of https://git.codelinaro.org/clo/la/kernel/msm-4.14 into android13-4.14-msmnile

"LA.UM.9.1.r1-14700-SMxxx0.QSSI13.0"

* tag 'LA.UM.9.1.r1-14700-SMxxx0.QSSI13.0' of https://git.codelinaro.org/clo/la/kernel/msm-4.14:
  msm: npu: Fix use after free issue
  msm: npu: Fix use after free issue
  iommu: Fix missing return check of arm_lpae_init_pte
  msm: kgsl: Prevent wrap around during user address mapping
  soc: qcom: qmi_encdec: out of bound check for input buffer
  iommu: Fix missing return check of arm_lpae_init_pte
  UPSTREAM: security: selinux: allow per-file labeling for bpffs
  UPSTREAM: security: selinux: allow per-file labeling for bpffs
  arm: configs: Enable QCOM_SHOW_RESUME_IRQ module for mdm9607
  Revert "irqchip/gic-v2: implement suspend and resume"
  exec: Force single empty string when argv is empty
  BACKPORT: FROMLIST: mm: protect free_pgtables with mmap_lock write lock in exit_mmap
  bus: mhi: misc: Add check for dev_rp if it is iommu range or not
  mdm: dataipa: increase the size of prefetch buffer

Change-Id: Ifb5dfd1a898ce82251e2cdc310698ed93281c4a2
parents 5fe8afd2 6cce8da0

arch/arm/configs/vendor/mdm9607-perf_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -321,6 +321,7 @@ CONFIG_IIO_BUFFER=y 
CONFIG_IIO_BUFFER_CB=y

CONFIG_QCOM_SPMI_VADC=y

CONFIG_QCOM_SPMI_ADC5=y

CONFIG_QCOM_SHOW_RESUME_IRQ=y

CONFIG_QTI_MPM=y

CONFIG_ANDROID=y

CONFIG_VFAT_FS=y

arch/arm/configs/vendor/mdm9607_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -331,6 +331,7 @@ CONFIG_IIO_BUFFER=y 
CONFIG_IIO_BUFFER_CB=y

CONFIG_QCOM_SPMI_VADC=y

CONFIG_QCOM_SPMI_ADC5=y

CONFIG_QCOM_SHOW_RESUME_IRQ=y

CONFIG_QTI_MPM=y

CONFIG_ANDROID=y

CONFIG_MSM_TZ_LOG=y

drivers/gpu/msm/kgsl_iommu.c

+9 −5
Original line number Diff line number Diff line 
/* Copyright (c) 2011-2021, The Linux Foundation. All rights reserved.

 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.

 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.
@@ -2506,14 +2506,18 @@ static uint64_t kgsl_iommu_find_svm_region(struct kgsl_pagetable *pagetable, 
static bool iommu_addr_in_svm_ranges(struct kgsl_iommu_pt *pt,

	u64 gpuaddr, u64 size)

{

	u64 end = gpuaddr + size;



	/* Make sure size is not zero and we don't wrap around */

	if (end <= gpuaddr)

		return false;



	if ((gpuaddr >= pt->compat_va_start && gpuaddr < pt->compat_va_end) &&

		((gpuaddr + size) > pt->compat_va_start &&

			(gpuaddr + size) <= pt->compat_va_end))

		(end > pt->compat_va_start && end <= pt->compat_va_end))

		return true;



	if ((gpuaddr >= pt->svm_start && gpuaddr < pt->svm_end) &&

		((gpuaddr + size) > pt->svm_start &&

			(gpuaddr + size) <= pt->svm_end))

		(end > pt->svm_start && end <= pt->svm_end))

		return true;



	return false;

drivers/iommu/io-pgtable-arm.c

+3 −1
Original line number Diff line number Diff line
@@ -670,9 +670,11 @@ static int arm_lpae_map_sg(struct io_pgtable_ops *ops, unsigned long iova, 
				arm_lpae_iopte *ptep = ms.pgtable +

					ARM_LPAE_LVL_IDX(iova, MAP_STATE_LVL,

							 data);

				arm_lpae_init_pte(

				ret = arm_lpae_init_pte(

					data, iova, phys, prot, MAP_STATE_LVL,

					ptep, ms.prev_pgtable, false);

				if (ret)

					goto out_err;

				ms.num_pte++;

			} else {

				ret = __arm_lpae_map(data, iova, phys, pgsize,

drivers/irqchip/irq-gic.c

+6 −88
Original line number Diff line number Diff line
@@ -93,11 +93,6 @@ struct gic_chip_data { 
#ifdef CONFIG_GIC_NON_BANKED

	void __iomem *(*get_base)(union gic_base *);

#endif

#ifdef CONFIG_PM

	unsigned int irq_offset;

	unsigned int wakeup_irqs[32];

	unsigned int enabled_irqs[32];

#endif

};



#ifdef CONFIG_BL_SWITCHER
@@ -238,41 +233,8 @@ static void gic_unmask_irq(struct irq_data *d) 


#ifdef CONFIG_PM



static DEFINE_RAW_SPINLOCK(irq_controller_lock);



#ifndef MAX_GIC_NR

#define MAX_GIC_NR	1

#endif



static int gic_suspend_one(struct gic_chip_data *gic)

{

	unsigned int i;

	void __iomem *base = gic_data_dist_base(gic);



	if (base == NULL)

		return 0;



	for (i = 0; i * 32 < gic->gic_irqs; i++) {

		gic->enabled_irqs[i]

			= readl_relaxed(base + GIC_DIST_ENABLE_SET + i * 4);

		/* disable all of them */

		writel_relaxed(0xffffffff,

			base + GIC_DIST_ENABLE_CLEAR + i * 4);

		/* enable the wakeup set */

		writel_relaxed(gic->wakeup_irqs[i],

			base + GIC_DIST_ENABLE_SET + i * 4);

	}

	/* make sure all gic setting finished */

	mb();

	return 0;

}



static int gic_suspend(void)

{

	int i;



	for (i = 0; i < MAX_GIC_NR; i++)

		gic_suspend_one(&gic_data[i]);

	return 0;

}
@@ -286,20 +248,20 @@ static void gic_show_resume_irq(struct gic_chip_data *gic) 
	if (base == NULL)

		return;



	raw_spin_lock(&irq_controller_lock);

	if (!msm_show_resume_irq_mask)

		return;



	for (i = 0; i * 32 < gic->gic_irqs; i++) {

		enabled = readl_relaxed(base + GIC_DIST_ENABLE_CLEAR + i * 4);

		pending[i] = readl_relaxed(base + GIC_DIST_PENDING_SET + i * 4);

		pending[i] &= enabled;

	}

	raw_spin_unlock(&irq_controller_lock);



	for (i = find_first_bit((unsigned long *)pending, gic->gic_irqs);

		i < gic->gic_irqs;

		i = find_next_bit((unsigned long *)pending,

				gic->gic_irqs, i+1)) {

		unsigned int irq = irq_find_mapping(gic->domain,

						i + gic->irq_offset);

		unsigned int irq = irq_find_mapping(gic->domain, i);

		struct irq_desc *desc = irq_to_desc(irq);

		const char *name = "null";
@@ -308,34 +270,20 @@ static void gic_show_resume_irq(struct gic_chip_data *gic) 
		else if (desc->action && desc->action->name)

			name = desc->action->name;



		pr_warn("%s: %d triggered %s\n", __func__,

					i + gic->irq_offset, name);

		pr_warn("%s: %d triggered %s\n", __func__, i, name);

	}

}



static void gic_resume_one(struct gic_chip_data *gic)

{

	unsigned int i;

	void __iomem *base = gic_data_dist_base(gic);



	gic_show_resume_irq(gic);

	for (i = 0; i * 32 < gic->gic_irqs; i++) {

		/* disable all of them */

		writel_relaxed(0xffffffff,

			base + GIC_DIST_ENABLE_CLEAR + i * 4);

		/* enable the enabled set */

		writel_relaxed(gic->enabled_irqs[i],

			base + GIC_DIST_ENABLE_SET + i * 4);

	}

	/* make sure all gic setting finished */

	mb();

}



static void gic_resume(void)

{

	int i;



	for (i = 0; i < MAX_GIC_NR; i++)

	for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++)

		gic_resume_one(&gic_data[i]);

}
@@ -467,30 +415,6 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 
}

#endif



#ifdef CONFIG_PM

static int gic_set_wake(struct irq_data *d, unsigned int on)

{

	int ret = 0;



	unsigned int reg_offset, bit_offset;

	unsigned int gicirq = gic_irq(d);

	struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);



	/* per-cpu interrupts cannot be wakeup interrupts */

	WARN_ON(gicirq < 32);



	reg_offset = gicirq / 32;

	bit_offset = gicirq % 32;



	if (on)

		gic_data->wakeup_irqs[reg_offset] |=  1 << bit_offset;

	else

		gic_data->wakeup_irqs[reg_offset] &=  ~(1 << bit_offset);



	return ret;

}

#endif



static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)

{

	u32 irqstat, irqnr;
@@ -565,15 +489,9 @@ static const struct irq_chip gic_chip = { 
	.irq_set_type		= gic_set_type,

	.irq_get_irqchip_state	= gic_irq_get_irqchip_state,

	.irq_set_irqchip_state	= gic_irq_set_irqchip_state,

#ifdef CONFIG_PM

	.irq_set_wake		= gic_set_wake,

	.flags			= IRQCHIP_SET_TYPE_MASKED |

				  IRQCHIP_MASK_ON_SUSPEND,

#else

	.flags			= IRQCHIP_SET_TYPE_MASKED |

				  IRQCHIP_SKIP_SET_WAKE |

				  IRQCHIP_MASK_ON_SUSPEND,

#endif

};



void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)