Merge "ARM: dts: msm: Add SSC QUPV3 DT nodes for SM8150" (e53ad3a1) · Commits · e / devices / android_kernel_xiaomi_nabu

arch/arm64/boot/dts/qcom/sm8150-qupv3.dtsi

+122 −0

Original line number	Original line	Diff line number	Diff line
	@@ -951,4 +951,126 @@
	dma-names = "tx", "rx";		dma-names = "tx", "rx";
	status = "disabled";		status = "disabled";
	};		};

			/* QUPv3 SSC Instances */
			qupv3_3: qcom,qupv3_3_geni_se@26c0000 {
			compatible = "qcom,qupv3-geni-se";
			reg = <0x26c0000 0x6000>;
			qcom,bus-mas-id = <MSM_BUS_MASTER_SENSORS_AHB>;
			qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;
			qcom,iommu-s1-bypass;

			iommu_qupv3_3_geni_se_cb: qcom,iommu_qupv3_3_geni_se_cb {
			compatible = "qcom,qupv3-geni-se-cb";
			iommus = <&apps_smmu 0x4e3 0x0>;
			};
			};

			/* I2C */
			qupv3_se20_i2c: i2c@2680000 {
			compatible = "qcom,i2c-geni";
			reg = <0x2680000 0x4000>;
			interrupts = <GIC_SPI 442 0>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-names = "se-clk", "m-ahb", "s-ahb";
			clocks = <&clock_scc SCC_QUPV3_SE0_CLK>,
			<&clock_scc SCC_QUPV3_M_HCLK_CLK>,
			<&clock_scc SCC_QUPV3_S_HCLK_CLK>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&qupv3_se20_i2c_active>;
			pinctrl-1 = <&qupv3_se20_i2c_sleep>;
			qcom,wrapper-core = <&qupv3_3>;
			status = "disabled";
			};

			qupv3_se21_i2c: i2c@2684000 {
			compatible = "qcom,i2c-geni";
			reg = <0x2684000 0x4000>;
			interrupts = <GIC_SPI 443 0>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-names = "se-clk", "m-ahb", "s-ahb";
			clocks = <&clock_scc SCC_QUPV3_SE1_CLK>,
			<&clock_scc SCC_QUPV3_M_HCLK_CLK>,
			<&clock_scc SCC_QUPV3_S_HCLK_CLK>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&qupv3_se21_i2c_active>;
			pinctrl-1 = <&qupv3_se21_i2c_sleep>;
			qcom,wrapper-core = <&qupv3_3>;
			status = "disabled";
			};

			qupv3_se22_i2c: i2c@2688000 {
			compatible = "qcom,i2c-geni";
			reg = <0x2688000 0x4000>;
			interrupts = <GIC_SPI 444 0>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-names = "se-clk", "m-ahb", "s-ahb";
			clocks = <&clock_scc SCC_QUPV3_SE2_CLK>,
			<&clock_scc SCC_QUPV3_M_HCLK_CLK>,
			<&clock_scc SCC_QUPV3_S_HCLK_CLK>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&qupv3_se22_i2c_active>;
			pinctrl-1 = <&qupv3_se22_i2c_sleep>;
			qcom,wrapper-core = <&qupv3_3>;
			status = "disabled";
			};

			qupv3_se23_i2c: i2c@268c000 {
			compatible = "qcom,i2c-geni";
			reg = <0x268c000 0x4000>;
			interrupts = <GIC_SPI 445 0>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-names = "se-clk", "m-ahb", "s-ahb";
			clocks = <&clock_scc SCC_QUPV3_SE3_CLK>,
			<&clock_scc SCC_QUPV3_M_HCLK_CLK>,
			<&clock_scc SCC_QUPV3_S_HCLK_CLK>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&qupv3_se23_i2c_active>;
			pinctrl-1 = <&qupv3_se23_i2c_sleep>;
			qcom,wrapper-core = <&qupv3_3>;
			status = "disabled";
			};

			/* SPI */
			qupv3_se21_spi: spi@2684000 {
			compatible = "qcom,spi-geni";
			reg = <0x2684000 0x4000>;
			reg-names = "se_phys";
			interrupts = <GIC_SPI 443 0>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-names = "se-clk", "m-ahb", "s-ahb";
			clocks = <&clock_scc SCC_QUPV3_SE1_CLK>,
			<&clock_scc SCC_QUPV3_M_HCLK_CLK>,
			<&clock_scc SCC_QUPV3_S_HCLK_CLK>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&qupv3_se21_spi_active>;
			pinctrl-1 = <&qupv3_se21_spi_sleep>;
			spi-max-frequency = <50000000>;
			qcom,wrapper-core = <&qupv3_3>;
			status = "disabled";
			};

			qupv3_se22_spi: spi@2688000 {
			compatible = "qcom,spi-geni";
			reg = <0x2688000 0x4000>;
			reg-names = "se_phys";
			interrupts = <GIC_SPI 444 0>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-names = "se-clk", "m-ahb", "s-ahb";
			clocks = <&clock_scc SCC_QUPV3_SE2_CLK>,
			<&clock_scc SCC_QUPV3_M_HCLK_CLK>,
			<&clock_scc SCC_QUPV3_S_HCLK_CLK>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&qupv3_se22_spi_active>;
			pinctrl-1 = <&qupv3_se22_spi_sleep>;
			spi-max-frequency = <50000000>;
			qcom,wrapper-core = <&qupv3_3>;
			status = "disabled";
			};
	};		};

arch/arm64/boot/dts/qcom/sm8150-slpi-pinctrl.dtsi

+178 −0

Original line number	Original line	Diff line number	Diff line
	@@ -16,5 +16,183 @@
	reg = <0x2B40000 0x20000>;		reg = <0x2B40000 0x20000>;
	qcom,num-pins = <14>;		qcom,num-pins = <14>;
	status = "disabled";		status = "disabled";

			qupv3_se20_i2c_pins: qupv3_se20_i2c_pins {
			qupv3_se20_i2c_active: qupv3_se20_i2c_active {
			mux {
			pins = "gpio0", "gpio1";
			function = "func1";
			};

			config {
			pins = "gpio0", "gpio1";
			drive-strength = <2>;
			bias-disable;
			};
			};

			qupv3_se20_i2c_sleep: qupv3_se20_i2c_sleep {
			mux {
			pins = "gpio0", "gpio1";
			function = "gpio";
			};

			config {
			pins = "gpio0", "gpio1";
			drive-strength = <2>;
			bias-pull-up;
			};
			};
			};

			qupv3_se21_i2c_pins: qupv3_se21_i2c_pins {
			qupv3_se21_i2c_active: qupv3_se21_i2c_active {
			mux {
			pins = "gpi2", "gpio3";
			function = "func1";
			};

			config {
			pins = "gpio2", "gpio3";
			drive-strength = <2>;
			bias-disable;
			};
			};

			qupv3_se21_i2c_sleep: qupv3_se21_i2c_sleep {
			mux {
			pins = "gpio2", "gpio3";
			function = "gpio";
			};

			config {
			pins = "gpio2", "gpio3";
			drive-strength = <2>;
			bias-pull-up;
			};
			};
			};

			qupv3_se22_i2c_pins: qupv3_se22_i2c_pins {
			qupv3_se22_i2c_active: qupv3_se22_i2c_active {
			mux {
			pins = "gpio6", "gpio7";
			function = "func1";
			};

			config {
			pins = "gpio6", "gpio7";
			drive-strength = <2>;
			bias-disable;
			};
			};

			qupv3_se22_i2c_sleep: qupv3_se22_i2c_sleep {
			mux {
			pins = "gpio6", "gpio7";
			function = "gpio";
			};

			config {
			pins = "gpio6", "gpio7";
			drive-strength = <2>;
			bias-pull-up;
			};
			};
			};

			qupv3_se23_i2c_pins: qupv3_se23_i2c_pins {
			qupv3_se23_i2c_active: qupv3_se23_i2c_active {
			mux {
			pins = "gpio8", "gpio9";
			function = "func3";
			};

			config {
			pins = "gpio8", "gpio9";
			drive-strength = <2>;
			bias-disable;
			};
			};

			qupv3_se23_i2c_sleep: qupv3_se23_i2c_sleep {
			mux {
			pins = "gpio8", "gpio9";
			function = "gpio";
			};

			config {
			pins = "gpio8", "gpio9";
			drive-strength = <2>;
			bias-pull-up;
			};
			};
			};

			/* SE21 pin mappings */
			qupv3_se21_spi_pins: qupv3_se21_spi_pins {
			qupv3_se21_spi_active: qupv3_se21_spi_active {
			mux {
			pins = "gpio2", "gpio3", "gpio4",
			"gpio5";
			function = "func1";
			};

			config {
			pins = "gpio2", "gpio3", "gpio4",
			"gpio5";
			drive-strength = <6>;
			bias-disable;
			};
			};

			qupv3_se21_spi_sleep: qupv3_se21_spi_sleep {
			mux {
			pins = "gpio2", "gpio3", "gpio4",
			"gpio5";
			function = "gpio";
			};

			config {
			pins = "gpio2", "gpio3", "gpio4",
			"gpio5";
			drive-strength = <6>;
			bias-disable;
			};
			};
			};

			/SE22 pin mappings/
			qupv3_se22_spi_pins: qupv3_se22_spi_pins {
			qupv3_se22_spi_active: qupv3_se22_spi_active {
			mux {
			pins = "gpio6", "gpio7", "gpio8",
			"gpio9";
			function = "func1";
			};

			config {
			pins = "gpio6", "gpio7", "gpio8",
			"gpio9";
			drive-strength = <6>;
			bias-disable;
			};
			};

			qupv3_se22_spi_sleep: qupv3_se22_spi_sleep {
			mux {
			pins = "gpio6", "gpio7", "gpio8",
			"gpio9";
			function = "gpio";
			};

			config {
			pins = "gpio6", "gpio7", "gpio8",
			"gpio9";
			drive-strength = <6>;
			bias-disable;
			};
			};
			};
	};		};
	};		};