Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e50d95e2 authored by Mika Westerberg's avatar Mika Westerberg Committed by Linus Walleij
Browse files

pinctrl: cannonlake: Fix HOSTSW_OWN register offset of H variant 

It turns out the HOSTSW_OWN register offset is different between LP and
H variants. The latter should use 0xc0 instead so fix that.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=199911


Fixes: a663ccf0 ("pinctrl: intel: Add Intel Cannon Lake PCH-H pin controller support")
Signed-off-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent b85bfa24

drivers/pinctrl/intel/pinctrl-cannonlake.c

+20 −13
Original line number Original line Diff line number Diff line
@@ -17,7 +17,8 @@ 




#define CNL_PAD_OWN		0x020

#define CNL_PAD_OWN		0x020

#define CNL_PADCFGLOCK		0x080

#define CNL_PADCFGLOCK		0x080

#define CNL_HOSTSW_OWN	0x0b0

#define CNL_LP_HOSTSW_OWN	0x0b0

#define CNL_H_HOSTSW_OWN	0x0c0

#define CNL_GPI_IE		0x120

#define CNL_GPI_IE		0x120





#define CNL_GPP(r, s, e, g)				\

#define CNL_GPP(r, s, e, g)				\
@@ -30,12 +31,12 @@ 




#define CNL_NO_GPIO	-1

#define CNL_NO_GPIO	-1





#define CNL_COMMUNITY(b, s, e, g)			\

#define CNL_COMMUNITY(b, s, e, o, g)			\

	{						\

	{						\

		.barno = (b),				\

		.barno = (b),				\

		.padown_offset = CNL_PAD_OWN,		\

		.padown_offset = CNL_PAD_OWN,		\

		.padcfglock_offset = CNL_PADCFGLOCK,	\

		.padcfglock_offset = CNL_PADCFGLOCK,	\

		.hostown_offset = CNL_HOSTSW_OWN,	\

		.hostown_offset = (o),			\

		.ie_offset = CNL_GPI_IE,		\

		.ie_offset = CNL_GPI_IE,		\

		.pin_base = (s),			\

		.pin_base = (s),			\

		.npins = ((e) - (s) + 1),		\

		.npins = ((e) - (s) + 1),		\
@@ -43,6 +44,12 @@ 
		.ngpps = ARRAY_SIZE(g),			\

		.ngpps = ARRAY_SIZE(g),			\

	}

	}





#define CNLLP_COMMUNITY(b, s, e, g)			\

	CNL_COMMUNITY(b, s, e, CNL_LP_HOSTSW_OWN, g)



#define CNLH_COMMUNITY(b, s, e, g)			\

	CNL_COMMUNITY(b, s, e, CNL_H_HOSTSW_OWN, g)



/* Cannon Lake-H */

/* Cannon Lake-H */

static const struct pinctrl_pin_desc cnlh_pins[] = {

static const struct pinctrl_pin_desc cnlh_pins[] = {

	/* GPP_A */

	/* GPP_A */
@@ -442,10 +449,10 @@ static const struct intel_function cnlh_functions[] = { 
};

};





static const struct intel_community cnlh_communities[] = {

static const struct intel_community cnlh_communities[] = {

	CNL_COMMUNITY(0, 0, 50, cnlh_community0_gpps),

	CNLH_COMMUNITY(0, 0, 50, cnlh_community0_gpps),

	CNL_COMMUNITY(1, 51, 154, cnlh_community1_gpps),

	CNLH_COMMUNITY(1, 51, 154, cnlh_community1_gpps),

	CNL_COMMUNITY(2, 155, 248, cnlh_community3_gpps),

	CNLH_COMMUNITY(2, 155, 248, cnlh_community3_gpps),

	CNL_COMMUNITY(3, 249, 298, cnlh_community4_gpps),

	CNLH_COMMUNITY(3, 249, 298, cnlh_community4_gpps),

};

};





static const struct intel_pinctrl_soc_data cnlh_soc_data = {

static const struct intel_pinctrl_soc_data cnlh_soc_data = {
@@ -803,9 +810,9 @@ static const struct intel_padgroup cnllp_community4_gpps[] = { 
};

};





static const struct intel_community cnllp_communities[] = {

static const struct intel_community cnllp_communities[] = {

	CNL_COMMUNITY(0, 0, 67, cnllp_community0_gpps),

	CNLLP_COMMUNITY(0, 0, 67, cnllp_community0_gpps),

	CNL_COMMUNITY(1, 68, 180, cnllp_community1_gpps),

	CNLLP_COMMUNITY(1, 68, 180, cnllp_community1_gpps),

	CNL_COMMUNITY(2, 181, 243, cnllp_community4_gpps),

	CNLLP_COMMUNITY(2, 181, 243, cnllp_community4_gpps),

};

};





static const struct intel_pinctrl_soc_data cnllp_soc_data = {

static const struct intel_pinctrl_soc_data cnllp_soc_data = {