File changed.
Preview size limit exceeded, changes collapsed.
Loading
Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more
The send DMA hardware queue voided a number of prior assumptions about when a send is complete which led to completions being generated out of order. There were also a number of locking issues when switching the QP to the error or reset states, and we implement the IB_QPS_SQD state. Signed-off-by:Ralph Campbell <ralph.campbell@qlogic.com> Signed-off-by:
Roland Dreier <rolandd@cisco.com>
File changed.
Preview size limit exceeded, changes collapsed.