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Commit e4f979e0 authored by Lina Iyer's avatar Lina Iyer
Browse files

ARM: dts: msm: add RSC device bindings for sdmshrike 



Add RSC controller bindings for Apps and Display RSCs for sdmshrike SoC.

Change-Id: Ic0185c4626b8b7eacfc578c6682aa0880d783e5a
Signed-off-by: default avatarLina Iyer <ilina@codeaurora.org>
parent 5dfea24b

arch/arm64/boot/dts/qcom/sdmshrike.dtsi

+33 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 


#include "skeleton64.dtsi"

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/soc/qcom,tcs-mbox.h>



/ {

	model = "Qualcomm Technologies, Inc. SDMSHRIKE";
@@ -310,6 +311,38 @@ 
			compatible = "qcom,llcc-amon";

		};

	};



	cmd_db: qcom,cmd-db@c3f000c {

		compatible = "qcom,cmd-db";

		reg = <0xc3f000c 8>;

	};



	apps_rsc: mailbox@18220000 {

		compatible = "qcom,tcs-drv";

		label = "apps_rsc";

		reg = <0x18220000 0x100>, <0x18220d00 0x3000>;

		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;

		#mbox-cells = <1>;

		qcom,drv-id = <2>;

		qcom,tcs-config = <ACTIVE_TCS  2>,

				  <SLEEP_TCS   3>,

				  <WAKE_TCS    3>,

				  <CONTROL_TCS 1>;

	};



	disp_rsc: mailbox@af20000 {

		status = "disabled";

		compatible = "qcom,tcs-drv";

		label = "display_rsc";

		reg = <0xaf20000 0x100>, <0xaf21c00 0x3000>;

		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;

		#mbox-cells = <1>;

		qcom,drv-id = <0>;

		qcom,tcs-config = <ACTIVE_TCS  2>,

				  <SLEEP_TCS   1>,

				  <WAKE_TCS    1>,

				  <CONTROL_TCS 0>;

	};

};



#include "sdmshrike-pinctrl.dtsi"