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Commit e4b23e1f authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "bindings: clock: Add debugcc support for SDM429W"

parents d78e395f 959b4de6
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@@ -11,6 +11,7 @@ Required properties :
		"qcom,atoll-debugcc",
		"qcom,debugcc-sdmshrike".
		"qcom,gcc-debug-sdm660".
		"qcom,sdm429w-debugcc".
- qcom,gcc: phandle to the GCC device node.
- qcom,videocc: phandle to the Video CC device node.
- qcom,camcc: phandle to the Camera CC device node.
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@@ -672,3 +672,11 @@ config SM_DEBUGCC_ATOLL
	  Support for the debug clock controller on Qualcomm Technologies, Inc
	  ATOLL devices.
	  Say Y if you want to support the clock measurement functionality.

config SDM_GCC_429W
        tristate "SDM429W Global Clock Controller"
	depends on COMMON_CLK_QCOM
	help
	  Support for the global clock controller on SDM429W devices.
	  Say Y if you want to use peripheral devices such as UART, SPI,
	  I2C, USB, UFS, SDCC, Display, Camera, Video etc.
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@@ -90,5 +90,6 @@ obj-$(CONFIG_SM_VIDEOCC_ATOLL) += videocc-atoll.o
obj-$(CONFIG_SM_VIDEOCC_TRINKET) += videocc-trinket.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
obj-$(CONFIG_VIRTIO_CLK) += virtio_clk.o virtio_clk_sm8150.o virtio_clk_sm6150.o virtio_clk_sa8195p.o
obj-$(CONFIG_SDM_GCC_429W) += gcc-sdm429w.o

obj-y += mdss/
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/*
 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_SDM429W_H
#define __DRIVERS_CLK_QCOM_VDD_LEVEL_SDM429W_H

#include <linux/regulator/rpm-smd-regulator.h>
#include <linux/regulator/consumer.h>

enum vdd_dig_levels {
	VDD_NONE,
	VDD_MIN,		/* MIN SVS */
	VDD_LOWER,		/* SVS2 */
	VDD_LOW,		/* SVS */
	VDD_LOW_L1,		/* SVSL1 */
	VDD_NOMINAL,	/* NOM */
	VDD_NOMINAL_L1,	/* NOM */
	VDD_HIGH,		/* TURBO */
	VDD_NUM,
};

static int vdd_corner[] = {
	RPM_REGULATOR_LEVEL_NONE,		/* VDD_NONE */
	RPM_REGULATOR_LEVEL_MIN_SVS,		/* VDD_MIN */
	RPM_REGULATOR_LEVEL_LOW_SVS,		/* VDD_LOWER */
	RPM_REGULATOR_LEVEL_SVS,		/* VDD_LOW */
	RPM_REGULATOR_LEVEL_SVS_PLUS,		/* VDD_LOW_L1 */
	RPM_REGULATOR_LEVEL_NOM,		/* VDD_NOMINAL */
	RPM_REGULATOR_LEVEL_NOM_PLUS,		/* VDD_NOMINAL */
	RPM_REGULATOR_LEVEL_TURBO,		/* VDD_HIGH */
};

enum vdd_hf_pll_levels {
	VDD_HF_PLL_OFF,
	VDD_HF_PLL_SVS,
	VDD_HF_PLL_NOM,
	VDD_HF_PLL_TUR,
	VDD_HF_PLL_NUM,
};

static int vdd_hf_levels[] = {
	0,       RPM_REGULATOR_LEVEL_NONE,	/* VDD_HF_PLL_OFF */
	1800000, RPM_REGULATOR_LEVEL_SVS,	/* VDD_HF_PLL_SVS */
	1800000, RPM_REGULATOR_LEVEL_NOM,	/* VDD_HF_PLL_NOM */
	1800000, RPM_REGULATOR_LEVEL_TURBO,	/* VDD_HF_PLL_TUR */
};

enum vdd_sr_pll_levels {
	VDD_SR_PLL_OFF,
	VDD_SR_PLL_SVS,
	VDD_SR_PLL_NOM,
	VDD_SR_PLL_TUR,
	VDD_SR_PLL_NUM,
};

static int vdd_sr_levels[] = {
	0,	/* VDD_SR_PLL_OFF */
	976000,	/* VDD_SR_PLL_SVS */
	976000,	/* VDD_SR_PLL_NOM */
	976000,	/* VDD_SR_PLL_TUR */
};

#endif
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