Loading arch/arm64/boot/dts/qcom/atoll-atp.dtsi +22 −0 Original line number Diff line number Diff line Loading @@ -206,3 +206,25 @@ }; }; &qupv3_se0_i2c { status = "ok"; qcom,clk-freq-out = <1000000>; #address-cells = <1>; #size-cells = <0>; nq@28 { compatible = "qcom,nq-nci"; reg = <0x28>; qcom,nq-irq = <&tlmm 37 0x00>; qcom,nq-ven = <&tlmm 12 0x00>; qcom,nq-firm = <&tlmm 36 0x00>; qcom,nq-clkreq = <&tlmm 31 0x00>; interrupt-parent = <&tlmm>; interrupts = <37 0>; interrupt-names = "nfc_irq"; pinctrl-names = "nfc_active", "nfc_suspend"; pinctrl-0 = <&nfc_int_active &nfc_enable_active &nfc_clk_req_active>; pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend &nfc_clk_req_suspend>; }; }; Loading
arch/arm64/boot/dts/qcom/atoll-atp.dtsi +22 −0 Original line number Diff line number Diff line Loading @@ -206,3 +206,25 @@ }; }; &qupv3_se0_i2c { status = "ok"; qcom,clk-freq-out = <1000000>; #address-cells = <1>; #size-cells = <0>; nq@28 { compatible = "qcom,nq-nci"; reg = <0x28>; qcom,nq-irq = <&tlmm 37 0x00>; qcom,nq-ven = <&tlmm 12 0x00>; qcom,nq-firm = <&tlmm 36 0x00>; qcom,nq-clkreq = <&tlmm 31 0x00>; interrupt-parent = <&tlmm>; interrupts = <37 0>; interrupt-names = "nfc_irq"; pinctrl-names = "nfc_active", "nfc_suspend"; pinctrl-0 = <&nfc_int_active &nfc_enable_active &nfc_clk_req_active>; pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend &nfc_clk_req_suspend>; }; };