clk: mediatek: Add MT2712 clock support (e2f744a8) · Commits · e / devices / android_kernel_xiaomi_nabu

drivers/clk/mediatek/Kconfig

+50 −0

Original line number	Diff line number	Diff line
		@@ -50,6 +50,56 @@ config COMMON_CLK_MT2701_BDPSYS
		---help---
		This driver supports Mediatek MT2701 bdpsys clocks.

		config COMMON_CLK_MT2712
		bool "Clock driver for Mediatek MT2712"
		depends on (ARCH_MEDIATEK && ARM64) \|\| COMPILE_TEST
		select COMMON_CLK_MEDIATEK
		default ARCH_MEDIATEK && ARM64
		---help---
		This driver supports Mediatek MT2712 basic clocks.

		config COMMON_CLK_MT2712_BDPSYS
		bool "Clock driver for Mediatek MT2712 bdpsys"
		depends on COMMON_CLK_MT2712
		---help---
		This driver supports Mediatek MT2712 bdpsys clocks.

		config COMMON_CLK_MT2712_IMGSYS
		bool "Clock driver for Mediatek MT2712 imgsys"
		depends on COMMON_CLK_MT2712
		---help---
		This driver supports Mediatek MT2712 imgsys clocks.

		config COMMON_CLK_MT2712_JPGDECSYS
		bool "Clock driver for Mediatek MT2712 jpgdecsys"
		depends on COMMON_CLK_MT2712
		---help---
		This driver supports Mediatek MT2712 jpgdecsys clocks.

		config COMMON_CLK_MT2712_MFGCFG
		bool "Clock driver for Mediatek MT2712 mfgcfg"
		depends on COMMON_CLK_MT2712
		---help---
		This driver supports Mediatek MT2712 mfgcfg clocks.

		config COMMON_CLK_MT2712_MMSYS
		bool "Clock driver for Mediatek MT2712 mmsys"
		depends on COMMON_CLK_MT2712
		---help---
		This driver supports Mediatek MT2712 mmsys clocks.

		config COMMON_CLK_MT2712_VDECSYS
		bool "Clock driver for Mediatek MT2712 vdecsys"
		depends on COMMON_CLK_MT2712
		---help---
		This driver supports Mediatek MT2712 vdecsys clocks.

		config COMMON_CLK_MT2712_VENCSYS
		bool "Clock driver for Mediatek MT2712 vencsys"
		depends on COMMON_CLK_MT2712
		---help---
		This driver supports Mediatek MT2712 vencsys clocks.

		config COMMON_CLK_MT6797
		bool "Clock driver for Mediatek MT6797"
		depends on (ARCH_MEDIATEK && ARM64) \|\| COMPILE_TEST

drivers/clk/mediatek/Makefile

+8 −0

Original line number	Diff line number	Diff line
		@@ -12,5 +12,13 @@ obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) += clk-mt2701-hif.o
		obj-$(CONFIG_COMMON_CLK_MT2701_IMGSYS) += clk-mt2701-img.o
		obj-$(CONFIG_COMMON_CLK_MT2701_MMSYS) += clk-mt2701-mm.o
		obj-$(CONFIG_COMMON_CLK_MT2701_VDECSYS) += clk-mt2701-vdec.o
		obj-$(CONFIG_COMMON_CLK_MT2712) += clk-mt2712.o
		obj-$(CONFIG_COMMON_CLK_MT2712_BDPSYS) += clk-mt2712-bdp.o
		obj-$(CONFIG_COMMON_CLK_MT2712_IMGSYS) += clk-mt2712-img.o
		obj-$(CONFIG_COMMON_CLK_MT2712_JPGDECSYS) += clk-mt2712-jpgdec.o
		obj-$(CONFIG_COMMON_CLK_MT2712_MFGCFG) += clk-mt2712-mfg.o
		obj-$(CONFIG_COMMON_CLK_MT2712_MMSYS) += clk-mt2712-mm.o
		obj-$(CONFIG_COMMON_CLK_MT2712_VDECSYS) += clk-mt2712-vdec.o
		obj-$(CONFIG_COMMON_CLK_MT2712_VENCSYS) += clk-mt2712-venc.o
		obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
		obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o

drivers/clk/mediatek/clk-mt2712-bdp.c

0 → 100644

+102 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2017 MediaTek Inc.
		* Author: Weiyi Lu <weiyi.lu@mediatek.com>
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		* published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		#include <linux/clk-provider.h>
		#include <linux/platform_device.h>

		#include "clk-mtk.h"
		#include "clk-gate.h"

		#include <dt-bindings/clock/mt2712-clk.h>

		static const struct mtk_gate_regs bdp_cg_regs = {
		.set_ofs = 0x100,
		.clr_ofs = 0x100,
		.sta_ofs = 0x100,
		};

		#define GATE_BDP(_id, _name, _parent, _shift) { \
		.id = _id, \
		.name = _name, \
		.parent_name = _parent, \
		.regs = &bdp_cg_regs, \
		.shift = _shift, \
		.ops = &mtk_clk_gate_ops_no_setclr, \
		}

		static const struct mtk_gate bdp_clks[] = {
		GATE_BDP(CLK_BDP_BRIDGE_B, "bdp_bridge_b", "mm_sel", 0),
		GATE_BDP(CLK_BDP_BRIDGE_DRAM, "bdp_bridge_d", "mm_sel", 1),
		GATE_BDP(CLK_BDP_LARB_DRAM, "bdp_larb_d", "mm_sel", 2),
		GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_PXL, "bdp_vdi_pxl", "tvd_sel", 3),
		GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_DRAM, "bdp_vdi_d", "mm_sel", 4),
		GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_B, "bdp_vdi_b", "mm_sel", 5),
		GATE_BDP(CLK_BDP_MT_B, "bdp_fmt_b", "mm_sel", 9),
		GATE_BDP(CLK_BDP_DISPFMT_27M, "bdp_27m", "di_sel", 10),
		GATE_BDP(CLK_BDP_DISPFMT_27M_VDOUT, "bdp_27m_vdout", "di_sel", 11),
		GATE_BDP(CLK_BDP_DISPFMT_27_74_74, "bdp_27_74_74", "di_sel", 12),
		GATE_BDP(CLK_BDP_DISPFMT_2FS, "bdp_2fs", "di_sel", 13),
		GATE_BDP(CLK_BDP_DISPFMT_2FS_2FS74_148, "bdp_2fs74_148", "di_sel", 14),
		GATE_BDP(CLK_BDP_DISPFMT_B, "bdp_b", "mm_sel", 15),
		GATE_BDP(CLK_BDP_VDO_DRAM, "bdp_vdo_d", "mm_sel", 16),
		GATE_BDP(CLK_BDP_VDO_2FS, "bdp_vdo_2fs", "di_sel", 17),
		GATE_BDP(CLK_BDP_VDO_B, "bdp_vdo_b", "mm_sel", 18),
		GATE_BDP(CLK_BDP_WR_CHANNEL_DI_PXL, "bdp_di_pxl", "di_sel", 19),
		GATE_BDP(CLK_BDP_WR_CHANNEL_DI_DRAM, "bdp_di_d", "mm_sel", 20),
		GATE_BDP(CLK_BDP_WR_CHANNEL_DI_B, "bdp_di_b", "mm_sel", 21),
		GATE_BDP(CLK_BDP_NR_AGENT, "bdp_nr_agent", "nr_sel", 22),
		GATE_BDP(CLK_BDP_NR_DRAM, "bdp_nr_d", "mm_sel", 23),
		GATE_BDP(CLK_BDP_NR_B, "bdp_nr_b", "mm_sel", 24),
		GATE_BDP(CLK_BDP_BRIDGE_RT_B, "bdp_bridge_rt_b", "mm_sel", 25),
		GATE_BDP(CLK_BDP_BRIDGE_RT_DRAM, "bdp_bridge_rt_d", "mm_sel", 26),
		GATE_BDP(CLK_BDP_LARB_RT_DRAM, "bdp_larb_rt_d", "mm_sel", 27),
		GATE_BDP(CLK_BDP_TVD_TDC, "bdp_tvd_tdc", "mm_sel", 28),
		GATE_BDP(CLK_BDP_TVD_54, "bdp_tvd_clk_54", "tvd_sel", 29),
		GATE_BDP(CLK_BDP_TVD_CBUS, "bdp_tvd_cbus", "mm_sel", 30),
		};

		static int clk_mt2712_bdp_probe(struct platform_device *pdev)
		{
		struct clk_onecell_data *clk_data;
		int r;
		struct device_node *node = pdev->dev.of_node;

		clk_data = mtk_alloc_clk_data(CLK_BDP_NR_CLK);

		mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
		clk_data);

		r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);

		if (r != 0)
		pr_err("%s(): could not register clock provider: %d\n",
		__func__, r);

		return r;
		}

		static const struct of_device_id of_match_clk_mt2712_bdp[] = {
		{ .compatible = "mediatek,mt2712-bdpsys", },
		{}
		};

		static struct platform_driver clk_mt2712_bdp_drv = {
		.probe = clk_mt2712_bdp_probe,
		.driver = {
		.name = "clk-mt2712-bdp",
		.of_match_table = of_match_clk_mt2712_bdp,
		},
		};

		builtin_platform_driver(clk_mt2712_bdp_drv);

drivers/clk/mediatek/clk-mt2712-img.c

0 → 100644

+80 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2017 MediaTek Inc.
		* Author: Weiyi Lu <weiyi.lu@mediatek.com>
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		* published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		#include <linux/clk-provider.h>
		#include <linux/platform_device.h>

		#include "clk-mtk.h"
		#include "clk-gate.h"

		#include <dt-bindings/clock/mt2712-clk.h>

		static const struct mtk_gate_regs img_cg_regs = {
		.set_ofs = 0x0,
		.clr_ofs = 0x0,
		.sta_ofs = 0x0,
		};

		#define GATE_IMG(_id, _name, _parent, _shift) { \
		.id = _id, \
		.name = _name, \
		.parent_name = _parent, \
		.regs = &img_cg_regs, \
		.shift = _shift, \
		.ops = &mtk_clk_gate_ops_no_setclr, \
		}

		static const struct mtk_gate img_clks[] = {
		GATE_IMG(CLK_IMG_SMI_LARB2, "img_smi_larb2", "mm_sel", 0),
		GATE_IMG(CLK_IMG_SENINF_SCAM_EN, "img_scam_en", "csi0", 3),
		GATE_IMG(CLK_IMG_SENINF_CAM_EN, "img_cam_en", "mm_sel", 8),
		GATE_IMG(CLK_IMG_CAM_SV_EN, "img_cam_sv_en", "mm_sel", 9),
		GATE_IMG(CLK_IMG_CAM_SV1_EN, "img_cam_sv1_en", "mm_sel", 10),
		GATE_IMG(CLK_IMG_CAM_SV2_EN, "img_cam_sv2_en", "mm_sel", 11),
		};

		static int clk_mt2712_img_probe(struct platform_device *pdev)
		{
		struct clk_onecell_data *clk_data;
		int r;
		struct device_node *node = pdev->dev.of_node;

		clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);

		mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
		clk_data);

		r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);

		if (r != 0)
		pr_err("%s(): could not register clock provider: %d\n",
		__func__, r);

		return r;
		}

		static const struct of_device_id of_match_clk_mt2712_img[] = {
		{ .compatible = "mediatek,mt2712-imgsys", },
		{}
		};

		static struct platform_driver clk_mt2712_img_drv = {
		.probe = clk_mt2712_img_probe,
		.driver = {
		.name = "clk-mt2712-img",
		.of_match_table = of_match_clk_mt2712_img,
		},
		};

		builtin_platform_driver(clk_mt2712_img_drv);

drivers/clk/mediatek/clk-mt2712-jpgdec.c

0 → 100644

+76 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2017 MediaTek Inc.
		* Author: Weiyi Lu <weiyi.lu@mediatek.com>
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		* published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		#include <linux/clk-provider.h>
		#include <linux/platform_device.h>

		#include "clk-mtk.h"
		#include "clk-gate.h"

		#include <dt-bindings/clock/mt2712-clk.h>

		static const struct mtk_gate_regs jpgdec_cg_regs = {
		.set_ofs = 0x4,
		.clr_ofs = 0x8,
		.sta_ofs = 0x0,
		};

		#define GATE_JPGDEC(_id, _name, _parent, _shift) { \
		.id = _id, \
		.name = _name, \
		.parent_name = _parent, \
		.regs = &jpgdec_cg_regs, \
		.shift = _shift, \
		.ops = &mtk_clk_gate_ops_setclr_inv, \
		}

		static const struct mtk_gate jpgdec_clks[] = {
		GATE_JPGDEC(CLK_JPGDEC_JPGDEC1, "jpgdec_jpgdec1", "jpgdec_sel", 0),
		GATE_JPGDEC(CLK_JPGDEC_JPGDEC, "jpgdec_jpgdec", "jpgdec_sel", 4),
		};

		static int clk_mt2712_jpgdec_probe(struct platform_device *pdev)
		{
		struct clk_onecell_data *clk_data;
		int r;
		struct device_node *node = pdev->dev.of_node;

		clk_data = mtk_alloc_clk_data(CLK_JPGDEC_NR_CLK);

		mtk_clk_register_gates(node, jpgdec_clks, ARRAY_SIZE(jpgdec_clks),
		clk_data);

		r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);

		if (r != 0)
		pr_err("%s(): could not register clock provider: %d\n",
		__func__, r);

		return r;
		}

		static const struct of_device_id of_match_clk_mt2712_jpgdec[] = {
		{ .compatible = "mediatek,mt2712-jpgdecsys", },
		{}
		};

		static struct platform_driver clk_mt2712_jpgdec_drv = {
		.probe = clk_mt2712_jpgdec_probe,
		.driver = {
		.name = "clk-mt2712-jpgdec",
		.of_match_table = of_match_clk_mt2712_jpgdec,
		},
		};

		builtin_platform_driver(clk_mt2712_jpgdec_drv);