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Commit e2eb8e38 authored by Benjamin Li's avatar Benjamin Li Committed by David S. Miller
Browse files

bnx2: Flush the register writes which setup the MSI-X table 



The MSI-X table size needs to be properly set before pci_enable_msix()
is called.  But on certain machines, the writes are delayed and the
MSI-X table size is incorrectly read.  By reading the
BNX2_PCI_MSIX_CONTROL register, the writes are flushed and now
ensure that the MSI-X table is set correctly before MSI-X
is enable on the device.

This patch was originally diagnosed and authored by
Kalyan Ram Chintalapati <kalyanc@vmware.com>.

Signed-off-by: default avatarBenjamin Li <benli@broadcom.com>
Signed-off-by: default avatarKalyan Ram Chintalapati <kalyanc@vmware.com>
Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 368c0ca2

drivers/net/bnx2.c

+4 −0
Original line number Diff line number Diff line
@@ -6145,6 +6145,10 @@ bnx2_enable_msix(struct bnx2 *bp, int msix_vecs) 
	REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);

	REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);



	/*  Need to flush the previous three writes to ensure MSI-X

	 *  is setup properly */

	REG_RD(bp, BNX2_PCI_MSIX_CONTROL);



	for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {

		msix_ent[i].entry = i;

		msix_ent[i].vector = 0;