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Commit e21e6fdd authored by Heiner Kallweit's avatar Heiner Kallweit Committed by Ulf Hansson
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mmc: meson-gx: add support for HS400 mode 



Add support for HS400 mode.

The driver still misses support for tuning, therefore
highspeed modes like HS400 might not work under all
circumstances yet.

Successfully tested on a Odroid C2 (S905 GXBB).

Signed-off-by: default avatarHeiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: default avatarKevin Hilman <khilman@baylibre.com>
Tested-by: default avatarKevin Hilman <khilman@baylibre.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 62d721a6

drivers/mmc/host/meson-gx-mmc.c

+11 −0
Original line number Original line Diff line number Diff line
@@ -83,6 +83,7 @@ 
#define   CFG_RC_CC_MASK 0xf

#define   CFG_RC_CC_MASK 0xf

#define   CFG_STOP_CLOCK BIT(22)

#define   CFG_STOP_CLOCK BIT(22)

#define   CFG_CLK_ALWAYS_ON BIT(18)

#define   CFG_CLK_ALWAYS_ON BIT(18)

#define   CFG_CHK_DS BIT(20)

#define   CFG_AUTO_CLK BIT(23)

#define   CFG_AUTO_CLK BIT(23)





#define SD_EMMC_STATUS 0x48

#define SD_EMMC_STATUS 0x48
@@ -408,6 +409,16 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 
	val &= ~(CFG_RC_CC_MASK << CFG_RC_CC_SHIFT);

	val &= ~(CFG_RC_CC_MASK << CFG_RC_CC_SHIFT);

	val |= ilog2(SD_EMMC_CFG_CMD_GAP) << CFG_RC_CC_SHIFT;

	val |= ilog2(SD_EMMC_CFG_CMD_GAP) << CFG_RC_CC_SHIFT;





	val &= ~CFG_DDR;

	if (ios->timing == MMC_TIMING_UHS_DDR50 ||

	    ios->timing == MMC_TIMING_MMC_DDR52 ||

	    ios->timing == MMC_TIMING_MMC_HS400)

		val |= CFG_DDR;



	val &= ~CFG_CHK_DS;

	if (ios->timing == MMC_TIMING_MMC_HS400)

		val |= CFG_CHK_DS;



	writel(val, host->regs + SD_EMMC_CFG);

	writel(val, host->regs + SD_EMMC_CFG);





	if (val != orig)

	if (val != orig)