Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e2028b05 authored by Nandha Kishore Easwaran's avatar Nandha Kishore Easwaran Committed by Gerrit - the friendly Code Review server
Browse files

fw-api: Add E3 headers for qcn9000 

Added qcn9000 headers corresponding to version E3

Change-Id: I782eefb47623f0ad211c0a2233bd64ba7e202f69
parent ff1580fe

hw/qcn9000/mac_tcl_reg_seq_hwioreg.h

+474 −566

File changed.

Preview size limit exceeded, changes collapsed.

hw/qcn9000/msmhwiobase.h

+4 −85
Original line number Diff line number Diff line
@@ -25,9 +25,6 @@ 
*/

/*

  ===========================================================================





  ===========================================================================

*/



/*----------------------------------------------------------------------------
@@ -134,14 +131,6 @@ 
#define BLSP1_BLSP_BASE_SIZE                                        0x00040000

#define BLSP1_BLSP_BASE_PHYS                                        0x01b40000



/*----------------------------------------------------------------------------

 * BASE: CE_WFSS_CE_REG

 *--------------------------------------------------------------------------*/



#define CE_WFSS_CE_REG_BASE                                         0x01b80000

#define CE_WFSS_CE_REG_BASE_SIZE                                    0x0001c000

#define CE_WFSS_CE_REG_BASE_PHYS                                    0x01b80000



/*----------------------------------------------------------------------------

 * BASE: MEMSS_CSR

 *--------------------------------------------------------------------------*/
@@ -206,14 +195,6 @@ 
#define SECURITY_CONTROL_WLAN_BASE_SIZE                             0x00008000

#define SECURITY_CONTROL_WLAN_BASE_PHYS                             0x01e20000



/*----------------------------------------------------------------------------

 * BASE: EDPD_EDPD_CAL_ACC

 *--------------------------------------------------------------------------*/



#define EDPD_EDPD_CAL_ACC_BASE                                      0x01e28000

#define EDPD_EDPD_CAL_ACC_BASE_SIZE                                 0x00004000

#define EDPD_EDPD_CAL_ACC_BASE_PHYS                                 0x01e28000



/*----------------------------------------------------------------------------

 * BASE: CPR_CX_CPR3

 *--------------------------------------------------------------------------*/
@@ -283,7 +264,7 @@ 
 *--------------------------------------------------------------------------*/



#define SYSTEM_NOC_BASE                                             0x01e80000

#define SYSTEM_NOC_BASE_SIZE                                        0x0000a000

#define SYSTEM_NOC_BASE_SIZE                                        0x00003280

#define SYSTEM_NOC_BASE_PHYS                                        0x01e80000



/*----------------------------------------------------------------------------
@@ -291,7 +272,7 @@ 
 *--------------------------------------------------------------------------*/



#define PC_NOC_BASE                                                 0x01f00000

#define PC_NOC_BASE_SIZE                                            0x00004200

#define PC_NOC_BASE_SIZE                                            0x00001180

#define PC_NOC_BASE_PHYS                                            0x01f00000



/*----------------------------------------------------------------------------
@@ -299,7 +280,7 @@ 
 *--------------------------------------------------------------------------*/



#define WLAON_WL_AON_REG_BASE                                       0x01f80000

#define WLAON_WL_AON_REG_BASE_SIZE                                  0x00000708

#define WLAON_WL_AON_REG_BASE_SIZE                                  0x00000704

#define WLAON_WL_AON_REG_BASE_PHYS                                  0x01f80000



/*----------------------------------------------------------------------------
@@ -315,7 +296,7 @@ 
 *--------------------------------------------------------------------------*/



#define PMU_WLAN_PMU_BASE                                           0x01f88000

#define PMU_WLAN_PMU_BASE_SIZE                                      0x000000d4

#define PMU_WLAN_PMU_BASE_SIZE                                      0x00000338

#define PMU_WLAN_PMU_BASE_PHYS                                      0x01f88000



/*----------------------------------------------------------------------------
@@ -326,14 +307,6 @@ 
#define PMU_NOC_BASE_SIZE                                           0x00000080

#define PMU_NOC_BASE_PHYS                                           0x01f8a000



/*----------------------------------------------------------------------------

 * BASE: BT_SEC_REG_SECURITY_CONTROL_BT

 *--------------------------------------------------------------------------*/



#define BT_SEC_REG_SECURITY_CONTROL_BT_BASE                         0x01f90000

#define BT_SEC_REG_SECURITY_CONTROL_BT_BASE_SIZE                    0x00008000

#define BT_SEC_REG_SECURITY_CONTROL_BT_BASE_PHYS                    0x01f90000



/*----------------------------------------------------------------------------

 * BASE: PCIE_ATU_REGION

 *--------------------------------------------------------------------------*/
@@ -358,59 +331,5 @@ 
#define PCIE_ATU_REGION_END_BASE_SIZE                               0x100000000

#define PCIE_ATU_REGION_END_BASE_PHYS                               0x43ffffff



/*----------------------------------------------------------------------------

 * BASE: MEM_SS_RAM_START_ADDRESS

 *--------------------------------------------------------------------------*/



#define MEM_SS_RAM_START_ADDRESS_BASE                               0x1400000

#define MEM_SS_RAM_START_ADDRESS_BASE_SIZE                          0x100000000

#define MEM_SS_RAM_START_ADDRESS_BASE_PHYS                          0x1400000



/*----------------------------------------------------------------------------

 * BASE: MEM_SS_RAM_SIZE

 *--------------------------------------------------------------------------*/

#define MEM_SS_RAM_SIZE_BASE                                        0x003a0000

#define MEM_SS_RAM_SIZE_BASE_SIZE                                   0x100000000

#define MEM_SS_RAM_SIZE_BASE_PHYS                                   0x003a0000



/*----------------------------------------------------------------------------

 * BASE: MEM_SS_RAM_END_ADDRESS

 *--------------------------------------------------------------------------*/



#define MEM_SS_RAM_END_ADDRESS_BASE                                 0x0179ffff

#define MEM_SS_RAM_END_ADDRESS_BASE_SIZE                            0x100000000

#define MEM_SS_RAM_END_ADDRESS_BASE_PHYS                            0x0179ffff



/*----------------------------------------------------------------------------

 * BASE: MEM_SS_ROM_START_ADDRESS

 *--------------------------------------------------------------------------*/



#define MEM_SS_ROM_START_ADDRESS_BASE                               0x00800000

#define MEM_SS_ROM_START_ADDRESS_BASE_SIZE                          0x100000000

#define MEM_SS_ROM_START_ADDRESS_BASE_PHYS                          0x00800000



/*----------------------------------------------------------------------------

 * BASE: MEM_SS_ROM_END_ADDRESS

 *--------------------------------------------------------------------------*/



#define MEM_SS_ROM_END_ADDRESS_BASE                                 0x008bffff

#define MEM_SS_ROM_END_ADDRESS_BASE_SIZE                            0x100000000

#define MEM_SS_ROM_END_ADDRESS_BASE_PHYS                            0x008bffff



/*----------------------------------------------------------------------------

 * BASE: MEM_SS_ROM_SIZE

 *--------------------------------------------------------------------------*/



#define MEM_SS_ROM_SIZE_BASE                                        0x000c0000

#define MEM_SS_ROM_SIZE_BASE_SIZE                                   0x100000000

#define MEM_SS_ROM_SIZE_BASE_PHYS                                   0x000c0000



/*----------------------------------------------------------------------------

 * BASE: QDSP6V67SS_WLAN

 *--------------------------------------------------------------------------*/



#define QDSP6V67SS_WLAN_BASE                                        0x00000000

#define QDSP6V67SS_WLAN_BASE_SIZE                                   0x01000000

#define QDSP6V67SS_WLAN_BASE_PHYS                                   0x00000000



#endif /* __MSMHWIOBASE_H__ */

hw/qcn9000/msmhwioreg.h

deleted100644 → 0
+0 −861

File deleted.

Preview size limit exceeded, changes collapsed.

hw/qcn9000/phyrx_rssi_legacy.h

+59 −9
Original line number Diff line number Diff line
@@ -30,7 +30,7 @@ 
//	3-18	struct receive_rssi_info pre_rssi_info_details;

//	19-34	struct receive_rssi_info preamble_rssi_info_details;

//	35	pre_rssi_comb[7:0], rssi_comb[15:8], normalized_pre_rssi_comb[23:16], normalized_rssi_comb[31:24]

//	36	rssi_comb_ppdu[7:0], rssi_db_to_dbm_offset[15:8], reserved_36a[31:16]

//	36	rssi_comb_ppdu[7:0], rssi_db_to_dbm_offset[15:8], rssi_for_spatial_reuse[23:16], rssi_for_trigger_resp[31:24]

//

// ################ END SUMMARY #################
@@ -53,7 +53,8 @@ struct phyrx_rssi_legacy { 
                      normalized_rssi_comb            :  8; //[31:24]

             uint32_t rssi_comb_ppdu                  :  8, //[7:0]

                      rssi_db_to_dbm_offset           :  8, //[15:8]

                      reserved_36a                    : 16; //[31:16]

                      rssi_for_spatial_reuse          :  8, //[23:16]

                      rssi_for_trigger_resp           :  8; //[31:24]

};



/*
@@ -433,9 +434,43 @@ rssi_db_to_dbm_offset 
			

			<legal all>



reserved_36a

rssi_for_spatial_reuse

			

			<legal 0>

			<legal all>



rssi_for_trigger_resp

			

			RSSI to be used by PDG for transmit (power) selection

			during trigger response, reported as an 8-bit signed value

			

			

			

			The resolution can be: 

			

			1dB or 0.5dB. This is statically configured within the

			PHY and MAC

			

			

			

			In case of 1dB, the Range is:

			

			 -128dB to 127dB

			

			

			

			In case of 0.5dB, the Range is:

			

			 -64dB to 63.5dB

			

			

			

			As per 802.11ax draft 3.3 subsubclauses 28.3.14.2, for

			trigger response, the received power should be measured from

			the non-HE portion of the preamble of the PPDU containing

			the trigger, normalized to 20 MHz, averaged over the

			antennas over which the average pathloss is being computed.

			

			<legal all>

*/
@@ -2250,13 +2285,28 @@ reserved_36a 
#define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_LSB               8

#define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_MASK              0x0000ff00



/* Description		PHYRX_RSSI_LEGACY_36_RESERVED_36A

/* Description		PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE

			

			<legal 0>

			RSSI to be used by HWSCH for transmit (power) selection

			during an SR opportunity, reported as an 8-bit signed value

			

			<legal all>

*/

#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_OFFSET           0x00000090

#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_LSB              16

#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_MASK             0x00ff0000



/* Description		PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP

			

			RSSI to be used by PDG for transmit (power) selection

			during trigger response, reported as an 8-bit signed value

			

			

			<legal all>

*/

#define PHYRX_RSSI_LEGACY_36_RESERVED_36A_OFFSET                     0x00000090

#define PHYRX_RSSI_LEGACY_36_RESERVED_36A_LSB                        16

#define PHYRX_RSSI_LEGACY_36_RESERVED_36A_MASK                       0xffff0000

#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_OFFSET            0x00000090

#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_LSB               24

#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_MASK              0xff000000





#endif // _PHYRX_RSSI_LEGACY_H_

hw/qcn9000/reo_destination_ring.h

+109 −15
Original line number Diff line number Diff line
@@ -31,8 +31,8 @@ 
//	4-5	struct rx_msdu_desc_info rx_msdu_desc_info_details;

//	6	rx_reo_queue_desc_addr_31_0[31:0]

//	7	rx_reo_queue_desc_addr_39_32[7:0], reo_dest_buffer_type[8], reo_push_reason[10:9], reo_error_code[15:11], receive_queue_number[31:16]

//	8	soft_reorder_info_valid[0], reorder_opcode[4:1], reorder_slot_index[12:5], mpdu_fragment_number[16:13], reserved_8a[31:17]

//	9	reserved_9a[31:0]

//	8	soft_reorder_info_valid[0], reorder_opcode[4:1], reorder_slot_index[12:5], mpdu_fragment_number[16:13], captured_msdu_data_size[20:17], sw_exception[21], reserved_8a[31:22]

//	9	reo_destination_struct_signature[31:0]

//	10	reserved_10a[31:0]

//	11	reserved_11a[31:0]

//	12	reserved_12a[31:0]
@@ -58,8 +58,10 @@ struct reo_destination_ring { 
                      reorder_opcode                  :  4, //[4:1]

                      reorder_slot_index              :  8, //[12:5]

                      mpdu_fragment_number            :  4, //[16:13]

                      reserved_8a                     : 15; //[31:17]

             uint32_t reserved_9a                     : 32; //[31:0]

                      captured_msdu_data_size         :  4, //[20:17]

                      sw_exception                    :  1, //[21]

                      reserved_8a                     : 10; //[31:22]

             uint32_t reo_destination_struct_signature: 32; //[31:0]

             uint32_t reserved_10a                    : 32; //[31:0]

             uint32_t reserved_11a                    : 32; //[31:0]

             uint32_t reserved_12a                    : 32; //[31:0]
@@ -218,6 +220,9 @@ reo_error_code 


receive_queue_number

			

			This field in NOT valid (should be set to 0), when

			SW_exception is set.

			

			This field indicates the REO MPDU reorder queue ID from

			which this frame originated. This field is populated from a

			field with the same name in the RX_REO_QUEUE descriptor.
@@ -226,6 +231,9 @@ receive_queue_number 


soft_reorder_info_valid

			

			This field in NOT valid (should be set to 0), when

			SW_exception is set.

			

			When set, REO has been instructed to not perform the

			actual re-ordering of frames for this queue, but just to

			insert the reorder opcodes
@@ -306,15 +314,50 @@ mpdu_fragment_number 
			

			

			

			<legal all>



captured_msdu_data_size

			

			The number of following REO_DESTINATION STRUCTs that

			have been replaced with msdu_data extracted from the

			msdu_buffer and copied into the ring for easy FW/SW access.

			

			Note that it is possible that these STRUCTs wrap around

			the end of the ring.

			

			Feature supported only in HastingsPrime

			

			<legal 0-4>



sw_exception

			

			This field has the same setting as the SW_exception

			field in the corresponding REO_entrance_ring descriptor.

			

			When set, the REO entrance descriptor is generated by

			FW, and the MPDU was processed in the following way:

			

			- NO re-order function is needed.

			

			- MPDU delinking is determined by the setting of

			Entrance ring field: SW_excection_mpdu_delink

			

			- Destination ring selection is based on the setting of

			

			Feature supported only in HastingsPrime

			

			<legal all>



reserved_8a

			

			<legal 0>



reserved_9a

reo_destination_struct_signature

			

			<legal 0>

			Set to value 0x8888_88888 when msdu capture mode is

			enabled for this ring (supported only in HastingsPrime)

			

			<legal 0, 2290649224 >



reserved_10a
@@ -919,10 +962,12 @@ looping_count 
			the REO2FW ring

			

			<enum 7 reo_destination_sw5> Reo will push the frame

			into the REO2SW5 ring 

			into the REO2SW5 ring (REO remaps this in chips without

			REO2SW5 ring, e.g. Pine) 

			

			<enum 8 reo_destination_sw6> Reo will push the frame

			into the REO2SW6 ring 

			into the REO2SW6 ring (REO remaps this in chips without

			REO2SW6 ring, e.g. Pine)

			

			 <enum 9 reo_destination_9> REO remaps this <enum 10

			reo_destination_10> REO remaps this
@@ -1229,6 +1274,9 @@ looping_count 


/* Description		REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER

			

			This field in NOT valid (should be set to 0), when

			SW_exception is set.

			

			This field indicates the REO MPDU reorder queue ID from

			which this frame originated. This field is populated from a

			field with the same name in the RX_REO_QUEUE descriptor.
@@ -1241,6 +1289,9 @@ looping_count 


/* Description		REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID

			

			This field in NOT valid (should be set to 0), when

			SW_exception is set.

			

			When set, REO has been instructed to not perform the

			actual re-ordering of frames for this queue, but just to

			insert the reorder opcodes
@@ -1339,21 +1390,64 @@ looping_count 
#define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_LSB              13

#define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_MASK             0x0001e000



/* Description		REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE

			

			The number of following REO_DESTINATION STRUCTs that

			have been replaced with msdu_data extracted from the

			msdu_buffer and copied into the ring for easy FW/SW access.

			

			Note that it is possible that these STRUCTs wrap around

			the end of the ring.

			

			Feature supported only in HastingsPrime

			

			<legal 0-4>

*/

#define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_OFFSET        0x00000020

#define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_LSB           17

#define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_MASK          0x001e0000



/* Description		REO_DESTINATION_RING_8_SW_EXCEPTION

			

			This field has the same setting as the SW_exception

			field in the corresponding REO_entrance_ring descriptor.

			

			When set, the REO entrance descriptor is generated by

			FW, and the MPDU was processed in the following way:

			

			- NO re-order function is needed.

			

			- MPDU delinking is determined by the setting of

			Entrance ring field: SW_excection_mpdu_delink

			

			- Destination ring selection is based on the setting of

			

			Feature supported only in HastingsPrime

			

			<legal all>

*/

#define REO_DESTINATION_RING_8_SW_EXCEPTION_OFFSET                   0x00000020

#define REO_DESTINATION_RING_8_SW_EXCEPTION_LSB                      21

#define REO_DESTINATION_RING_8_SW_EXCEPTION_MASK                     0x00200000



/* Description		REO_DESTINATION_RING_8_RESERVED_8A

			

			<legal 0>

*/

#define REO_DESTINATION_RING_8_RESERVED_8A_OFFSET                    0x00000020

#define REO_DESTINATION_RING_8_RESERVED_8A_LSB                       17

#define REO_DESTINATION_RING_8_RESERVED_8A_MASK                      0xfffe0000

#define REO_DESTINATION_RING_8_RESERVED_8A_LSB                       22

#define REO_DESTINATION_RING_8_RESERVED_8A_MASK                      0xffc00000



/* Description		REO_DESTINATION_RING_9_RESERVED_9A

/* Description		REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE

			

			<legal 0>

			Set to value 0x8888_88888 when msdu capture mode is

			enabled for this ring (supported only in HastingsPrime)

			

			<legal 0, 2290649224 >

*/

#define REO_DESTINATION_RING_9_RESERVED_9A_OFFSET                    0x00000024

#define REO_DESTINATION_RING_9_RESERVED_9A_LSB                       0

#define REO_DESTINATION_RING_9_RESERVED_9A_MASK                      0xffffffff

#define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x00000024

#define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_LSB  0

#define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0xffffffff



/* Description		REO_DESTINATION_RING_10_RESERVED_10A