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Commit e18e2a00 authored by David S. Miller's avatar David S. Miller
Browse files

[SPARC64]: Move over to GENERIC_HARDIRQS.



This is the long overdue conversion of sparc64 over to
the generic IRQ layer.

The kernel image is slightly larger, but the BSS is ~60K
smaller due to the reduced size of struct ino_bucket.

A lot of IRQ implementation details, including ino_bucket,
were moved out of asm-sparc64/irq.h and are now private to
arch/sparc64/kernel/irq.c, and most of the code in irq.c
totally disappeared.

One thing that's different at the moment is IRQ distribution,
we do it at enable_irq() time.  If the cpu mask is ALL then
we round-robin using a global rotating cpu counter, else
we pick the first cpu in the mask to support single cpu
targetting.  This is similar to what powerpc's XICS IRQ
support code does.

This works fine on my UP SB1000, and the SMP build goes
fine and runs on that machine, but lots of testing on
different setups is needed.

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 8047e247
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+4 −0
Original line number Diff line number Diff line
@@ -87,6 +87,10 @@ config SYSVIPC_COMPAT
	depends on COMPAT && SYSVIPC
	default y

config GENERIC_HARDIRQS
	bool
	default y

menu "General machine setup"

config SMP
+1 −1
Original line number Diff line number Diff line
@@ -157,7 +157,7 @@ unsigned int sun4v_vdev_device_interrupt(unsigned int dev_node)
		return 0;
	}

	return sun4v_build_irq(sun4v_vdev_devhandle, irq, 0);
	return sun4v_build_irq(sun4v_vdev_devhandle, irq);
}

static const char *cpu_mid_prop(void)
+1 −1
Original line number Diff line number Diff line
@@ -432,7 +432,7 @@ do_ivec:
	membar		#Sync

	sethi		%hi(ivector_table), %g2
	sllx		%g3, 5, %g3
	sllx		%g3, 3, %g3
	or		%g2, %lo(ivector_table), %g2
	add		%g2, %g3, %g3

+284 −673

File changed.

Preview size limit exceeded, changes collapsed.

+0 −38
Original line number Diff line number Diff line
@@ -47,12 +47,6 @@ struct pci_controller_info *pci_controller_root = NULL;
/* Each PCI controller found gets a unique index. */
int pci_num_controllers = 0;

/* At boot time the user can give the kernel a command
 * line option which controls if and how PCI devices
 * are reordered at PCI bus probing time.
 */
int pci_device_reorder = 0;

volatile int pci_poke_in_progress;
volatile int pci_poke_cpu = -1;
volatile int pci_poke_faulted;
@@ -316,27 +310,6 @@ static void __init pci_scan_each_controller_bus(void)
		p->scan_bus(p);
}

/* Reorder the pci_dev chain, so that onboard devices come first
 * and then come the pluggable cards.
 */
static void __init pci_reorder_devs(void)
{
	struct list_head *pci_onboard = &pci_devices;
	struct list_head *walk = pci_onboard->next;

	while (walk != pci_onboard) {
		struct pci_dev *pdev = pci_dev_g(walk);
		struct list_head *walk_next = walk->next;

		if (pdev->irq && (__irq_ino(pdev->irq) & 0x20)) {
			list_del(walk);
			list_add(walk, pci_onboard);
		}

		walk = walk_next;
	}
}

extern void clock_probe(void);
extern void power_init(void);

@@ -348,9 +321,6 @@ static int __init pcibios_init(void)

	pci_scan_each_controller_bus();

	if (pci_device_reorder)
		pci_reorder_devs();

	isa_init();
	ebus_init();
	clock_probe();
@@ -441,14 +411,6 @@ EXPORT_SYMBOL(pcibios_bus_to_resource);

char * __init pcibios_setup(char *str)
{
	if (!strcmp(str, "onboardfirst")) {
		pci_device_reorder = 1;
		return NULL;
	}
	if (!strcmp(str, "noreorder")) {
		pci_device_reorder = 0;
		return NULL;
	}
	return str;
}

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