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Commit e16a2c7a authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

pinctrl: sh-pfc: Drop width parameter of sh_pfc_{read,write}_reg() 



On modern Renesas SoCs, all PFC registers are 32-bit, and all callers of
sh_pfc_{read,write}_reg() already operate on 32-bit registers only.
Hence make the 32-bit width implicit, and rename the functions to
sh_pfc_{read,write}() to shorten lines.

All accesses to 8-bit or 16-bit registers are still done using
sh_pfc_{read,write}_raw_reg().

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
parent 35406b1f

drivers/pinctrl/sh-pfc/core.c

+4 −4
Original line number Diff line number Diff line
@@ -175,19 +175,19 @@ void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width, 
	BUG();

}



u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width)

u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)

{

	return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), width);

	return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32);

}



void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data)

void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)

{

	if (pfc->info->unlock_reg)

		sh_pfc_write_raw_reg(

			sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,

			~data);



	sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), width, data);

	sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data);

}



static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,

drivers/pinctrl/sh-pfc/core.h

+2 −3
Original line number Diff line number Diff line
@@ -26,9 +26,8 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc); 
u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width);

void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,

			  u32 data);

u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width);

void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width,

		      u32 data);

u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg);

void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data);



int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);

int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);

drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c

+6 −6
Original line number Diff line number Diff line
@@ -5671,9 +5671,9 @@ static unsigned int r8a7795es1_pinmux_get_bias(struct sh_pfc *pfc, 
	reg = info->reg;

	bit = BIT(info->bit);



	if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))

	if (!(sh_pfc_read(pfc, PUEN + reg) & bit))

		return PIN_CONFIG_BIAS_DISABLE;

	else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)

	else if (sh_pfc_read(pfc, PUD + reg) & bit)

		return PIN_CONFIG_BIAS_PULL_UP;

	else

		return PIN_CONFIG_BIAS_PULL_DOWN;
@@ -5694,16 +5694,16 @@ static void r8a7795es1_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, 
	reg = info->reg;

	bit = BIT(info->bit);



	enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;

	enable = sh_pfc_read(pfc, PUEN + reg) & ~bit;

	if (bias != PIN_CONFIG_BIAS_DISABLE)

		enable |= bit;



	updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit;

	updown = sh_pfc_read(pfc, PUD + reg) & ~bit;

	if (bias == PIN_CONFIG_BIAS_PULL_UP)

		updown |= bit;



	sh_pfc_write_reg(pfc, PUD + reg, 32, updown);

	sh_pfc_write_reg(pfc, PUEN + reg, 32, enable);

	sh_pfc_write(pfc, PUD + reg, updown);

	sh_pfc_write(pfc, PUEN + reg, enable);

}



static const struct sh_pfc_soc_operations r8a7795es1_pinmux_ops = {

drivers/pinctrl/sh-pfc/pfc-r8a7795.c

+6 −6
Original line number Diff line number Diff line
@@ -5660,9 +5660,9 @@ static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc, 
	reg = info->reg;

	bit = BIT(info->bit);



	if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))

	if (!(sh_pfc_read(pfc, PUEN + reg) & bit))

		return PIN_CONFIG_BIAS_DISABLE;

	else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)

	else if (sh_pfc_read(pfc, PUD + reg) & bit)

		return PIN_CONFIG_BIAS_PULL_UP;

	else

		return PIN_CONFIG_BIAS_PULL_DOWN;
@@ -5683,16 +5683,16 @@ static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, 
	reg = info->reg;

	bit = BIT(info->bit);



	enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;

	enable = sh_pfc_read(pfc, PUEN + reg) & ~bit;

	if (bias != PIN_CONFIG_BIAS_DISABLE)

		enable |= bit;



	updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit;

	updown = sh_pfc_read(pfc, PUD + reg) & ~bit;

	if (bias == PIN_CONFIG_BIAS_PULL_UP)

		updown |= bit;



	sh_pfc_write_reg(pfc, PUD + reg, 32, updown);

	sh_pfc_write_reg(pfc, PUEN + reg, 32, enable);

	sh_pfc_write(pfc, PUD + reg, updown);

	sh_pfc_write(pfc, PUEN + reg, enable);

}



static const struct soc_device_attribute r8a7795es1[] = {

drivers/pinctrl/sh-pfc/pfc-r8a7796.c

+6 −6
Original line number Diff line number Diff line
@@ -5724,9 +5724,9 @@ static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc, 
	reg = info->reg;

	bit = BIT(info->bit);



	if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))

	if (!(sh_pfc_read(pfc, PUEN + reg) & bit))

		return PIN_CONFIG_BIAS_DISABLE;

	else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)

	else if (sh_pfc_read(pfc, PUD + reg) & bit)

		return PIN_CONFIG_BIAS_PULL_UP;

	else

		return PIN_CONFIG_BIAS_PULL_DOWN;
@@ -5747,16 +5747,16 @@ static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, 
	reg = info->reg;

	bit = BIT(info->bit);



	enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;

	enable = sh_pfc_read(pfc, PUEN + reg) & ~bit;

	if (bias != PIN_CONFIG_BIAS_DISABLE)

		enable |= bit;



	updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit;

	updown = sh_pfc_read(pfc, PUD + reg) & ~bit;

	if (bias == PIN_CONFIG_BIAS_PULL_UP)

		updown |= bit;



	sh_pfc_write_reg(pfc, PUD + reg, 32, updown);

	sh_pfc_write_reg(pfc, PUEN + reg, 32, enable);

	sh_pfc_write(pfc, PUD + reg, updown);

	sh_pfc_write(pfc, PUEN + reg, enable);

}



static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {