Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e0f0eae8 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "msm: ipa3: Enable QDSS IPA offload"

parents aeba8e72 e4b0a93f
Loading
Loading
Loading
Loading
+1 −1
Original line number Diff line number Diff line
@@ -542,7 +542,7 @@
		qcom,ipa-hw-mode = <0>;
		qcom,ee = <0>;
		qcom,use-ipa-tethering-bridge;
		qcom,mhi-event-ring-id-limits = <9 11>; /* start and end */
		qcom,mhi-event-ring-id-limits = <9 14>; /* start and end */
		qcom,modem-cfg-emb-pipe-flt;
		qcom,use-ipa-pm;
		qcom,arm-smmu;
+4 −0
Original line number Diff line number Diff line
@@ -220,6 +220,10 @@ const char *ipa_clients_strings[IPA_CLIENT_MAX] = {
	__stringify(IPA_CLIENT_MHI2_CONS),
	__stringify(IPA_CLIENT_Q6_CV2X_PROD),
	__stringify(IPA_CLIENT_Q6_CV2X_CONS),
	__stringify(IPA_CLIENT_MHI_QMAP_PROD),
	__stringify(IPA_CLIENT_MHI_QMAP_CONS),
	__stringify(RESERVERD_PROD_110),
	__stringify(IPA_CLIENT_MHI_QDSS_CONS),
};

/**
+3 −3
Original line number Diff line number Diff line
/* Copyright (c) 2015, 2017-2019 The Linux Foundation. All rights reserved.
/* Copyright (c) 2015, 2017-2020 The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
@@ -63,8 +63,8 @@
#define IPA_MHI_SUSPEND_SLEEP_MIN 900
#define IPA_MHI_SUSPEND_SLEEP_MAX 1100

#define IPA_MHI_MAX_UL_CHANNELS 2
#define IPA_MHI_MAX_DL_CHANNELS 3
#define IPA_MHI_MAX_UL_CHANNELS 3
#define IPA_MHI_MAX_DL_CHANNELS 5

/* bit #40 in address should be asserted for MHI transfers over pcie */
#define IPA_MHI_CLIENT_HOST_ADDR_COND(addr) \
+2 −1
Original line number Diff line number Diff line
@@ -69,7 +69,8 @@ int ipa3_enable_data_path(u32 clnt_hdl)
		 * on other end from IPA hw.
		 */
		if ((ep->client == IPA_CLIENT_USB_DPL_CONS) ||
				(ep->client == IPA_CLIENT_MHI_DPL_CONS))
				(ep->client == IPA_CLIENT_MHI_DPL_CONS) ||
				(ep->client == IPA_CLIENT_MHI_QDSS_CONS))
			holb_cfg.en = IPA_HOLB_TMR_EN;
		else
			holb_cfg.en = IPA_HOLB_TMR_DIS;
+19 −1
Original line number Diff line number Diff line
@@ -2602,6 +2602,12 @@ static const struct ipa_ep_configuration ipa3_ep_mapping
			IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,
			QMB_MASTER_SELECT_DDR,
			{ 10, 13, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },
	[IPA_4_5_MHI][IPA_CLIENT_MHI_QMAP_PROD] = {
			true, IPA_v4_5_MHI_GROUP_PCIE,
			false,
			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
			QMB_MASTER_SELECT_PCIE,
			{ 3, 5, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 } },
	/* Only for test purpose */
	[IPA_4_5_MHI][IPA_CLIENT_TEST_PROD]           = {
			true, QMB_MASTER_SELECT_DDR,
@@ -2688,7 +2694,18 @@ static const struct ipa_ep_configuration ipa3_ep_mapping
			IPA_DPS_HPS_SEQ_TYPE_INVALID,
			QMB_MASTER_SELECT_PCIE,
			{ 22, 2, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5_MHI][IPA_CLIENT_MHI_QMAP_CONS] = {
			true, IPA_v4_5_MHI_GROUP_PCIE,
			false,
			IPA_DPS_HPS_SEQ_TYPE_INVALID,
			QMB_MASTER_SELECT_PCIE,
			{ 30, 6, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 } },
	[IPA_4_5_MHI][IPA_CLIENT_MHI_QDSS_CONS] = {
			true, IPA_v4_5_MHI_GROUP_PCIE,
			false,
			IPA_DPS_HPS_SEQ_TYPE_INVALID,
			QMB_MASTER_SELECT_PCIE,
			{ 24, 3, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 } },
	/* Dummy consumer (pipe 31) is used in L2TP rt rule */
	[IPA_4_5_MHI][IPA_CLIENT_DUMMY_CONS]          = {
			true, QMB_MASTER_SELECT_DDR,
@@ -3527,6 +3544,7 @@ bool ipa3_should_pipe_be_suspended(enum ipa_client_type client)
	if (client == IPA_CLIENT_USB_CONS     ||
		client == IPA_CLIENT_USB2_CONS    ||
	    client == IPA_CLIENT_USB_DPL_CONS ||
	    client == IPA_CLIENT_MHI_QDSS_CONS ||
	    client == IPA_CLIENT_MHI_CONS     ||
	    client == IPA_CLIENT_MHI_DPL_CONS ||
	    client == IPA_CLIENT_HSIC1_CONS   ||
Loading