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Commit e0e3e1a3 authored by Viken Dadhaniya's avatar Viken Dadhaniya Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add support for HSUART for RS232 usecase 



Add UART setting for implement RS232 driver.
This usecase is required for customer hence enabled it.

Change-Id: I45443d68a9898505f21e1033e9ee054fa0cc5404
Signed-off-by: default avatarViken Dadhaniya <quic_vdadhani@quicinc.com>
parent ad8e8306

arch/arm64/boot/dts/qcom/trinket-facepay.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -400,3 +400,7 @@ 
		report_type = <1>;

	};

};



&qupv3_se6_4uart {

	status = "ok";

};

arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi

+41 −0
Original line number Diff line number Diff line
@@ -461,6 +461,47 @@ 
			};

		};



		qupv3_se6_4uart_pins: qupv3_se6_4uart_pins {

			qupv3_se6_ctsrx: qupv3_se6_ctsrx {

				mux {

					pins = "gpio30", "gpio33";

					function = "qup11";

				};



				config {

					pins = "gpio30", "gpio33";

					drive-strength = <2>;

					bias-no-pull;

				};

			};



			qupv3_se6_rts: qupv3_se6_rts {

				mux {

					pins = "gpio31";

					function = "qup11";

				};



				config {

					pins = "gpio31";

					drive-strength = <2>;

					bias-pull-down;

				};

			};



			qupv3_se6_tx: qupv3_se6_tx {

				mux {

					pins = "gpio32";

					function = "qup11";

				};



				config {

					pins = "gpio32";

					drive-strength = <2>;

					bias-pull-up;

				};

			};

		};



		qupv3_se9_4uart_pins: qupv3_se9_4uart_pins {

			qupv3_se9_ctsrx: qupv3_se9_ctsrx {

				mux {

arch/arm64/boot/dts/qcom/trinket-qupv3.dtsi

+18 −0
Original line number Diff line number Diff line
@@ -269,6 +269,24 @@ 
		status = "disabled";

	};



	qupv3_se6_4uart: qcom,qup_uart@0x4c84000 {

		compatible = "qcom,msm-geni-serial-hs";

		reg = <0x4c84000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,

			<&qupv3_se6_tx>;

		pinctrl-1 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,

			<&qupv3_se6_tx>;

		interrupts = <GIC_SPI 309 0>;

		qcom,wrapper-core = <&qupv3_1>;

		status = "disabled";

	};



	/* I2C */

	qupv3_se5_i2c: i2c@4c80000 {

		compatible = "qcom,i2c-geni";