Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e0c3f3f3 authored by Xiaojun Sang's avatar Xiaojun Sang Committed by Gerrit - the friendly Code Review server
Browse files

ASoC: codecs: fix inconsistency of boost state register value 



Use hardware default value for boost state in regmap.
Use correct mask for initial value of boost state.

Change-Id: Ia8b707ba0128662d47059d25325693bc8eaff723
Signed-off-by: default avatarXiaojun Sang <xsang@codeaurora.org>
parent 253f1479

asoc/codecs/msm_sdw/msm_sdw_cdc.c

+2 −2
Original line number Diff line number Diff line
@@ -1705,8 +1705,8 @@ static const struct msm_sdw_reg_mask_val msm_sdw_reg_init[] = { 
	{MSM_SDW_BOOST1_BOOST_CFG1, 0x3F, 0x12},

	{MSM_SDW_BOOST1_BOOST_CFG2, 0x1C, 0x08},

	{MSM_SDW_COMPANDER8_CTL7, 0x1E, 0x18},

	{MSM_SDW_BOOST0_BOOST_CTL, 0x70, 0x58},

	{MSM_SDW_BOOST1_BOOST_CTL, 0x70, 0x58},

	{MSM_SDW_BOOST0_BOOST_CTL, 0x7C, 0x58},

	{MSM_SDW_BOOST1_BOOST_CTL, 0x7C, 0x58},

	{MSM_SDW_RX7_RX_PATH_CFG1, 0x08, 0x08},

	{MSM_SDW_RX8_RX_PATH_CFG1, 0x08, 0x08},

	{MSM_SDW_TOP_TOP_CFG1, 0x02, 0x02},

asoc/codecs/msm_sdw/msm_sdw_regmap.c

+2 −2
Original line number Diff line number Diff line
@@ -65,11 +65,11 @@ static const struct reg_default msm_sdw_defaults[] = { 
	{ MSM_SDW_RX8_RX_PATH_MIX_SEC1, 0x00 },

	/* Page #12 registers */

	{ MSM_SDW_BOOST0_BOOST_PATH_CTL, 0x00 },

	{ MSM_SDW_BOOST0_BOOST_CTL, 0xba },

	{ MSM_SDW_BOOST0_BOOST_CTL, 0xb2 },

	{ MSM_SDW_BOOST0_BOOST_CFG1, 0x00 },

	{ MSM_SDW_BOOST0_BOOST_CFG2, 0x00 },

	{ MSM_SDW_BOOST1_BOOST_PATH_CTL, 0x00 },

	{ MSM_SDW_BOOST1_BOOST_CTL, 0xba },

	{ MSM_SDW_BOOST1_BOOST_CTL, 0xb2 },

	{ MSM_SDW_BOOST1_BOOST_CFG1, 0x00 },

	{ MSM_SDW_BOOST1_BOOST_CFG2, 0x00 },

	{ MSM_SDW_AHB_BRIDGE_WR_DATA_0, 0x00 },

asoc/codecs/wcd9335-regmap.c

+2 −2
Original line number Diff line number Diff line
@@ -1213,11 +1213,11 @@ static const struct reg_default wcd9335_defaults[] = { 
	{ WCD9335_CDC_CLSH_TEST1,                         0x00 },

	{ WCD9335_CDC_CLSH_OVR_VREF,                      0x00 },

	{ WCD9335_CDC_BOOST0_BOOST_PATH_CTL,              0x00 },

	{ WCD9335_CDC_BOOST0_BOOST_CTL,                   0xba },

	{ WCD9335_CDC_BOOST0_BOOST_CTL,                   0xb2 },

	{ WCD9335_CDC_BOOST0_BOOST_CFG1,                  0x00 },

	{ WCD9335_CDC_BOOST0_BOOST_CFG2,                  0x00 },

	{ WCD9335_CDC_BOOST1_BOOST_PATH_CTL,              0x00 },

	{ WCD9335_CDC_BOOST1_BOOST_CTL,                   0xba },

	{ WCD9335_CDC_BOOST1_BOOST_CTL,                   0xb2 },

	{ WCD9335_CDC_BOOST1_BOOST_CFG1,                  0x00 },

	{ WCD9335_CDC_BOOST1_BOOST_CFG2,                  0x00 },

	{ WCD9335_SWR_AHB_BRIDGE_WR_DATA_0,               0x00 },

asoc/codecs/wcd9335.c

+2 −2
Original line number Diff line number Diff line
@@ -12405,8 +12405,8 @@ static const struct tasha_reg_mask_val tasha_codec_reg_init_common_val[] = { 
	{WCD9335_CDC_CLSH_K2_MSB, 0x0F, 0x00},

	{WCD9335_CDC_CLSH_K2_LSB, 0xFF, 0x60},

	{WCD9335_CPE_SS_DMIC_CFG, 0x80, 0x00},

	{WCD9335_CDC_BOOST0_BOOST_CTL, 0x70, 0x58},

	{WCD9335_CDC_BOOST1_BOOST_CTL, 0x70, 0x58},

	{WCD9335_CDC_BOOST0_BOOST_CTL, 0x7C, 0x58},

	{WCD9335_CDC_BOOST1_BOOST_CTL, 0x7C, 0x58},

	{WCD9335_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08},

	{WCD9335_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08},

	{WCD9335_ANA_LO_1_2, 0x3C, 0X3C},

asoc/codecs/wcd934x/wcd934x-regmap.c

+2 −2
Original line number Diff line number Diff line
@@ -1248,11 +1248,11 @@ static const struct reg_default wcd934x_defaults[] = { 
	{ WCD934X_CDC_CLSH_TEST1,                          0x00 },

	{ WCD934X_CDC_CLSH_OVR_VREF,                       0x00 },

	{ WCD934X_CDC_BOOST0_BOOST_PATH_CTL,               0x00 },

	{ WCD934X_CDC_BOOST0_BOOST_CTL,                    0xba },

	{ WCD934X_CDC_BOOST0_BOOST_CTL,                    0xb2 },

	{ WCD934X_CDC_BOOST0_BOOST_CFG1,                   0x00 },

	{ WCD934X_CDC_BOOST0_BOOST_CFG2,                   0x00 },

	{ WCD934X_CDC_BOOST1_BOOST_PATH_CTL,               0x00 },

	{ WCD934X_CDC_BOOST1_BOOST_CTL,                    0xba },

	{ WCD934X_CDC_BOOST1_BOOST_CTL,                    0xb2 },

	{ WCD934X_CDC_BOOST1_BOOST_CFG1,                   0x00 },

	{ WCD934X_CDC_BOOST1_BOOST_CFG2,                   0x00 },

	{ WCD934X_CDC_VBAT_VBAT_PATH_CTL,                  0x00 },